receiving a sealant. Preferably the signal pins pass
METHOD OF MAKING THREE DIMENSIONAL through the metallic layer without making electrical
INTEGRATED CIRCUIT INTERCONNECT contact by being smaller than the openings in the metal
MODULE lic layer. Some of the signal pins may provide an electri
5 cal connection between integrated circuits in different
This is a continuation of application Ser. No. sijces preferably the middle layer extends inwardly
07/958,974, filed Oct. 9, 1992, which is a division of Ser. closer to the si ^ ms ^ the other k for ease of
No. 07/753,504, filed Sep. 3, 1991, both abandoned. ... conn^tion therebetween.
BACKGROUND OF THE INVENTION 1Q Yet a still further object of the present invention is a
_ . . .. • i- * i * ^ j- method of making a three dimensional IC interconnect
The present invention is directed to a three dimen- , , ,. , » ,. ,
sional integrated circuit (IC) interconnect module by mod^ which mcludes makmS a ?lmah? of slices hav
providing a fully interconnected module with a plural- m§ at, least one integrated circuit with a p urahty of
ity of chips. One or more chips are mounted on a sepa- input/output pads and a lead interconnect electrically
rate slice, each slice is individually tested, and the slices 15 connected to each pad. The lead interconnects termi
are assembled by stacking them one on top of another. nate at various locations within the periphery of the
This module approach will produce a low cost, moder- slices and surround the integrated circuits. The method
ate performance package which will hold an entire chip includes testing each slice individually for testing the
set and may have a standard pin grid array (PGA) or integrated circuits and the lead interconnects prior to
quad flat pack footprint for mounting on a printed cir- 20 assembly. The method thereafter includes stacking the
cuit board. slices together and then aligning a plurality of signal
The method of manufacturing allows each compo- connections extending transversely through the plural
nent to be tested individually after mounting and prior ity of slices within the periphery of the slices and sur
to assembly. It provides for the interconnect leads to be rounding the integrated circuits, electrically connecting
accessible for testing and provides an assembly check 25 the lead interconnects to the signal connections, and
test method for testing during the manufacturing pro- testing the stacked slices through the signal connec
cess. The manufacturing process should provide an tions.
extremely high yield module, and the finished module ^ method further mcludes pr0viding a plurality of
allows testing using traditional approaches. openings in each slice in which one of the openings is
SUMMARY ^ positioned adjacent to the termination of each lead in
„ ^ ... ,. terconnect and providing a plurality of parallel extendThe present invention is directed to a three dimen- , r ^ • _, v sional IC module which includes a plurality of verti- "WjagTM* connection puis, and stacking the slices locally stacked slices. Each slice includes at least one Sfff bv T-f** °PemnSs over the ^ integrated circuit having a plurality of input/output 35 bly the method mcludes electrically connecrmg the lead pads and a lead interconnect electrically connected to interconnects to the puis by heating the pms and soldereach pad. A plurality of signal connections extend trans- mS the interconnects and pins together. Preferably the versely through the inside of all of the slices and sur- testing step includes testing each slice individually by rounds the integrated circuit, and one of the connec- first testing only the lead interconnects and thereafter tions are connected to each of the lead interconnects. 40 testing the combination of lead interconnects and inteThis structure provides shorter connecting lines with grated circuits.
lower parasitics because the connections are made Another object of the present invention is providing
closely adjacent to the integrated circuits. a plurality of solder filled openings in each slice, one of
An object of the present invention is wherein the said openings positioned adjacent the termination of
slices are ceramic and the signal connections are stacked 45 each lead interconnect, and heating the stacked to
in aligned metal filled vias which are connected to- gether slices for connecting the solder filled openings
gether to form the signal connections. together forming the signal connections.
Still a further object is wherein the lead connects In one form 0f the invention the slices are ceramic
include a film strip position between slices providing an md tne iead interconnects are formed by placing a film
electrical interconnection between the vias and the 50 0f interconnect circuitry between ceramic slices.
Pads- ,„',,. Yet in another form of the invention, the slices are
In another form of the invention, each slice mcludes fonned b a bottom metauic layer, a middle
a middle layer having at least one mtegrated circuit j havin ^ mt ted circuit with a lurality of
with a plurahty of input/output pads and a lead inter- m^ * ^ a mation j Mso>
connect electrically connected to each pad, a metallic 55 r . r r . . \. . * , , .
. ,. . c., i i openings are provided m all of the layers within their
layer adjacent one side of the middle layer for support- ■ , , ^ ■ . 1 , ■
ing the middle layer and providing a heat spreader, and P^phery and surrounding tiie integrated circuits,
an encapsulation layer adjacent to second side of the ^A stlU obJf1 of the Present invention is
middle layer. The middle, metauic and encapsulation wherem the mtegrated circuits have mput protection
layers include a plurahty of openings within the layers 60 dlodes at each Pad and the testing mcludes applying a
and surrounding the integrated circuits. A plurahty of negative voltage to each of the lead interconnects when
signal pins are provided, each of which extend through testing each slice, and measuring the current drawn for
an opening in each layer and through the slices. One each of the interconnects.
end of the pin is connectable to an electronic compo- Other and further objects, features and advantages
nent and one of the pins is electrically connected to 65 will be apparent from the following description of pres
each of the lead interconnects, but are insulated from ently preferred embodiments of the invention, given for
the metallic layer. Preferably the encapsulation layer the purpose of disclosure, and taken in conjunction with
includes a recess mating with the integrated circuit for the accompanying drawings.