Patent US5383269 - Method of making three dimensional integrated circuit interconnect module

1 2

receiving a sealant. Preferably the signal pins pass

METHOD OF MAKING THREE DIMENSIONAL through the metallic layer without making electrical

INTEGRATED CIRCUIT INTERCONNECT contact by being smaller than the openings in the metal

MODULE lic layer. Some of the signal pins may provide an electri

5 cal connection between integrated circuits in different

This is a continuation of application Ser. No. sijces preferably the middle layer extends inwardly

07/958,974, filed Oct. 9, 1992, which is a division of Ser. closer to the si ^ ms ^ the other k for ease of

No. 07/753,504, filed Sep. 3, 1991, both abandoned. ... conn^tion therebetween.

BACKGROUND OF THE INVENTION 1Q Yet a still further object of the present invention is a

_ . . .. • i- * i * ^ j- method of making a three dimensional IC interconnect

The present invention is directed to a three dimen- , , ,. , » ,. ,

sional integrated circuit (IC) interconnect module by mod^ which mcludes makmS a ?lmah? of slices hav

providing a fully interconnected module with a plural- m§ at, least one integrated circuit with a p urahty of

ity of chips. One or more chips are mounted on a sepa- input/output pads and a lead interconnect electrically

rate slice, each slice is individually tested, and the slices 15 connected to each pad. The lead interconnects termi

are assembled by stacking them one on top of another. nate at various locations within the periphery of the

This module approach will produce a low cost, moder- slices and surround the integrated circuits. The method

ate performance package which will hold an entire chip includes testing each slice individually for testing the

set and may have a standard pin grid array (PGA) or integrated circuits and the lead interconnects prior to

quad flat pack footprint for mounting on a printed cir- 20 assembly. The method thereafter includes stacking the

cuit board. slices together and then aligning a plurality of signal

The method of manufacturing allows each compo- connections extending transversely through the plural

nent to be tested individually after mounting and prior ity of slices within the periphery of the slices and sur

to assembly. It provides for the interconnect leads to be rounding the integrated circuits, electrically connecting

accessible for testing and provides an assembly check 25 the lead interconnects to the signal connections, and

test method for testing during the manufacturing pro- testing the stacked slices through the signal connec

cess. The manufacturing process should provide an tions.

extremely high yield module, and the finished module ^ method further mcludes pr0viding a plurality of

allows testing using traditional approaches. openings in each slice in which one of the openings is

SUMMARY ^ positioned adjacent to the termination of each lead in

„ ^ ... ,. terconnect and providing a plurality of parallel extendThe present invention is directed to a three dimen- , r ^ • _, v sional IC module which includes a plurality of verti- "WjagTM* connection puis, and stacking the slices locally stacked slices. Each slice includes at least one Sfff bv T-f** °PemnSs over the ^ integrated circuit having a plurality of input/output 35 bly the method mcludes electrically connecrmg the lead pads and a lead interconnect electrically connected to interconnects to the puis by heating the pms and soldereach pad. A plurality of signal connections extend trans- mS the interconnects and pins together. Preferably the versely through the inside of all of the slices and sur- testing step includes testing each slice individually by rounds the integrated circuit, and one of the connec- first testing only the lead interconnects and thereafter tions are connected to each of the lead interconnects. 40 testing the combination of lead interconnects and inteThis structure provides shorter connecting lines with grated circuits.

lower parasitics because the connections are made Another object of the present invention is providing

closely adjacent to the integrated circuits. a plurality of solder filled openings in each slice, one of

An object of the present invention is wherein the said openings positioned adjacent the termination of

slices are ceramic and the signal connections are stacked 45 each lead interconnect, and heating the stacked to

in aligned metal filled vias which are connected to- gether slices for connecting the solder filled openings

gether to form the signal connections. together forming the signal connections.

Still a further object is wherein the lead connects In one form 0f the invention the slices are ceramic

include a film strip position between slices providing an md tne iead interconnects are formed by placing a film

electrical interconnection between the vias and the 50 0f interconnect circuitry between ceramic slices.

Pads- ,„',,. Yet in another form of the invention, the slices are

In another form of the invention, each slice mcludes fonned b a bottom metauic layer, a middle

a middle layer having at least one mtegrated circuit j havin ^ mt ted circuit with a lurality of

with a plurahty of input/output pads and a lead inter- m^ * ^ a mation j Mso>

connect electrically connected to each pad, a metallic 55 r . r r . . \. . * , , .

. ,. . c., i i openings are provided m all of the layers within their

layer adjacent one side of the middle layer for support- ■ , , ^ ■ . 1 , ■

ing the middle layer and providing a heat spreader, and P^phery and surrounding tiie integrated circuits,

an encapsulation layer adjacent to second side of the ^A stlU obJf1 of the Present invention is

middle layer. The middle, metauic and encapsulation wherem the mtegrated circuits have mput protection

layers include a plurahty of openings within the layers 60 dlodes at each Pad and the testing mcludes applying a

and surrounding the integrated circuits. A plurahty of negative voltage to each of the lead interconnects when

signal pins are provided, each of which extend through testing each slice, and measuring the current drawn for

an opening in each layer and through the slices. One each of the interconnects.

end of the pin is connectable to an electronic compo- Other and further objects, features and advantages

nent and one of the pins is electrically connected to 65 will be apparent from the following description of pres

each of the lead interconnects, but are insulated from ently preferred embodiments of the invention, given for

the metallic layer. Preferably the encapsulation layer the purpose of disclosure, and taken in conjunction with

includes a recess mating with the integrated circuit for the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an elevational view of one slice of one embodiment of the present invention without the integrated circuit and schematically illustrating testing the S lead interconnects,

FIG. 2 is an elevational view similar to FIG. 1 but with the integrated circuit die installed,

FIG. 3 is an exploded isometric view of the three layers of one slice of FIG. 2, 10

FIG. 4 is an isometric view of the layers of FIG. 3 stacked into one slice with the addition of a sealant,

FIG. 5 is a cross-sectional view taken along the line 5—5 of FIG. 4,

FIG. 6 is a cross-sectional view of a plurality of slices 15 of FIG. 5 stacked upon a base plate with signal connection pins to form a module,

FIG. 7 is a fragmentary enlarged elevational view showing a soldered coated signal pin,

FIG. 8 is a view similar to FIG. 7 after heat has been 20 applied soldering the pin and lead interconnections together,

FIG. 9 is an elevational view of a completed module with a schematic test set up for testing the final assembly, 25

FIG. 10 is a completed module assembly having horizontal extending pins for providing a quad flat pack connection,

FIG. 11 is a cross-sectional view of another embodiment showing a ceramic slice with lead interconnects 30 and an integrated circuit die with a schematic test set up,

FIG. 12 is an assembly composed of a plurality of the ceramic slices of FIG. 11 which have been bonded together and provided with a schematic test set up, and 35

FIG. 13 is an alternate ceramic slice embodiment having a film strip with interconnect leads on the bottom for connecting to the signal connections, but with the traces on the film shown below in dotted lines for clarity. 40

DESCRIPTION OF THE PREFERRED
EMBODIMENTS

Referring now to the drawings and particularly to FIG. 6, one embodiment of the present invention is 45 shown generally indicated by the reference 10 which generally uses standard printed circuit board materials and provides a standard PGA footprint mounting of the package on a printed circuit board. The three dimensional IC module 10 of the present invention includes a 50 plurality of slices generally indicated by the reference 12 here shown as three slices for convenience although any suitable number may be utilized.

Referring now to FIG. 3, an exploded view of one of the slices 12 is best seen which may include a bottom 55 metallic layer 14 such as alumina for acting as a support and a heat sink, a middle layer 16 having at least one integrated circuit die 18 which includes a plurality of input/output pads 20 and a plurality of lead interconnects 19, one electrically connected to each pad 20, and 60 an encapsulation layer 24 which preferably includes a window 26 adjacent the IC die 18 for receiving a suitable sealant such as silicone gel 28 (FIGS. 4 and 5).

A plurality of openings 30,32, and 34 are provided in each of the layers 14,16 and 24, respectively. The open- 65 ings 30, 32 and 34 are coaxially aligned with each other when the layers 14,16 and 24 are assembled together to form a plurality of openings through each layer 12 for

receiving a plurality of signal connections. As best seen in FIGS. 1 and 2 the openings 40 and thus signal connections 42 (FIG. 6) are positioned within the outer periphery of the slices 12, surround the integrated circuits 18, and are positioned as closely as possible to the integrated circuits 18. As will be described, since the signal connections 42 are connected to lead interconnects 19 and thus to one of the pads 20 on the integrated circuits 18 the particular configuration shown is highly advantageous. First, the lines of connection between the signal connections 42 and the pads 20 are short, the ensuing capacitance is a minimum, the signal rise time is short, and easier and quicker testing of the various components can be accomplished since each of the pads 20 is directly connected to one of the signal connections 42. It is further to be noted that the signal connections 42 match the footprint of a PGA package and thus can be conventionally mounted with other electronic components. Also, because of the arrangement shown a high density module may be provided in a small package.

The significant challenges involved in testing conventional multi-chip modules may be overcome with the present module 10 as each component may be tested individually during the assembly process. Referring now to FIG. 1, one assembled slice 12 is shown minus the integrated circuit die 18. The lead interconnects 19 (shown as dotted lines) are custom fabricated in the printed circuit board layer 16 (beneath layer 24) having first ends 21 surrounding the space for insertion of the integrated circuit die 18 and second ends 23 positioned adjacent one of the openings 40. Only a few of the lead interconnects 19 are illustrated, but each lead interconnect 19 would lead from one of the pads 20 of integrated circuit 18 to one of the openings 40 for connection to a signal connection 42, either to be interconnected to other integrated circuits 18 on other slices 12 or brought to the lowest slice 12 which provides the connections to another electronic component. In FIG. 1 an electrical test apparatus 44 is shown testing the electric continuity of each of the lead interconnects 19 before the slice 12 is fully assembled.

And referring to FIG. 2, the integrated circuit 18 is connected in place and the pads 20 (FIG. 3) are electrically connected to the ends 21 of the lead interconnects 19 by any suitable means such as either TAB bonding or conventional wire bonding. At this stage the testing apparatus 44 may again be used to test the individual slice 12 to determine if any fault exists in the integrated circuit 18, the bonding between the integrated circuit 18 and the lead interconnection 19, or again in the lead interconnections 19. Of course, the testing step illustrated in FIG. 1 may be omitted, but it provides an additional testing method for isolating any faults detected in the testing step shown in FIG. 2. It is to be noted that each of the IC pads 20 includes an input protection diode 46 and the testing step may take advantage of this structure. That is, a negative voltage, such as minus 3 V, may be applied to each of the pads 20 of the integrated circuit 18 and a known current should be drawn. A low current indicates an open pad, and a high current indicates a shorted pad.

After the individual slices 12 have been assembled and tested, they are then ready for stacking as best seen in FIG. 6. That is, a base heat sink 48 is provided which has connected thereto and insulated therefrom the plurality of signal connection pins 42. The individual slices 12 may then be stacked as the openings 40 may be inserted over the pins 42.

5 6

Referring now to FIG. 7, it is to be noted that the individually and prior to the assembly of the completed

openings 34 in the encapsulation layer 24 and the open- three dimensional module 106.

ings 30 in the metallic layer 14 are preferably larger As also shown in FIG. 12 after assembly of the modthan the openings 32 in the layer 16. For example only, ule 106 it may again be tested by the apparatus 44. While the openings 40 may be made at a pitch of 100 mils, with 5 the module 106 shown in FIG. 12 has horizontally exopenings 30 and 34 having a diameter of 75 mils, while tending connections 56b of a quad flat pack, it is to be the diameters of the openings 32 are 27 mils (or 24 mils understood that connections could be directed downwith pasteless solder on the sidewalk) and the diameters wardly to 6 meet a conventional PGA footprint. Also in of the signal pins 42 are 18 mils (or 24 mils if coated with FIG. 12 a top seal 62 is added to the module 106 after solder). Because of the difference in size between the 10 testing.

openings 30 of the metal layer 14 and of the pins 42, the Referring now to FIG. 13 a further embodiment of a pins may extend through a plurality of metal layers 14 ceramic slice 12c is shown in which instead of having a with the air gap therebetween providing sufficient insu- plurality of lead networks 19b made in the slice 12b, a lation and providing ease of construction. However, it separate film 70 is provided having a plurality of lead is desirable that the openings 32 be closer to the outside 15 networks 19c which can be easily custom fabricated to of the signal pins 42 for ease of connection. After each make contacts with various signal connections 60c and slice 12 is stacked onto the pins 42, each of the pins 42 be soldered thereto during the assembly process, is sprayed lightly with a flux 50 to facilitate solder re- As before in the other embodiments, each IC 18c is flow. A light pressure is then applied to the stacked mounted on a custom interconnect slice 12c, tested, then slices 12 to hold the assembly while the pins 42 are 20 all slices are stacked together with electrical connecheated such as being inserted into a suitable metal heater tions from one slice layer 12c to the next slice layer 12c block (not shown). The pins 42 are then heated causing and to the signal connections for connection to other the solder 50 (whether on each pin 42, in each opening electronic components. In addition, all of the intercon32, or both) flow and make interconnections, if any, nect networks are accessible for testing at the final asbetween the pins 42 and the lead interconnections 19 in 25 sembly stage which is an important testability feature layers 16. This provides, as best seen in FIG. 8 an elec- not afforded by conventional multi-chip packages. By trical connection 52 between the signal pins 42 and the individually testing each of the components prior to interconnection leads. final assembly, the risk and trouble of assembling a Referring now to FIG. 9, after the module 10 has multi-chip package with faulty components is minibeen assembled and connected to the signal pins 42, it 30 mized.

may be tested by suitable testing apparatus 44 which in The present three dimensional IC interconnect modfact may be a standard test fixture which matches the ules make use of electrical signal connections surroundfootprint of the PGA pins 42 to make the necessary ing the integrated circuits. The signal connections are electrical contacts needed for complete full speed test- assigned to each of the signals to be routed between ing of a module 10. In addition, when the module 10 is 35 seperate integrated circuit chips as well as between assembled, all of the lead networks 19 are available for integrated circuit chips and external package pins. The testing at the pins 42 with no concealed signals or net- integrated circuit bond pads are connected to the signal works. Again, taking advantage of the input protection connections using standard patterned metallic traces on diodes 46 of the integrated circuit 18 a negative voltage a printed circuit board or multi-layer ceramic interconmay be applied to each network and a known current 40 nect. After testing, if any defect is found, the same heatshould be drawn for each of the networks, indicative of ing block which was used to electrically connect the a number of diodes connected to the network. A low solder on each pin to the lead interconnections may be current indicates an open pad, a high current indicates a used to remelt the solder joints and disassemble the shorted network. module for retest and repair.

Other and further embodiments of the present inven- 45 The method of making the three dimensional IC in

tion may be provided. As shown in FIG. 10, a module terconnect modules and the testing of them is apparent

10a is provided which is generally the same as module from the foregoing description.

10 with the exception of having a base 54 which in The present invention, therefore, is well adapted to

addition to having a plurality of vertical extending sig- carry out the objects and attain the ends and advantages

nal pins 42a also includes a plurality of horizontally 50 mentioned as well as others inherent therein. While

directed pins 56 that provide a conventional footprint presently preferred embodiments of the invention have

for connections with a quad flat pack. been given for the purpose of disclosure, numerous

Referring now to FIGS. 11 and 12, another embodi- changes and details of construction, arrangement of

ment of the present invention is used which utilizes a parts, and steps of the process, will be readily apparent

multilayer ceramic slice. Thus, slice 12b is provided 55 to those skilled in the art which are encompassed within

having an integrated circuit 186 in which its pads 20b the spirit of the invention and the scope of the appended

are connected to ends 21b of the lead interconnects 19b claims,

in the ceramic slice 12b. The ceramic slice 126 includes What is claimed is:

a plurality of openings 326 which are filled with solder 1. A method of making a three-dimensional IC inter

60. When a plurality of slices 126 are stacked together 60 connect module comprising,

and heated the solder reflow creates signal connections making a plurality of slices having at least one inte

vertically through an assembled module as best seen in grated circuit having a plurality of input/output

FIG. 12. The vertical signal connections may also be pads and a lead interconnect electrically connected

made using conductive adhesive or conductive tape. to each pad, said lead interconnects terminating at

Again it is to be noted that the openings 326 through the 65 various locations within the periphery of the slices

slice 126 are positioned through, surround, and are and surrounding the integrated circuits,

closely adjacent to the IC 186. It is also noted from testing each slice individually to test the integrated

FIG. 11 that each individual slice 126 may be tested circuits and the lead interconnects,

« FöregåendeFortsätt »