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QUAD FLAT NO LEAD (QFN) GRID ARRAY
PACKAGE
CROSS-REFERENCE TO RELATED
APPLICATION 5
This application is a divisional of application Ser. No. 09/933,297, filed Aug. 20, 2001, now U.S. Pat. No. 6,967, 125, issued Nov. 22, 2005.
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor packaging. More specifically, the present invention relates to 15 semiconductor packaging using a quad flat package design incorporating a lead frame and providing an increased number of input/output contacts arranged in a grid array.
2. State of the Art
Conventional quad flat packages (QFP) are formed with a 20 semiconductor die connected to a lead frame and being encapsulated to form a package such that a plurality of leads extends laterally outwardly from each side of the periphery of the encapsulating structure. Such a configuration is relatively simple in design and may be efficiently produced. 25 However, the QFP-type semiconductor has shown various design and production limitations. For example, reducing the overall package size of a QFP becomes difficult because of the arrangement of leads about the lateral periphery of the package. This is particularly evident when reduced package 30 size is attempted to be combined with increasing the number of input/output (I/O) connections required for the smaller yet ever-more complex dice representing the state of the art.
In order to either reduce the size of a conventional QFP while at least maintaining, if not increasing, the number of 35 connections or to increase the number of I/O connections while at least maintaining, if not decreasing, the package size, a higher density of connections would be required along the package perimeter. However, such an increased density of leads about the package perimeter inherently 40 requires a reduced pitch or spacing between adjacent leads and promotes an increased likelihood of cross-talk and signal interference as well as making such packages more difficult to fabricate.
In an effort to increase the number of connections in an 45 integrated circuit (IC) package while maintaining or decreasing the overall size, alternative packaging arrangements have been implemented. For example, grid array devices such as pin grid arrays (PGAs), ball grid arrays (BGAs), land grid arrays (LGAs) and their associated vari- 50 ants have been used to reduce package size and increase input/output connections. As an example of a grid array type device, a BGA device employs a number of input/output connections in the form of conductive bumps, such as solder balls, extending transversely from a major surface of the 55 package in a pattern, or "array," of columns and rows. The conductive bumps may be formed on one surface of a circuit board or other interposer substrate and are in electrical connection with bonding pads on the opposing surface of the circuit board. A semiconductor die is coupled to the bonding 60 pads, such as by wire bonding, to establish electrical connections from the bond pads of the semiconductor die to the conductive bumps. The resulting assembly is then typically encapsulated, such as by transfer molding with a filled polymer, with the array of conductive bumps being left 65 exposed for subsequent electrical connection to higher-level packaging such as a carrier substrate. The conductive bumps
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are configured to be coupled to a mirror image pattern of terminal pads on the carrier substrate which may comprise a printed circuit board (PCB) or another structure by reflowing the solder. In essence, a BGA device increases the number of input/output connections by allowing the connections to be positioned over substantially the entirety of a major surface of the package rather than extending laterally outwardly from the periphery of the package such as in a QFP.
While BGA and other grid array devices provide an increased number of input/output connections and may allow a simultaneous reduction in size for a given package, such devices are not without their own limitations and drawbacks. For example, the use of circuit board interposers, upon which the array of conductive elements is formed, imposes limitations on the size of the package since the circuit board is typically larger than the semiconductor die. Additionally, the circuit boards used in making BGA packages have been known to take on moisture during the fabrication process, leading to subsequent cracking and warpage which ultimately renders the device unusable. Furthermore, the cost of circuit boards used in the fabrication of grid array type devices may also be viewed as a drawback.
In view of the shortcomings in the art, it would be advantageous to provide a semiconductor die package which allows for a higher density of input/output connections without increasing package size. It would further be advantageous to provide such a package having a patterned array of input/output connections formed from a lead frame.
Additionally, it would be advantageous to provide a method of producing such a package, and the lead frame utilized in such a package, which does not require significant changes in tooling or fabrication processes such that the method is easily and efficiently implemented without incurring significant capital costs for new equipment or an increase in process steps.
BRIEF SUMMARY OF THE INVENTION
One aspect of the invention includes a method of forming a semiconductor die or IC package. The method includes providing a semiconductor die having a plurality of bond pads located on an active surface thereof. A lead frame having a plurality of conductive leads is provided adjacent the semiconductor die. A first bond pad on the semiconductor die is electrically coupled to a first portion of at least one conductive lead and a second bond pad is coupled to a second portion of the same lead. The first portion and second portion of the lead are then electrically isolated from one another to form two individual conductive elements from the original conductive lead. Additionally, an insulative encapsulant may be formed about the semiconductor die and at least partially about the lead frame while allowing a portion of each individual conductive element to remain exposed for subsequent electrical coupling with an external electrical circuit such as a carrier substrate.
The individual conductive elements may, for example, be electrically isolated from one another by saw cutting the conductive lead subsequent to the first and second portion being coupled to the bond pads of the semiconductor die. Also, a severance region may be predefined in the lead between the first portion and second portion so as to help facilitate the electrical isolation of the two portions. The severance region may include a notch or recess formed by scoring, cutting or etching partially through the material of the lead. Encapsulant covering the semiconductor die may
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be extended into the notch or recess of the severance region prior to isolating the first portion and second portion to help retain the first portion and second portion in their respective positions once they have been separated from one another by complete removal of any intervening lead material. 5
Another aspect of the present invention includes a method of forming an array of electrically conductive elements for an IC package. The method includes disposing a semiconductor die having a plurality of bond pads on an active surface thereof on a lead frame including a plurality of leads. l o At least two bond pads of the semiconductor die are electrically coupled with each lead of the lead frame. The leads are then severed between the locations of coupling to form at least two electrically isolated conductive elements, each such electrically isolated conductive element being coupled 15 to an individual bond pad on the semiconductor die.
The present invention also includes a lead frame of a first design. The lead frame includes a plurality of individual leads. At least one of the plurality of leads includes a first bonding region, a second bonding region and a severance 20 region located between the first and second bonding regions. The severance region is configured to facilitate separation of the first bonding region from the second bonding region subsequent to connection of bond pads of a semiconductor die to the respective first and second bonding regions and 25 encapsulation of the lead frame and semiconductor die to form an IC package.
The present invention further includes a lead frame of a second design. This lead frame includes a die paddle configured for attachment of a semiconductor die thereto. The 30 lead frame also includes a plurality of conductive elements, each having at least two bonding regions. The bonding regions are arranged in a grid array pattern which includes a first peripheral row of bonding regions spaced about a periphery of the die paddle and at least one other peripheral 35 row of bonding regions spaced laterally outwardly from the first peripheral row.
Yet another aspect of the invention includes a semiconductor die or IC package. The IC package includes a semiconductor die a lead frame and an electrically insulative 40 encapsulant. The lead frame includes a plurality of spaced conductive elements arranged in an array including a first set of conductive elements on a major surface of the package and adjacent a lateral periphery thereof and at least one other set of conductive elements inwardly adjacent the first set. 45 The insulative encapsulant extends over the semiconductor die and at least partially over the lead frame while allowing a portion of each of the conductive elements to be exposed on the major surface for connection with an external electrical circuit. At least one concavity or other recess is defined 50 between and electrically isolates at least one conductive element of the first set and an adjacent conductive element of the at least one other set.
In accordance with another aspect of the invention, another IC package is provided. The IC package includes a 55 semiconductor die having a plurality of bond pads and a lead frame having a plurality of conductive leads. Each of the plurality of conductive leads is electrically coupled to at least two bond pads of the plurality of bond pads.
In accordance with another aspect of the present inven- 60 tion, a memory module is provided. The memory module includes a carrier substrate in the form of a module board configured to be electrically coupled to another, higher-level packaging structure such as a motherboard, enabling the memory module to communicate with a processor. At least 65 one IC package having features such as those described above is electrically coupled to the module board.
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In accordance with another aspect of the invention, a computer system is provided. The computer system comprises an input device, an output device, a processor coupled to the input and output devices, and a memory module, such as described above, coupled with the processor.
BRIEF DESCRIPTION OF THE SEVERAL
VIEWS OF THE DRAWINGS
The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
FIG. 1 is a plan view of the bottom of an IC package according to one embodiment of the present invention;
FIG. 2 is a cross-sectional view of the IC package of FIG.
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FIGS. 3A and 3B are enlarged views of the section specified in FIG. 2 at various stages of manufacturing;
FIGS. 4A and 4B are partial plan views of an IC package according to alternative embodiments;
FIG. 5 is a plan view of a lead frame strip according to one embodiment of the present invention; and
FIG. 6 is schematic of a computer system incorporating the IC package of the present invention.
DETAILED DESCRIPTION OF THE
INVENTION
FIGS. 1 and 2 depict one embodiment of an IC package of the present invention in the form of a quad flat no-lead (QFN) grid array package 10. FIG. 1 presents a view of a major surface comprising the underside of the QFN package 10, while FIG. 2 shows a cross-section of the QFN package 10 taken along section line 2—2 as shown in FIG. 1. The QFN package 10 includes a semiconductor die 12 positioned on and secured by its back side to a die paddle 14, die paddle 14 originally comprising a portion of a lead frame as will be-hereinafter described. Conductive elements 16 are positioned about the die paddle 14 in a grid array pattern, outwardly of semiconductor die 12 and adjacent the lateral periphery of QFN package 10. The die paddle 14 and conductive elements 16 may be formed of any suitable material such as copper, aluminum, alloy 42 or any other suitable conductive material for lead frames as understood by those of ordinary skill in the art.
The grid array pattern of the conductive elements 16 may be described in various geometrical terms such as a grid having a specified number of columns and rows. However, due to the general placement of the conductive elements 16 outwardly of the semiconductor die 12 and generally adjacent the lateral periphery of the QFN package 10, the grid array structure will be discussed in terms of peripheral rows. Thus, the QFN package 10 shown in FIGS. 1 and 2 includes a first inner peripheral row 18A and a second outer peripheral row 18B of conductive elements 16.
The language "peripheral row" is used herein for convenience in describing the configuration of the QFN package 10 and should not be understood as-requiring all of the conductive elements 16 to be located at or on the lateral peripheral edge of the QFN package 10, nor should such phraseology be taken to mean that a given lateral peripheral row of conductive elements 16 must circumscribe the entire die paddle 14 and semiconductor die 12. While it is desirable to have the conductive elements 16 positioned about each side of the QFN package 10 so as to maximize the number of conductive elements 16 in the package, some designs may not require such an arrangement. Alternatively, some con
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