EXECUTION UNIT FOR DATA PROCESSOR
USING SEGMENTED BUS STRUCTURE
CROSS-REFERENCE TO RELATED 5
APPLICATIONS
1. "Multi-port RAM Structure For Data Processor Registers", invented by McAlister et al, bearing Ser. No. 961,797, filed on even date herewith, and assigned
to the assignee of the present invention. 10
2. "Microprogrammed Control Apparatus For Data Processor Having a Two-Level Control Store", invented by Tredennick et al, bearing Ser. No. 961,796, filed on event date herewith, and assigned to the assignee of the present invention. 15
TECHNICAL FIELD
This invention relates generally to data processors and more particularly to a bus structure employed to implement the execution unit of a data processor. 20
BACKGROUND ART
The field of single-chip, large scale integration (LSI) microprocessors is advancing at an incredible rate. Progress in the underlying semiconductor technology, 25 MOS, is driving the advance. Every two years, circuit densities are improving by a factor of 2, circuit speeds are increasing by a factor of 2, and at the same time speed-power products are decreasing by a factor of 4. Finally, yield enhancement techniques are driving 30 down production costs and hence product prices, thereby increasing demand and opening up new applications and markets.
One effect of this progress in semiconductor technology is advancement in LSI microprocessors. The latest 35 generation, currently being introduced by several companies, is an order of magnitude more powerful than the previous generation, the 8-bit microprocessors of three or four years ago. The new microprocessors have 16-bit data paths and arithmetic capability. They directly ad- 40 dress multiple-megabyte memories. In terms of functional capability and speed, they will outperform all but the high end models of current 16-bit minicomputers.
A particular data processor, which incorporates the present invention, supports an instruction set which 45 consists of general single and dual operand instructions involving byte (8 bits), word (16 bits) or double word operands. Operations are generally memory-to-register, register-to-memory, or register-to-register. In addition to standard instructions such as add, compare, and shift, 50 this particular data processor is designed to support such instructions as load and store multiple registers, multiply and divide, and various forms of bit manipulation. The data processor provides eight 32-bit address manipulation registers and eight 32-bit data manipula- 55 tion registers. Address registers allow 16-bit and 32-bit operations, and data registers allow 8-, 16-, and 32-bit operations. All address and data registers are accessible to the programmer. In addition, there is a program counter with limited user accessibility, and there are 60 several registers not available to the user which are used for temporary storage during instruction execution.
In many prior art data processors, one or more digital buses are used to interconnect a plurality of address and data registers to an arithmetic unit within the execution 65 unit of the data processor. The digital buses are also generally used to interconnect the execution unit to the input/output terminals of the data processor for trans
2
mining an address and for transmitting and receiving instructions and data. An example of a data processor using such a bus structure is the MC6800 integrated circuit microprocessor supplied by Motorola, Inc., which is described in U.S. Pat. No. 4,004,281, "Microprocessor Chip Register Bus Structure", invented by Bennett et al and assigned to the assignee of the present invention.
One technique for improving the speed and efficiency of a data processor is to provide for parallel operations. For example, a data computation might be performed according to a current instruction while an address computation might be simultaneously performed for computing a memory address where the next instruction will be found. The bus structure disclosed by U.S. Pat. No. 4,004,281 is not ideally suited for such parallel operations. One approach to allow for more parallel operations is simply to add another digital bus in parallel with existing digital buses for allowing an additional transfer to occur without interfering with the transfers already taking place on the existing digital buses. Such an approach is disclosed in co-pending application "Microprocessor Having Plural Internal Data Buses" invented by Daniels et al, bearing Ser. No, 939,741, and assigned to the assignee of the present invention. However, the addition of one or more digital buses increases the required chip area for implementing the data processor. Also, additional coupling MOSFET devices are required in order to enable or disable the input and output of each register and arithmetic unit to the additional digital buses, and additional control signals must be decoded by the data processor control circuitry for controlling the added coupling MOSFET devices.
It will be noted that many address computations will require an arithmetic unit capable of more than mere increment and decrement functions. Indexed and selfrelative addressing modes require that an offset be added to or subtracted from an index register or program counter, respectively. Thus a bus structure which allows for parallel address and data computations must allow for individual arithmetic units for address and data computations.
It should be appreciated by those skilled in the art that a bus structure which allows for a highly dense data processor execution unit and which is adapted to allow for parallel operations within the execution unit is a significant improvement over the prior art.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a bus structure for the execution unit of a data processor which facilitates general bidirectional transfers among various functional units and registers while maintaining the number of digital buses to a minimum in order that the execution unit be as dense as possible.
It is a further object of the present invention to provide a bus structure for the execution unit of a data processor which facilitates parallel computations of addresses and data in order to improve the speed and efficiency of the data processor.
Another object of the present invention is to provide a data processor adapted for operating upon 16-bit data words and being adapted to directly address multiplemegabyte memories such that parallel computations of address and data words may be performed.
These and many other objects are accomplished by the present invention which includes first and second
