Method and apparatus for testing integrated circuit chips

Il l II IIIII111I I11I I il I II I111II

United States Patent m

Charlton et al.

US005528159A [11] Patent Number: [45] Date of Patent:

5,528,159 Jun. 18, 1996

[54] METHOD AND APPARATUS FOR TESTING INTEGRATED CDRCUIT CHIPS

[75] Inventors: Richard G. Charlton; George C.

Correia, both of Essex Junction; Mark
A. Couture, Milton; Gary R. Hill,
Jerico; Kibby B. Horsford, Charlotte,
all of Vt.; Anthony P. Ingraham;
Michael D. Lowell, both of Endicott,
N.Y.; Voya R. Markovich, Endwell,
N.Y.; Gordon C. Osborne, Jr., Essex
Junction, Vt.; Mark V. Pierson,
Binghamton, N.Y.

[73] Assignee: International Business Machine
Corp., Armonk, N.Y.

[21] Appl. No.: 454,458

[22] Filed: May 30, 1995

Related U.S. Application Data

[60] Division of Ser. No. 163,452, Dec. 7, 1993, which is a continuation-in-part of Ser. No. 76,079, Jun. 14, 1993, abandoned.

[51] Int. CI.6 G01R 1/073

[52] U.S. CI 324/758; 324/757

[58] Field of Search 324/758, 757,

324/754

[56] References Cited

U.S. PATENT DOCUMENTS 4,254,443 3/1981 Babuka et al 257/718

A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

10 Claims, 13 Drawing Sheets