Integrated circuit package and method for fabricating same

US007348663B1

(12) United States Patent

Kirloskar et al.

(io) Patent No.: (45) Date of Patent:

US 7,348,663 Bl Mar. 25, 2008

(54) INTEGRATED CIRCUIT PACKAGE AND METHOD FOR FABRICATING SAME

(75) Inventors: Mohan Kirloskar, Cupertino, CA (US);

Katherine Wagenhoffer, Union City,
CA (US); Leo M. Higgins, III, Austin,
TX (US)

(73) Assignee: ASAT Ltd., Tsuen Wan, New
Territories (HK)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 64 days.

(21) Appl. No.: 11/183,290

(22) Filed: Jul. 15, 2005

5,343,076 A 8/1994 Katayama et al.

5,406,124 A 4/1995 Morita et al.

5,424,576 A 6/1995 Djennas et al.

5,444,301 A 8/1995 Song et al.

5,457,340 A 10/1995 Templeton, Jr. et al.

5,474,958 A 12/1995 Djennas et al.

5,483,099 A 1/1996 Natarajan et al.

(Continued)
FOREIGN PATENT DOCUMENTS
JP 59-208756 11/1984

OTHER PUBLICATIONS

Neil McLellan et al.; Leadless Plastic Chip Carrier With Etch Back Pad Singulation; U.S. Appl. No. 09/802,678, filed Mar. 9, 2001.

Primary Examiner—Long K. Tran

(74) Attorney, Agent, or Firm—Morrison & Foerster LLP

A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

9 Claims, 11 Drawing Sheets