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Patent

  

United States Patent im

Wada et al.

[li] Patent Number: 4,790,902 [45] Date of Patent: Dec. 13, 1988

[54] METHOD OF PRODUCING CONDUCTOR CIRCUIT BOARDS

[75] Inventors: Tatsuo Wada, Ebina; Keizo Yamashita, Shizuoka; Tasuku Touyama, Shimizu; Teruaki Yamamoto, Shizuoka, all of Japan

[73] Assignee: Meiko Electronics Co., Ltd., Ayase, Japan

[21] Appl. No.: 131,050

[22] PCT Filed: Feb. 21, 1987

[86] PCT No.: PCT/JP87/00111
§ 371 Date: Oct. 16,1987
§ 102(e) Date: Oct. 16, 1987

[87] PCT Pub. No.: WO87/05182
PCT Pub. Date: Aug. 27, 1987

[30] Foreign Application Priority Data

Feb. 21, 1986 [JP] Japan 61-036712

[51] Int. CI.4 B44C 1/22; C03C 15/00;

C03C 25/06; C23F 1/00

[52] U.S. CI 156/630; 29/848;

156/151; 156/153; 156/233; 156/236; 156/240; 156/249; 156/631; 156/634; 156/645; 156/650; 156/656; 156/659.1; 156/902; 156/666; 204/15;

204/23; 204/32.1

[58] Field of Search 156/150, 151, 153, 154,

156/233, 235, 236, 240, 241, 247, 249, 629, 630, 631, 634, 645, 650, 656, 659.1, 664, 666, 901, 902; 174/68.5; 427/96-98; 428/601, 901; 29/846, 848-852, 856; 204/15, 23, 32.1, 34, 40,

44, 52.1

[56] References Cited

U.S. PATENT DOCUMENTS

4,604,160 8/1986 Murakami et al 156/630

4,606,787 8/1986 Pelligrino 156/150 X

4,715,116 12/1987 Thorpe et al 29/846

FOREIGN PATENT DOCUMENTS

51-39539 4/1976 Japan .
55-32239 8/1980 Japan .
0147192 3/1985 Japan .

Primary Examiner—William A. Powell

Attorney, Agent, or Firm—Frishauf, Holtz, Goodman &

Woodward

[57] ABSTRACT

A thin metal layer with a thickness of 1 to 5 ju. is formed electrolytically (S2) on an electrically conductive single-plate substrate having a predetermined roughness, a resist mask is formed (S3) on the surface of the thin metal layer, and a conductor circuit is then electroformed thereon (S4) using copper. After the surface of the conductor circuit is roughened (S5), the conductor circuit, along with the single plate and the interposed thin metal layer, is stacked on an insulating substrate for lamination, and the individual layers are adhered integrally to one another by the application of heat and pressure (S7). Then, the single plate only is peeled off (S8), and the exposed thin metal layer is removed by etching (S9). The thin metal layer and the conductor circuit are electroplated under high-speed conditions including a solution contact speed of 2.6 to 20 m/sec and a current density of 0.15 to 4.0 A/cm2, so that a required adhesion force can be obtained between the thin metal layer and the resist mask, and the conductor circuit can be made as flexible as rolled annealed copper. Thus, very thin, high-density conductor circuits can be produced which, having a thickness of 10 tun or less, are adapted not only for rigid printed wiring boards but also for flexible printed wiring boards.

8 Claims, 12 Drawing Sheets

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