United States Patent m
Nickel
[54] APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUIT DEVICES
[75] Inventor: Donald F. Nickel, West Columbia, S.C.
[73] Assignee: NCR Corporation, Dayton, Ohio
[21] Appl. No.: 161,738
[22] Filed: Dec. 3,1993
[51] Int CI.6 H05K 3/34; H01L 23/495;
H01R 9/09
[52] U.S. CI 29/840; 29/740; 29/827;
29/830; 228/180.22; 257/737; 257/774;
257/778; 439/65
[58] Field of Search 29/827, 830, 832,
29/834, 840, 740, 759, 760; 228/6.2, 180.21, 180.22; 437/206, 207; 174/16.3; 257/778, 779, 676, 737, 774, 777, 675, 686, 713;
439/65, 68, 74
[56] References Cited
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3,868,765 3/1975 Hartleroad et al 29/740 X
3,914,850 10/1975 Coucoulas 29/827 X
3,984,860 10/1976 Logue 257/737 X
4,021,838 5/1977 Warwick 257/737 X
4,079,509 3/1978 Jackson et al 29/759 X
4,774,760 10/1988 Seaman et al 29/840
4,801,992 1/1989 Golubic 257/737 X
4,825,284 4/1989 Soga et al 257/778 X
4,954,878 9/1990 Fox et al 439/68 X
5,019,673 5/1991 Juskey et al 257/778 X
5,046,953 9/1991 Shreeve et al 29/840 X
5,058,265 10/1991 Goldfarb 228/180.22 X
5,065,227 11/1991 Frankeny et al 257/700 X
5,072,289 12/1991 Sugimoto et al 257/737
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US005454160A
[ii] Patent Number: 5,454,160 [45] Date of Patent: Oct. 3,1995
5,103,290 4/1992 Temple et al 257/774
5,111,279 5/1992 Paschetal 257/779 X
5,168,346 12/1992 Pasch et al 257/778 X
5,173,574 12/1992 Kraus 29/840 X
5,191,511 3/1993 Sawaya 257/737 X
5,219,377 6/1993 Poradish 29/840 X
FOREIGN PATENT DOCUMENTS
248907 8/1987 Germany .
189945 9/1985 Japan .
152031 7/1986 Japan.
OTHER PUBLICATIONS
Direct Light-Chip Interconnection Scheme Accommodating Flip-Chip Bonding; IBM Technical Disclosure Bulletin, vol. 33, No. 8; Jan. 1991; pp. 141-142.
Primary Examiner—Peter Vo
Attorney, Agent, or Firm—Paul W. Martin
[57] ABSTRACT
An apparatus and method for stacking integrated circuit devices which combine flip-chip technology and soldering methods with laminated stack frames to provide a vertical stack array with minimal parasitic inductance. Each laminated stack frame has a central cavity and includes a plurality of vias extending through them. The vias have top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump. Each laminated stack frame also includes a plurality of solder bump pads extending into the cavity to contact corresponding solder bumps on a flip-chip integrated circuit chip, and a plurality of traces coupling each solder bump pad to a via. The bottom surfaces of the vias of a bottom laminated stack frame couple to contacts on a printed circuit board.
13 Claims, 3 Drawing Sheets
