Method and apparatus for SoC design validation

(54) METHOD AND APPARATUS FOR SOC DESIGN VALIDATION

(75) Inventors: Rochit Rajsuman, Santa Clara, CA

(US); Hiroaki Yamoto, Santa Clara, CA
(US)

(73) Assignee: Advantest Corp., Tokyo (JP)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 09/428,746

(22) Filed: Oct. 28, 1999

(51) Int. CI.7 G06F 17/50

(52) U.S. CI 703/20; 714/33; 714/39;

714/735; 714/736; 714/737; 714/741; 714/742; 703/14; 703/15; 703/17; 703/16; 716/4;

716/16; 716/17; 716/18

(58) Field of Search 703/20, 21, 22,

703/23, 24, 25, 26-28, 15, 17, 19, 18; 716/18, 4, 5, 6, 16, 17; 712/28, 35; 714/33, 39, 735, 737, 736, 741, 742

(56) References Cited

U.S. PATENT DOCUMENTS

5,801,958 A * 9/1998 Dangelo et al 716/18

5,903,475 A * 5/1999 Gupte et al 703/16

6,009,256 A * 12/1999 Tseng et al 703/13

6,094,726 A * 7/2000 Gonion et al 712/221

6,269,467 Bl * 7/2001 Chang et al 716/1

6,304,837 Bl * 10/2001 Geiger et al 703/14

6,360,353 Bl * 3/2002 Pember et al 716/4

6,532,561 Bl * 3/2003 Turnquist et al 714/738

OTHER PUBLICATIONS

Rochit Rajsuman, "Design-for-Iddq-Testing for Embedded Cores Based System-on-a-Chip," 1998 IEEE International Workshop on IDDQ Testing, 1998. Proceedings, pp.: 69-73.*

Pankaj Chauhan, Edmund Clarke, Yuan Lu, and Dong Wang, "Verifying IP-Core Based System-On-Chip Designs," Twelfth Annual IEEE International ASIC/SOC Conference, 1999. Proceedings, pp.: 27-31.*

* cited by examiner

Primary Examiner—W. Thomson

(74) Attorney, Agent, or Firm—Muramatsu & Associates (57) ABSTRACT

A method and apparatus for validating SoC (system-on-achip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/ emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].

33 Claims, 10 Drawing Sheets