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Patent

  

United States Patent ti9]

Huppenthal

[ii]

[45]

US005162728A

Patent Number:
Date of Patent:

5,162,728 Nov. 10,1992

[54] FUNCTIONAL AT SPEED TEST SYSTEM

FOR INTEGRATED CIRCUITS ON UNDICED
WAFERS

[75] Inventor: Jon Huppenthal, Colorado Springs, Colo.

[73] Assignee: Cray Computer Corporation,

Colorado Springs, Colo.

[21] Appl. No.: 580,765

[22] Filed: Sep. 11,1990

[51] Int. CI.' G01R 1/02; G01R 1/04

[52] U.S. CI 324/158 R; 324/158 P;

324/158 F; 439/482

[58] Field of Search 324/158 R, 158 F, 73.1,

324/72.5, 158 P; 437/8; 371/1, 15.1, 16.1, 27, 25.1; 439/482, 824; 361/397, 400, 401;

174/52.4, 52.2

[56] References Cited

U.S. PATENT DOCUMENTS

3,676,777 7/1972 Charters 324/158 P

3,963,986 6/1976 Morton et al 324/158 F

3,975,680 8/1976 Webb 324/158 R

4,473,798 9/1984 Cedrone et al 324/158 P

4,497,056 1/1985 Sugamori 371/25.1

4,504,783 3/1985 Zasio et al 324/158 F

4,567,432 1/1986 Buol et al 324/158 F

4,574.235 3/1986 Kelly et al 324/158 F

4,593,243 6/1986 Lao et al 324/158 P

4,672,312 4/1987 Takamine et al 324/158 F

4,684,884 8/1987 Soderlund 324/158 R

4,697,143 9/1987 LocKwood et al 324/158 F

4,719,411 1/1988 Buehler 324/158 R

4,731,577 3/1988 Logan 324/158 F

4,733,172 3/1988 Smolley 324/158 P

4,739,257 4/1988 Jenson et al 324/158 F

4,764,723 8/1988 Strid 324/158 P

4,769,591 9/1988 Binet et al 324/158 F

4,775,977 10/1988 Dehara 371/27

4,780,670 10/1988 Cherry 324/158 F

[blocks in formation]

A digital test system for functionally testing undiced ICs on wafers at relatively high test frequencies includes an improved probe card and interface assemblies. The probe card and interface assemblies each include a plurality of printed circuit boards laminated together as a single laminated structure. Equal length and equal impedance elongated micro strip test signal traces conduct the signals to and from a probe ring with a plurality of resilient probes physically and electrically in contact with the contact pads of the IC. Other circuit patterns includes a relatively large reference plane and a power plane of approximately equal size. The interface assembly performs selective I/O functions to electrically conduct input signals from a test signal generator to the probe card assembly and to electrically conduct response signals from the probe card assembly to the signal analyzer for determining the proper functionality of the IC. The printed circuit techniques assures a high degree of signal integrity, control over the signals at very high test frequencies, and efficiency in signal path routing.

36 Claims, 8 Drawing Sheets

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