A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing...http://www.google.se/patents/US7594088?utm_source=gb-gplus-sharePatent US7594088 - System and method for an asynchronous data buffer having buffer write and read pointers
