A memory controller includes a pair of input command decoders and a pair of multiplexers. If the memory controller receives a data transfer request related to a read or write burst which will stay within a page of memory, the first input command decoder circuit generates a first input command which is...http://www.google.se/patents/US6587390?utm_source=gb-gplus-sharePatent US6587390 - Memory controller for handling data transfers which exceed the page width of DDR SDRAM devices
