A microprocessor having variable data width comprising a bus cycle changeover circuit between a command execution unit and each of an address output logic, a data input/output logic, and a bus controller. The bus cycle changeover circuit receives an address, data, a memory access instruction and a data...http://www.google.se/patents/US4766538?utm_source=gb-gplus-sharePatent US4766538 - Microprocessor having variable data width
