A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output lines and address lines. Each transistor...http://www.google.se/patents/US6747305?utm_source=gb-gplus-sharePatent US6747305 - Memory address decode array with vertical transistors
