A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed,...http://www.google.se/patents/US8172980?utm_source=gb-gplus-sharePatent US8172980 - Device with self aligned gaps for capacitance reduction
