A three dimensional memory enabling both pixel and bit slice data to be stored and retrieved through different ports. A memory circuit (30) is divided into a lower memory block (32a) and an upper memory block (32b). Each memory block is organized into 256 rows .times.16 groups (pixel planes) of eight...http://www.google.se/patents/US5303200?utm_source=gb-gplus-sharePatent US5303200 - N-dimensional multi-port memory
