A chip scale package is disclosed that includes a semiconductor die further comprising an array of power buses electrically coupled to a high power integrated circuit, and a plurality of Under Bump Metallization (UBM) multi-layer power buses disposed parallel to one another and spanning substantially...http://www.google.se/patents/US7944048?utm_source=gb-gplus-sharePatent US7944048 - Chip scale package for power devices and method for making the same
