WO2012113441A1

WO2012113441A1 - Thin-film solar fabrication process, deposition method for a layer stack of a solar cell, and solar cell precursor

Info

Publication number: WO2012113441A1
Application number: PCT/EP2011/052537
Authority: WO
Inventors: Stefan Klein; Martin Rohde; Konrad Schwanitz; Tobias Stolley; Christian Stoemmer; Susanne Buschbaum
Original assignee: Applied Materials, Inc.
Priority date: 2011-02-21
Filing date: 2011-02-21
Publication date: 2012-08-30

Abstract

A method of depositing layer stacks for photoelectric conversion devices, e.g., solar cells and corresponding layer stacks or solar cell precursors are described. The method includes depositing a first conductivity-type silicon-containing layer for a p-i-n-junction of a solar cell, depositing an intrinsic-type silicon containing layer for a p-i-n-junction of a solar cell, and depositing a second conductivity-type layer with a conductivity-type opposite to the first conductivity-type layer. The method further includes providing a back contact, wherein the second conductivity type layer is deposited between the intrinsic- type layer and the back contact, and wherein the further conductivity-type layer is deposited by chemical vapor deposition using CO₂.

Description

THIN-FILM SOLAR FABRICATION PROCESS, DEPOSITION METHOD FOR A LAYER STACK OF A SOLAR CELL, AND SOLAR CELL PRECURSOR

BACKGROUND OF THE INVENTION

Field of the Invention

[0001] Embodiments of the present invention generally relate to depositing layers of a photoelectric conversion module, e.g., a thin-film solar cell. Particularly, they relate to a layer stack of a solar cell, e.g., a solar cell with a one or more p-i-n junctions or n-i-p junctions. Specifically, they relate a method of manufacturing a layer stack adapted for a thin-film solar cell and a precursor for a solar cell.

Description of the Related Art [0002] Crystalline silicon solar cells and thin-film solar cells are two types of solar cells. Crystalline silicon solar cells typically use either mono- crystalline substrates (i.e., single-crystal substrates of pure silicon) or multi- crystalline silicon substrates (i.e., poly-crystalline or polysilicon). Additional film layers are deposited onto the silicon substrates to improve light capture, form the electrical circuits, and protect the devices. Thin-film solar cells use thin layers of materials deposited on suitable substrates to form one or more p- i-n junctions. Suitable substrates include glass, metal, and polymer substrates.

[0003] To expand the economic uses of solar cells, efficiency must be improved. Solar cell stabilized efficiency relates to the proportion of incident radiation converted into usable electricity. For solar cells to be useful for more applications, solar cell efficiency must be improved beyond the current best performance of approximately 10% for Si based thin-film solar modules. With energy costs rising, there is a need for improved thin-film solar cells and methods and apparatuses for forming the same in a factory environment.

[0004] Thin film solar cell can efficiently be manufactured by combining CVD processes such as PECVD and PVD processes such as sputtering. However, particularly if CVD and PVD processes are used for manufacturing a layer stack in a production line, it is not always possible to control the substrate flow such that each substrate is immediately processed after the previous processing step has been completed. Thus, there might be a time between different productions steps, particularly between CVD and PVD productions steps and vice versa, which can vary by a factor of up to ten or even twenty. In order to cope with such process variations, a precursor for a light conversion module needs to be manufactured such that the variations do not significantly influence the quality or characteristics of the precursor or the final product. This has to be considered when developing a manufacturing recipe. [0005] Another aspect for improving mass production of solar cells is the use of large scale processes, increasing the throughput, and improving the reliability at which processes can be conducted. Thus, there is a desire to improve the processes for increasing the efficiency on a large scale and for applications during industrial manufacturing.

SUMMARY OF THE INVENTION

[0006] In light of the above, a method of manufacturing a layer stack adapted for a thin-film solar cell according to independent claim 1 and a precursor for a solar cell according to independent claim 8 are provided. [0007] Embodiments of the invention provide methods of depositing layer stacks for photoelectric conversion devices, e.g., solar cells. According to one embodiment, a method of manufacturing a layer stack adapted for a thin-film solar cell is provided. The method includes depositing a first conductivity-type silicon-containing layer for a p-i-n-junction of a solar cell, depositing an intrinsic-type silicon containing layer for a p-i-n-junction of a solar cell, and depositing a second conductivity-type layer with a conductivity-type opposite to the first conductivity-type layer. The method further includes providing a back contact, wherein the second conductivity type layer is deposited between the intrinsic-type layer and the back contact, and wherein the further conductivity-type layer is deposited by chemical vapor deposition using C0₂.

[0008] According to another embodiment, a precursor for a solar cell is provided. The precursor includes a transparent substrate, a first conductivity- type silicon-containing layer for a p-i-n-junction of a solar cell, an intrinsic - type silicon containing layer for a p-i-n-junction of a solar cell, and a second conductivity-type layer with a conductivity-type opposite to the first conductivity-type layer. The precursor further includes a back contact, wherein the second conductivity-type layer is deposited between the intrinsic-type layer and the back contact, and wherein the further conductivity-type layer includes oxygen.

[0009] Further advantages, features, aspects and details that can be combined with embodiments described herein are evident from the depending claims, the description and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof, which are illustrated in the appended drawings.

[0011] Figure 1 is a schematic side-view of a layer stack configured for a thin-film solar cell according to one embodiment of the invention;

[0012] Figure 2 is a schematic side-view of a tandem-junction thin-film solar cell according to one embodiment of the invention; [0013] Figures 3 is a schematic side-view of a further thin-film solar cell according to one embodiment of the invention;

[0014] Figure 4 is a flow-chart illustrating methods of manufacturing a solar cell precursor according to embodiments described herein; [0015] Figures 5 A to 51 illustrate the layers deposited on a substrate according to embodiments described herein;

[0016] Figure 6 is a flow-chart illustrating methods of manufacturing a solar cell precursor according to embodiments described herein;

[0017] Figure 7 illustrates a plan view of a cluster tool that may be used according to one embodiment described herein; and

[0018] Figure 8 is a cross-sectional side view of a deposition chamber which can be used according to one embodiment described herein.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical or similar elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation.

[0020] It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are, therefore, not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

DETAILED DESCRIPTION

[0021] Reference will now be made in detail to the various embodiments of the invention, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation of the invention and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations.

[0022] The term "substrate" as used herein shall embrace both inflexible substrates, e.g., a wafer, a transparent substrate, or a glass substrate such as a glass plate, and flexible substrates such as webs and foils.

[0023] Embodiments described herein relate to a solar cell precursor and methods of manufacturing thereof, wherein a second conductivity-type layer includes a SiOx containing layer. Thereby, reference is, for example, made to the solar cells as described below and explained in further detail with respect to Fig. 2.

[0024] Fig. 1 shows a layer stack configured for use in an optoelectronic conversion module, such as a thin-film layer cell, a TFT of a display, an optoelectronic diode or the like. The layer stack includes a substrate 102, such as a transparent substrate, which can be a glass substrate, polymer substrate, or other suitable substrate, with thin films formed thereover. The layer stack, e.g., a precursor for a solar cell, further includes a first transparent conducting oxide (TCO) layer 104 formed over the substrate 102, and a junction, which can be a p-i-n junction or an n-i-p junction formed over the first TCO layer 104. According to embodiments described herein, the junction includes a first conductive-type layer 105 (e.g., a p-layer), an intrinsic-type layer 108, and a second conductive-type layer 110 with a conductivity opposite to the first conductive-type layer (e.g., an n-layer). Thereby, the second conductive type layer 110 shown in Fig. 1 is a doped SiOx layer, which is deposited in a CVD processing system. For example, the second conductive type layer, which is provided between the intrinsic layer and the back contact 124 can include at least 5 % by weight oxygen.

[0025] As shown for other embodiments described herein, the precursor for a thin-film solar cell as shown in Fig. 1 can further include a back contact layer, which can, for example be manufactured by sputtering ZnO and Ag or ZnO and Al. Generally, the metal back layer may include, but is not limited to a material selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, alloys thereof, or combinations thereof. According to typical implementations, a scribing process such as a laser scribing process can further be performed to form the solar cell. Other films, materials, substrates, and/or packaging may be provided over the metal back layer to complete the solar cell device. The formed solar cells may be interconnected to form modules, which in turn can be connected to form arrays.

[0026] According to embodiments described herein, a sensitivity to air exposure during the production for the time period between the deposition of the silicon layers and the deposition of the back contact can be reduced. The time between these two deposition steps, i.e. CVD and PVD, can vary during production significantly, e.g. between 2 and 36 hours. This might result in a change of precursor characteristics, e.g. the short circuit current may increase while the FF decreases (-1% for tandem junction and 5% for SJ). Due to the modified second conductive-type layer, e.g. an n-layer including oxygen such as SiOx, the current and thus the efficiency of solar panels can increase and furthermore the sensitivity to air disappears.

[0027] According to typical embodiments described herein, which can be combined with other embodiments described herein, the second conductive- type layer can be a phosphorous doped microcrystalline silicon- siliconoxide alloy. Typically, the alloy can be deposited with PECVD using a mixture of silane, phosphine, hydrogen and C0₂. Other gases like disilane, N20 or others might also be suitable to get similar layers. The microcrystalline layer, such as an n-layer, includes oxygen (and optionally carbon) and has a lower optical absorption compared to common amorphous or microcrystalline n-layers usually used in thin film silicon solar cells. The lower optical absorption can be achieved by alloying the μΰ-8ί material with silicon oxide by adding C0₂ to the gas phase during deposition. The microcrystalline fraction of the material ensures a good electrical transport, in particular perpendicular to the substrate plane by forming microcrystalline chains. The μΰ-8ί fraction also enables good doping efficiency. Yet further, embodiments described herein allow for adaptation of the layer characteristics such that a highly doped μΰ-8ί phase results in a good low resistive contact to the following ZnO-layer of the back contact. Yet further, the incorporated oxygen in the second conductive-type layer makes the layer less sensitive to oxidation by ambient air.

[0028] Thin-film solar cells are generally formed from numerous types of films, or layers, combined in many different ways. Most films used in such devices incorporate a semiconductor element that may include silicon, germanium, carbon, boron, phosphorous, nitrogen, oxygen, hydrogen, and the like. Characteristics of the different films include degree of crystallinity, dopant type, dopant concentration, film refractive index, film extinction coefficient, film transparency, film absorption, and conductivity. Typically, most of these films can be formed by use of a chemical vapor deposition process, which may include some degree of ionization, plasma formation and/or sputtering processes.

[0029] The term "coating" and the term "depositing" are used synonymously herein. The terms "CVD installation" and "deposition apparatus" are used synonymously herein and shall embrace, for example, an apparatus which uses CVD processes for depositing material, typically as a thin film, on a substrate.

[0030] However, layer such as the TCO layer or the back contact layer can efficiently be manufactured by sputtering processes, e.g. from rotatable targets. [0031] According to different embodiments, a plurality of films can be used in solar cells. Charge generation during a photovoltaic process is generally provided by a bulk semiconductor layer, such as a silicon-containing layer. The bulk layer is also sometimes called an intrinsic layer to distinguish it from the various doped layers present in the solar cell. The intrinsic layer may have any desired degree of crystallinity, which will influence its light-absorbing characteristics. For example, an amorphous intrinsic layer, such as amorphous silicon, will generally absorb light at different wavelengths from intrinsic layers having different degrees of crystallinity, such as microcrystalline silicon. For this reason, most solar cells will use both types of layers to yield the broadest possible absorption characteristics. In some instances, an intrinsic layer may be used as a buffer layer between two dissimilar layer types to provide a smoother transition in optical or electrical properties between the two layers.

[0032] Silicon and other semiconductors can be formed into solids having varying degrees of crystallinity. Solids having essentially no crystallinity are amorphous, and silicon with negligible crystallinity is referred to as amorphous silicon. Completely crystalline silicon is referred to as crystalline, polycrystalline, or monocrystalline silicon. Polycrystalline silicon is crystalline silicon formed into numerous crystal grains separated by grain boundaries. Monocrystalline silicon is a single crystal of silicon. Solids having partial crystallinity, that is a crystal fraction between about 5% and about 95%, are referred to as nanocrystalline or microcrystalline, generally referring to the size of crystal grains suspended in an amorphous phase. Solids having larger crystal grains are referred to as microcrystalline, whereas those with smaller crystal grains are nanocrystalline. It should be noted that the term "crystalline silicon", in general and as used herein, may refer to any form of silicon having a crystal phase, including microcrystalline and nanocrystalline silicon. Nevertheless, some embodiments described herein, may refer to specific forms of crystallinity in order to distinguish over other forms of crystallinity.

[0033] Fig. 1 shows a layer stack configured for use in an optoelectronic conversion module, such as a thin-film layer cell, a TFT of a display, an optoelectronic diode or the like. The layer stack includes a substrate 102, such as a transparent substrate, which can be a glass substrate, polymer substrate, or other suitable substrate, with thin films formed thereover. The layer stack, e.g., a precursor for a solar cell, further includes a first transparent conducting oxide (TCO) layer 104 formed over the substrate 102, and a junction, which can be a p-i-n junction or an n-i-p junction formed over the first TCO layer 104. According to embodiments described herein, the junction includes a first conductive-type layer 105 (e.g., a p-layer), an intrinsic-type layer 108, and a second conductive-type layer 110 with a conductivity opposite to the first conductive-type layer (e.g., an n-layer). [0034] FIG. 2 is a schematic diagram of an embodiment of a multi-junction solar cell 100 oriented toward the light or solar radiation 101. Solar cell 100 includes a substrate 102, such as a glass substrate, polymer substrate, metal substrate, or other suitable substrate, with thin films formed thereover. The solar cell 100 further includes a first transparent conducting oxide (TCO) layer 104 formed over the substrate 102, and a first p-i-n junction 126 formed over the first TCO layer 104. In one configuration, a wavelength selective reflector (WSR) layer 112 is formed over the first p-i-n junction 126. A second p-i-n junction 128 is formed over the first p-i-n junction 126, a second TCO layer 122 is formed over the second p-i-n junction 128, and a metal back layer 124 is formed over the second TCO layer 122. In one embodiment, a WSR layer 112 is disposed between the first p-i-n junction 126 and the second p-i-n junction 128, and is configured to have film properties that improve light scattering and current generation in the formed solar cell 100. Additionally, the WSR layer 112 also provides a good p-n tunnel junction that has a high electrical conductivity and a tailored bandgap range that affects its transmissive and reflective properties to improve the formed solar cell's light conversion efficiency.

[0035] To improve light absorption by enhancing light trapping, the substrate and/or one or more of the thin films formed thereover may be optionally textured by wet, plasma, ion etching, and/or mechanical processes. For example, in the embodiment shown in FIG. 2, the first TCO layer 104 is textured and the subsequent thin films deposited thereover will generally follow the topography of the surface below it. [0036] According to some embodiments described herein, a further layer such as a buffer layer is deposited between the substrate 102 and the TCO layer 104. Thereby, typically, the further layer can be a SiON-containing layer. The further layer is provided in order to have an improved nucleation of the transparent conductive oxide (TCO) layer, such as a ZnO-containing TCO layer. Accordingly, the substrate including, e.g., a buffer layer is conditioned for improved ZnO growth. According to embodiments described herein, the further layer includes a metal such as Al, Ti, Zn, or the like. Thereby, nucleation of the TCO layer can be influenced to provide for improved texturing and desired electrical and optical properties of the TCO layer. According to some embodiments, the conditioning can be conducted by depositing or preparing a metal-containing layer, e.g., that the layer is doped with a metal.

[0037] The first TCO layer 104 and the second TCO layer 122 may each include tin oxide, zinc oxide, indium tin oxide, cadmium stannate, combinations thereof, or other suitable materials. It is understood that the TCO materials may also include additional dopants and components. For example, zinc oxide may further include dopants such as aluminum, gallium, boron, and other suitable dopants. Zinc oxide preferably includes 5 atomic % or less of dopants, and more preferably includes 2.5 atomic % or less aluminum. In certain instances, the substrate 102 may be provided by the glass manufacturers with the first TCO layer 104 already provided. [0038] The first p-i-n junction 126 may include a p-type amorphous silicon layer 106, an intrinsic-type amorphous silicon layer 108 formed over the p-type amorphous silicon layer 106, and an n-type microcrystalline silicon layer 110 formed over the intrinsic-type amorphous silicon layer 108.

[0039] According to further embodiments, which can be combined with other embodiments described herein, the first p-i-n junction 126 may include an optional p-i buffer- type intrinsic amorphous silicon (PIB) layer 116 that is formed over the p-type silicon layer 106. In certain embodiments, the p-i buffer- type intrinsic amorphous silicon (PIB) layer 116 may be formed to a thickness between about 50 A and about 500 A. [0040] According to embodiments described herein, an anti-reflections layer 105 is deposited within the p-type layer or as a part of the p-type layer, i.e., the first layer of the p-i-n junction or an n-i-p junction of the first conductive-type.

[0041] In certain embodiments, the p-type amorphous silicon layer 106 may be formed to a thickness between about 60A and about 300A. In certain embodiments, the intrinsic-type amorphous silicon layer 108 may be formed to a thickness between about 1,500A and about 3,500A. In certain embodiments, the n-type microcrystalline semiconductor layer 110 may be formed to a thickness between about 100A and about 400A. [0042] The WSR layer 112 disposed between the first p-i-n junction 126 and the second p-i-n junction 128 is generally configured to have certain desired film properties. In this configuration, the WSR layer 112 actively serves as an intermediate reflector having a desired refractive index, or ranges of refractive indexes, to reflect light received from the light incident side of the solar cell 100. The WSR layer 112 also serves as a junction layer that boosts the absorption of the short to mid wavelengths of light (e.g., 400 nm to 700 nm) in the first p-i-n junction 126 and improves short-circuit current, resulting in improved quantum and conversion efficiency. Further, the WSR layer 112 has high film transmittance for mid to long wavelengths of light (e.g., 500nm to l lOOnm) to facilitate the transmission of light to the layers formed in the junction 128. Further, it is generally desirable for the WSR layer 112 to absorb as little light as possible while reflecting desirable wavelengths of light (e.g., shorter wavelengths) back to the layers in the first p-i-n junction 126 and transmitting desirable wavelengths of light (e.g., longer wavelengths) to the layers in the second p-i-n junction 128.

[0043] The second p-i-n junction 128 may include a p-type microcrystalline silicon layer 114 and, in some cases, an optional p-i buffer- type intrinsic amorphous silicon (PIB) layer 116' that is formed over the p-type microcrystalline silicon layer 114. Subsequently, an intrinsic-type microcrystalline silicon layer 118 is formed over the p-type microcrystalline silicon layer 114, and an n-type amorphous silicon layer 120 is formed over the intrinsic type microcrystalline silicon layer 118. In certain embodiments, the p-type microcrystalline silicon layer 114 may be formed to a thickness between about 100A and about 400A. In certain embodiments, the p-i buffer- type intrinsic amorphous silicon (PIB) layer 116' may be formed to a thickness between about 50 A and about 500 A. In certain embodiments, the intrinsic- type microcrystalline silicon layer 118 may be formed to a thickness between about 7,000A and about 25,000A. In certain embodiments, the n-type amorphous silicon layer 120 may be formed to a thickness between about 100 A and about 500A.

[0044] The metal back layer 124 may include, but is not limited to a material selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, alloys thereof, or combinations thereof. Other processes may be performed to form the solar cell 100, such as laser scribing processes. Other films, materials, substrates, and/or packaging may be provided over the metal back layer 124 to complete the solar cell device. The formed solar cells may be interconnected to form modules, which in turn can be connected to form arrays.

[0045] According to embodiments described herein, the first p-i-n junction 126 and the second p-i-n junction 128 are deposited with CVD process such as PECVD. The second TCO layer 122 and the metal back contact layer are deposited with a PVD deposition method such as sputtering. Accordingly, it is desirable to provide the second conductive-type layer, the n-type amorphous silicon layer 120 in Fig. 2, such that deposition by PVD of layers 122 and 124 after deposition by CVD of layer 120 is not influenced by process control of a complete factory street. Accordingly, the second conductive-type layer 120 can be provided as a doped microcrystalline silicon-siliconoxide alloy. Typically, the alloy can be deposited with PECVD using a mixture of silane, phosphine, hydrogen and C0₂.

[0046] Solar radiation 101 is primarily absorbed by the intrinsic layers 108, 118 of the p-i-n junctions 126, 128 and is converted to electron-hole pairs. The electric field created between the p-type layer 106, 114 and the n-type layer 110, 120 that stretches across the intrinsic layer 108, 118 causes electrons to flow toward the n-type layers 110, 120 and holes to flow toward the p-type layers 106, 114 creating a current. According to some embodiments, which can be combined with other embodiments described herein, the first p-i-n junction 126 includes an intrinsic type amorphous silicon layer 108 and the second p-i-n junction 128 includes an intrinsic-type microcrystalline silicon layer 118 since amorphous silicon and microcrystalline silicon absorb different wavelengths of the solar radiation 101. Therefore, the formed solar cell 100 is more efficient, since it captures a larger portion of the solar radiation spectrum. The intrinsic layer 108, 118 of amorphous silicon and the intrinsic layer of microcrystalline silicon are stacked in such a way that solar radiation 101 first strikes the intrinsic type amorphous silicon layer 118 and is transmitted through the WSR layer 112 and then strikes the intrinsic type microcrystalline silicon layer 118 since amorphous silicon has a larger bandgap than microcrystalline silicon. Solar radiation not absorbed by the first p-i-n junction 126 continuously transmits through the WSR layer 112 and continues to the second p-i-n junction 128.

[0047] Charge collection is generally provided by doped semiconductor layers, such as silicon layers doped with p-type or n-type dopants. P-type dopants are generally group III elements, such as boron or aluminum. N-type dopants are generally group V elements, such as phosphorus, arsenic, or antimony. In most embodiments, boron is used as the p-type dopant and phosphorus as the n-type dopant. These dopants may be added to the p-type and n-type layers 106, 110, 114, 120 described above by including boron- containing or phosphorus-containing compounds in the reaction mixture. Suitable boron and phosphorus compounds generally include substituted and unsubstituted lower borane and phosphine oligomers. Some suitable boron compounds include trimethylboron (B(CH₃)₃ or TMB), diborane (B₂H6), boron trifluoride (BF₃), and triethylboron (B(C₂Hs)₃ or TEB). Phosphine is the most common phosphorus compound. The dopants are generally provided with carrier gases, such as hydrogen, helium, argon, and other suitable gases. If hydrogen is used as the carrier gas, it adds to the total hydrogen in the reaction mixture. Thus, hydrogen ratios will include hydrogen used as a carrier gas for dopants.

[0048] According to embodiments described herein, the best known methods have been further adapted by providing second conductive-type layers (e.g., n-layers) with C0₂ addition during deposition and/or with additional C0₂-plasma treatment after the n-layer deposition in the CVD chamber. Thereby, a doped SiOx layer has been deposited as the second-conductive type layer or as a portion of the second conductive-type layer.

[0049] According to different embodiments, a plurality of methods, systems, and apparatus configurations for providing a precursor for a solar cell having an improved second conductive-type layer between the intrinsic layer and the back contact structure of a TCO and a metal layer. This can be typically the second conductive-type layer of a single junction, the second conductive-type layer of the bottom cell of a tandem junction or the second conductive-type layer of the junction closest to the back contact if more than two junctions are provided. Figure 3 illustrates one embodiment of a precursor for a solar cell. The corresponding method of manufacturing a layer stack adapted for use in a thin film solar cell, according to embodiments described herein, is described in figure 4. A TCO layer 104 is deposited over a substrate 102. A corresponding method step is indicated by step 402 in figure 4. In step 404, the first conductive-type layer 106 of the p-i-n junction 126 is deposited. According to typical embodiments, the first conductive-type layer can be a p- type layer.

[0050] According to different embodiments, which can be combined with other embodiments described herein, the first conductivity-type layer, the i- layer and the second conductivity-type layer having a conductivity opposite to the first conductivity-type layer form a p-i-n junction or an n-i-p junction, respectively. The examples provided herein generally refer to p-i-n junctions, wherein the first conductivity-type layer is a p-layer and the second conductivity-type layer is an n-layer. It is to be understood that the first conductivity-type layer can also be an n-layer and the second conductivity-type layer can be a p-layer. Thereby, also a p-i-n junctions or an n-i-p junction can be formed.

[0051] Typically, the junction 126 is deposited by chemical vapor deposition. In step 406, an intrinsic portion of the junction is deposited. Thereafter the deposition of the second conductive-type layer 410 is started in step 408. In step 410 an SiOx containing portion of the second conductive- type layer, e.g., the n-type layer 210, is provided as shown in figure 3. Figure 3 further shows a back contact 124. Typically, a further TCO layer is provided between layer 210 and the back contact layer 124.

[0052] The SiOx layer 210 being a part of the second conductive-type layer can be deposited between a first portion of the second conductivity-type layer and the subsequent layer, which is deposited by PVD. According to yet further embodiments, which can be combined with other embodiments described herein, the SiOx layer can be deposited as the only layer having the second conductivity type, with one other layer or portion of the second conductivity- type, or with several other layers of the second conductivity type.

[0053] According to embodiments, which can be combined with other embodiments described herein, the second conductivity- type layer 210 is a SiOx-containing layer. For example, the layer 210 can include a microcrystalline or nanocrystalline SiOx material that can, e.g., be doped. Typically, the microcrystalline silicon oxide material can be p-or n-doped by boron or phosphorus. According to typical embodiments, which can be combined with other embodiments described herein, the refraction index of the layer 210 can be tuned by adjusting or varying the oxygen content of the SiOx material. Accordingly, by the refraction index can be between 2.5 and 3.8. [0054] According to further embodiments, which may be combined with other embodiments described herein, the SiOx-containing layer of the second conductive-type can be deposited by adding C0₂ in the processing region of the CVD processing chamber. Typically, by variation of the oxygen content in the layer various properties of the layer can be tuned. Thus, according to methods described herein, the C0₂ content in the process gas can be varied for optimizing the process and can typically be in a range of 50 seem to 300 seem for manufacturing a GEN 5 module, which results in about 35 sccm/m² per substrate area to about 210 sccm/m² per substrate area, e.g. 70 sccm/m² per substrate area. By increasing the C0₂ concentration in the processing region as described above, the refraction index can, for example, be reduced from about 3.0 to about 2.2, while the band gap is increased from about 2.15 eV to about 2.45 eV, the conductivity is reduced from about 1*10 -^"3 S/cm² to about 5*10 -^"9 S/cm², and the crystalline fraction is reduced from about 0.6 to 0.

[0055] According to embodiments described herein, doped a-SiOx and μΰ- SiOx single layers, e.g. n-doped layers, have compared to an amorphous Si-n- layer a 2 to 3 times lower absorption in the entire spectral range due to the addition of C0₂ in the CVD process. At the same time dark conductivity of 10^"5 S/cm and above can be achieved an a-SiOx n-layer and about 0.3 S/cm for a μΰ-8ίΟχ n-layer. Further, the second conductive-type layer utilized for embodiments describe herein, results in an increase of the Isc (short circuit current) for these new n-layers. A large increase of the Isc of 7% can be observed for the C0₂ a plasma treated layer. This is, however, accompanied by a loss of the fill factor (FF) and Voc- A current gain can also be confirmed by quantum efficiency (QE) measurements. Thereby, also a 3% current gain for the

and 7% current gain for the C0₂ plasma treated cell can be observed. It could be shown that, according to some embodiment described herein, providing a μΰ-8ίΟχ second conductive-type layer, e.g., an n-layer, results in a significant increase of the module power and a very good stability with respect to the time between CVD and PVD. This could be verified by applying different times between CVD and PVD and still obtaining a very narrow distribution of all I-V-parameters.

[0056] Yet further typical embodiments of a solar cell precursor, such as a layer stack for a thin-film solar cell and the manufacturing thereof, are illustrated in figures 5A to 51 and in figure 6. As shown in figure 5A, a buffer layer 103 is deposited on the substrate 102. Thereafter, the TCO layer 104, for example a doped ZnO layer, is provided over the substrate as indicated by step 602 in figure 6. Figure 5 A shows the TCO layer 104 being textured for improved light trapping. Typically, a doped ZnO layer is deposited by a DC- sputtering process as a TCO front contact with a thickness of about 800 - 1000 nm. The dopant can be, but is not limited to, aluminum. Finally, the layer stack is etched in diluted acid in order to roughen the ZnO surface by wet etching. The textured transparent conductive oxide layer can have a layer thickness of, for example, 400 nm to 700 nm, typically 400 nm to 600 nm, wherein the thickness of the texture surface is measured with X-ray fluorescence (XRF).

[0057] Examples of a TCO layers, particularly ZnO-containing TCO layers are described in patent application Ser. No. 12/854,469, entitled " Thin film solar fabrication process, deposition method for TCO layer, and solar cell precursor layer stack" filed August 11, 2010 and U.S. patent application Ser. No. 12/840,039, entitled " Thin Film Solar Fabrication Process, Deposition method for TCO layer, and Solar cell precursor layer stack" filed July 20, 2010, both of which are incorporated herein by reference to the extent the applications are not inconsistent with this disclosure.

[0058] In step 604, a first p-i-n junction is deposited. Thereby, a layer 506 of the first conductive-type such as a

is deposited on the doped and textured ZnO layer. Typically, the

can have a layer thickness of 2 nm to 10 nm. Thereafter, as shown in Fig. 5C, an anti-reflection layer 505 can be deposited. Even though not shown in all detail in Fig. 5C, according to some embodiments, which can be combined with other embodiments described herein, a SiOx-containing anti-reflection layer 505 can include several anti-reflection layers or anti-reflection sub-layers. According to a typical modification, these layers can be μΰ(ρ)-8ίΟχ, μΰ(ρ)8 ϋ, nc(p)SiOx, nc(p)SiC, a(p)-SiOx, and a(p)SiC. Thereby, the crystalline fraction is reduced continuously, e.g., by increasing the C0₂ during the CVD process from the μΰ- layer to the a-layer. Thus, the one or more SiOx-containing layers can be deposited by adding C0₂ in the processing region of the CVD processing chamber. Typically, the stack of anti-reflection layers can have a thickness of about 10 nm to 50 nm. Examples of a anti-reflection layers, particularly SiOx- containing ant-reflection layers are described in patent application Ser. No. 12/878,804, entitled "Thin-film solar fabrication process, deposition method for solar cell precursor layer stack, and solar cell precursor layer stack" filed September 9, 2010 which is incorporated herein by reference to the extent the applications are not inconsistent with this disclosure. [0059] In step 604, a further conductive-type layer 507 (see, e.g., Fig. 5D) having the same conductive-type as the layer 506 is provided. For example, the layer 507 can be an a-Si(p)-layer, which is deposited over an a(p)-SiOx layer described above as part of the anti-reflection layer 505 or as a further anti-reflection layer. Further in step 604, an i-type layer 108 (see Fig. 5E), which acts as an absorber layer in the top cell, is deposited by PECVD before an n-type layer 110 (see Fig. 5F) is deposited. Thereby, a first p-i-n junction is deposited including layers 506, 505, 507, 108, and 110.

[0060] In step 606 an intermediate layer 112 is deposited, which can serve as a wavelength selective reflection layer. Further, a first conductive-type layer 114 (e.g. an p-layer) and an intrinsic layer of the bottom cell are deposited in steps 606 and 610, respectively. The resulting layer stack is shown in Fig 5G. In step 612 an SiOx containing layer 120 providing the second conductive-type layer is deposited as shown in Fig. 5H. The SiOx- containing layer of the second conductive-type, typically a μΰ- SiOx- containing layer forming a doped microcrystalline silicon-siliconoxide alloy, can be deposited by adding C0₂ in the processing region of the CVD processing chamber. Typically, by variation of the oxygen content in the layer various properties of the layer can be tuned. According to typical embodiments for manufacturing the layer stack, at least one of the steps can be provided for manufacturing the second conductive-type layer, which are selected from the group: providing a C0₂ gas flow of 70 seem to 120 seem, e.g. for a Gen 5 module, providing a ratio of C0₂/silane gas flow of 0.7 to 1.3, and providing RF power of 2000W to 7000W for the CVD process, e.g. for a Gen 5 module.

[0061] According to yet further embodiment, which can be combined with other embodiments, a layer stack for a solar cell, such as typically a tandem module can further increased in cell efficiency if a a-SiO_x layer of the second conductive type is introduced between the i-layer and the μΰ-8ίΟ_χ n-layer (not shown in FIGS. 5). This can be provided by flowing a process gas including C0₂ in the processing region and adapting the growth parameters for deposition of an amorphous layer. [0062] As shown in Figure 51, a back contact can be formed by sputtering a TCO layer (see step 614) and a metal back contact layer (see step 616). Typically, the second TCO layer 122 may include tin oxide, zinc oxide, indium tin oxide, cadmium stannate, combinations thereof, or other suitable materials. It is understood that the TCO materials may also include additional dopants and components. For example, zinc oxide may further include dopants such as aluminum, gallium, boron, and other suitable dopants. Zinc oxide preferably includes 5 atomic % or less of dopants, and more preferably includes 2.5 atomic % or less aluminum. The back contact layer can, for example, be manufactured by sputtering Ag or Al after sputtering ZnO, each being sputtered from a rotatable target. Generally, the metal back layer may include, but is not limited to a material selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, alloys thereof, or combinations thereof.

[0063] Some of the above described embodiments refer to a single junction or a tandem junction having a first and a second p-i-n junction, e.g., a top cell and a bottom cell, and an anti-reflection layer. However, this is not to be understood as limiting to the invention. According to modifications thereof, additionally a third, forth, or fifth p-i-n junction can be provided, wherein according to typical modifications between one or more boundaries of the further p-i-n junctions a corresponding WSR layer can be provided.

[0064] According to embodiments described herein, a precursor for a solar cell is deposited on an industrially-relevant scale. For example, the layers of some embodiments described herein can be deposited on an area of 1 m² and above, 4 m² and above, or 5 m² and above. Thereby, the surface on which the layers are to be deposited and the layers themselves need to be provided with a predetermined uniformity on a large scale. According to some embodiments, which can be combined with other embodiments described herein, the solar cell precursors, the layer stacks for solar cells, and the methods and devices for manufacturing layers can be utilized for large-area thin films. For example, substrate sizes of 1.43 m² (Gen5) and above, such as 5.7 m² (Gen8.5) or larger, can be realized. [0065] According to embodiments described herein, it is possible to deposit SiOx containing layers of a second conductive-type, such as an n-type oxygen containing layer within a chemical vapor deposition process for manufacturing a solar cell layer stack. Thereby, reducing of the influence between the time of a CVD process and a subsequent PVD process can be applied on large area substrates as referred to in some embodiments herein. Further, as described above, the layer properties of the SiOx-containing material such as, for example, band gap, refraction index, conductivity, and crystal fraction can be tuned in large ranges in order to provide the desired electrical and optical properties or electrical and optical property gradings.

[0066] According to yet further embodiments, which can be combined with other embodiments described herein, the doped SiOx layers (p- or n-doped) with the above described properties for being contacted by a contact layer can also be used for other applications, particularly electro-optical applications such as diodes or thin film transistors.

[0067] Figures 7 and 8 illustrate a processing system 800 and a processing chamber 901 that may be used to form a portion of the solar cell, discussed above. Figure 7 is a top schematic view of one embodiment of a processing system 800, which may be one of the one or more cluster tools. The processing system 800 can thus be used to perform one or more processing steps that are used to form the various layers or regions of the solar cell device. The processing system 800 will generally contain a plurality of process chambers 881-887, such as a plasma enhanced chemical vapor deposition (PECVD) chamber 901 (Figure 8), capable of depositing one or more desired layers onto the substrate surface. The process system 800 includes a transfer chamber 870 coupled to a load lock chamber 860 and the process chambers 881-887. The load lock chamber 860 allows substrates to be transferred between the ambient environment outside the system and the vacuum environment within the transfer chamber 870 and process chambers 881-887. The load lock chamber 860 includes one or more evacuatable regions holding one or more substrates. The evacuatable regions are pumped down during input of substrates into the system 800 and are vented during output of the substrates from the system 800. The transfer chamber 870 has at least one vacuum robot 872 disposed therein that is adapted for transferring substrates between the load lock chamber 860 and the process chambers 881-887. While seven process chambers are shown in Figure 7, the system 800 may have any suitable number of process chambers.

[0068] Figure 8 is a schematic cross-section view of one embodiment of a processing chamber, such as a PECVD chamber 901, in which one or more films of a solar cell may be deposited. One suitable plasma enhanced chemical vapor deposition chamber is available from Applied Materials, Inc., located in Santa Clara, CA. It is contemplated that other deposition chambers, such as hot wire chemical vapor deposition (HWCVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), evaporation, or other similar devices, including those from other manufacturers, may be utilized to practice the present invention. In one embodiment, the chamber 901 generally includes walls 902, a bottom 904, a showerhead 910, and a substrate support 930 which define a process volume 906. The process volume is accessed through a valve 908 such that the substrate, such as substrate 102, may be transferred in and out of the PECVD chamber 901. The substrate support 930 includes a substrate receiving surface for supporting a substrate and stem 934 coupled to a lift system 936 to raise and lower the substrate support 930. A shadow frame 933 may be optionally placed over the periphery of the device substrate that may already have one or more layers formed thereon, for example, the TCO layer. Lift pins can be moveably disposed through the substrate support 930 to move a substrate to and from the substrate receiving surface. The substrate support 930 may also include heating and/or cooling elements to maintain the substrate support 930 at a desired temperature. The substrate support 930 may also include grounding straps to provide RF grounding at the periphery of the substrate support 930. Examples of grounding straps are disclosed in U.S. Patent 6,024,044 issued on Feb. 15, 2000 to Law et al. and U.S. Patent Application 11/613,934 filed on Dec. 20, 2006 to Park et al., which are both incorporated by reference in their entirety to the extent not inconsistent with the present disclosure. [0069] The showerhead 910 is coupled to a backing plate 912 at its periphery by a suspension 914. The showerhead 910 may also be coupled to the backing plate by one or more center supports 916 to help prevent sag and/or to control the straightness/curvature of the showerhead 910. A gas source 920 is coupled to the backing plate 912 to provide gas through the backing plate 912 and through the plurality of holes 911 in the showerhead 910 to the substrate receiving surface. A vacuum pump 909 is coupled to the PECVD chamber 901 to control the process volume 906 at a desired pressure. An RF power source 922 is coupled to the backing plate 912 and/or to the showerhead 910 to provide an RF power to the showerhead 910 so that an electric field is created between the showerhead and the substrate support so that a plasma may be generated from the gases between the showerhead 910 and the substrate support 930. Various RF frequencies may be used, such as a frequency between about 0.3 MHz and about 200 MHz. In one embodiment, the RF power source is provided at a frequency of 13.56 MHz. Examples of showerheads are disclosed in U.S. Patent 6,477,980 issued on November 12, 2002, to White et al., U.S. Publication 20050251990 published on November 17, 2006, to Choi et al., and U.S. Publication 2006/0060138 published on March 23, 2006, to Keller et al, which are all incorporated by reference in their entirety to the extent not inconsistent with the present disclosure.

[0070] A remote plasma source 924, such as an inductively coupled remote plasma source, may also be coupled between the gas source and the backing plate. Between processing substrates, a cleaning gas may be provided to the remote plasma source 924 so that a remote plasma is generated and provided to clean chamber components. The cleaning gas may be further excited by the RF power source 922 provided to the showerhead. Suitable cleaning gases include but are not limited to NF3, F2, and SF6. Examples of remote plasma sources are disclosed in U.S. Patent 5,788,778 issued August 4, 1998 to Shang et al, which is incorporated by reference to the extent not inconsistent with the present disclosure.

[0071] Referring back to Figure 7, in one embodiment of the system 800, one of the process chambers 881-887 is configured to deposit a p-type silicon layer(s) of a first p-i-n junction 126 or a second p-i-n junction 128 of a solar cell device, another one of the process chambers 881-887 is configured to deposit an intrinsic silicon layer of the first or the second p-i-n junction, and another of the process chambers 881-887 is configured to deposit the n-type silicon layer(s) of the first or the second p-i-n junction. While a three chamber process configuration may have some contamination control advantages, it will generally have a lower substrate throughput than a two chamber processing system, and generally cannot maintain a desirable throughput when one or more of the processing chambers is undergoing maintenance. [0072] In one example, in which the substrate processing sequence is performed in a system configured similarly to the processing system 800, a substrate enters the processing system 800 through the load lock chamber 860. The substrate is then transferred by the vacuum robot 872 into the process chamber 881 that is configured to deposit a p-type silicon layer(s) on the substrate. After depositing the p-type layer in process chamber 881, the substrate is then transferred by the vacuum robot 872 into the process chamber 884 that is configured to deposit both the intrinsic-type silicon layer(s) and the n-type silicon layer(s). After depositing the intrinsic-type layer(s) and n-type layer(s) in process chamber 884, the intermediate layer is deposited after the substrate is transferred to chamber 885, before a second p-i-n junction is deposited and the substrate is returned to the load lock chamber 460, after which the substrate can be removed from the system. Assuming that the p-type layer is 150A in thickness and the deposition rate is 500A per minute, the period of time to deposit the p-type layer is approximately 0.3 minutes. For an intrinsic layer of 2,700A at a deposition rate of 220A/min., the time period to deposit the intrinsic layer is approximately 12.3 minutes. Assuming an n-type layer of 250A at a deposition rate of 500A per minute, it will require approximately 0.5 minute to deposit the n-type layer. It can therefore be seen that if one chamber is dedicated to the deposition of a p-type layer and multiple chambers are dedicated to the deposition of the intrinsic and n-type layers, an increased throughput of substrates can be realized by increasing the number of processing chambers that can produce the i-n layers in parallel. That is, a continuous series of substrates can be loaded and maneuvered by the transfer chamber 870 from a process chamber that is adapted to deposit a p-type layer, such as process chamber 881, and then each of the substrates can be transferred to at least one subsequent processing chamber, such as process chambers 882 through 848 and 846 to 487 to form the i-n layers.

[0073] In light of the above, a plurality of embodiments has been described. According to one embodiment, a method of manufacturing a layer stack adapted for a thin-film solar cell is provided. The method includes depositing a first conductivity-type silicon-containing layer for a p-i-n-junction of a solar cell, depositing an intrinsic-type silicon containing layer for a p-i-n- junction of a solar cell, depositing a second conductivity-type layer with a conductivity-type opposite to the first conductivity-type layer, and providing a back contact, wherein the second conductivity type layer is deposited between the intrinsic-type layer and the back contact, and wherein the further conductivity-type layer is deposited by chemical vapor deposition using C0₂ or N₂0. According to a yet further particular embodiment, the method can further include: depositing a third SiOx-containing conductivity-type layer having the same conductivity type as the further conductivity type layer between the intrinsic layer and the further conductivity-type layer. According to yet further alternative or additional modifications the third SiOx-containing conductivity- type layer can be an amorphous layer; the second conductivity-type layer can be a microcrystalline SiOx-layer; and/or the depositing the second conductivity-type layer can include flowing a gas mixture including at least silane, a phosphine-containing gas, hydrogen and C0₂ in a deposition region of the chemical vapor deposition process. According to yet further embodiments, which can be combined with other embodiments described herein the flow of C0₂ in the deposition region can be between 35 sccm/m² and 210 sccm/m² per substrate area and/or the first conductivity-type layer is a p-type layer and the second and the third conductivity-type layers are an n-type layer. [0074] According to another embodiment, a precursor for a solar cell is provided, the precursor includes a transparent substrate, a first conductivity- type silicon-containing layer for a p-i-n-junction of a solar cell, an intrinsic - type silicon containing layer for a p-i-n-junction of a solar cell, a second conductivity-type layer with a conductivity-type opposite to the first conductivity-type layer, and a back contact, wherein the second conductivity- type layer is deposited between the intrinsic-type layer and the back contact, and wherein the further conductivity-type layer includes oxygen. According to further particular embodiments, the precursor can further include a third SiOx- containing conductivity-type layer between the intrinsic layer and the further conductivity-type layer, wherein the SiOx containing layer has the same conductivity type as the further conductivity type layer. According to yet further additional or alternative modifications, one or more of the following features can be included: the third SiOx-containing conductivity-type layer can be an amorphous layer; the second conductivity-type layer can be a microcrystalline SiOx-layer; the second conductivity-type layer can include carbon; the second conductivity-type layer can be a doped layer, particularly a phosphorous doped layer; and the first conductivity-type layer can be a p-type layer and the second and third conductivity- type layers can be an-type layers.

[0075] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method of manufacturing a layer stack adapted for a thin-film solar cell, the method comprising: depositing a first conductivity-type silicon-containing layer for a p-i-n- junction of a solar cell; depositing an intrinsic-type silicon containing layer for a p-i-n-junction of a solar cell; depositing a second conductivity-type layer with a conductivity- type opposite to the first conductivity-type layer; and providing a back contact; wherein the second conductivity type layer is deposited between the intrinsic-type layer and the back contact, and wherein the further conductivity- type layer is deposited by chemical vapor deposition using C0₂ or N₂0.

2. The method according to claim 1, further comprising: depositing a third SiOx-containing conductivity-type layer having the same conductivity type as the further conductivity type layer between the intrinsic layer and the further conductivity-type layer.

3. The method according to claim 2, wherein the third SiOx-containing conductivity-type layer is an amorphous layer.

4. The method according to any of claims 1 to 3, wherein the second conductivity-type layer is a microcrystalline SiOx-layer.

5. The method according to any of claims 1 to 4, wherein the depositing the second conductivity- type layer comprises: flowing a gas mixture comprising at least silane, a phosphine- containing gas, hydrogen and C02 in a deposition region of the chemical vapor deposition process.

6. The method according to any of claims 1 to 5, wherein the flow of C02 in the deposition region is between 35 sccm/m² and 210 sccm/m² per substrate area.

7. The method according to any of claims 1 to 6, wherein the first conductivity- type layer is a p-type layer and the second and the third conductivity-type layers are an n-type layer.

8. A precursor for a solar cell, comprising: a transparent substrate; a first conductivity-type silicon-containing layer for a p-n-junction of a solar cell; an intrinsic-type silicon containing layer for a p-n-junction of a solar cell; and a second conductivity-type layer with a conductivity-type opposite to the first conductivity-type layer a back contact; wherein the second conductivity-type layer is deposited between the intrinsic-type layer and the back contact, and wherein the further conductivity- type layer comprises oxygen.

9. The precursor according to claim 8, further comprising: a third SiOx-containing conductivity-type layer between the intrinsic layer and the further conductivity-type layer, wherein the SiOx containing layer has the same conductivity type as the further conductivity type layer.

10. The precursor according to claim 9, wherein the third SiOx-containing conductivity-type layer is an amorphous layer.

11. The precursor according to any of claims 8 to 10, wherein the second conductivity- type layer is a microcrystalline SiOx-layer.

12. The precursor according to any of claims 8 to 11, wherein the second conductivity-type layer comprises carbon.

13. The precursor according to any of claims 8 to 12, wherein the second conductivity-type layer is a doped layer, particularly a phosphorous doped layer.

14. The precursor according to any of claims 8 to 13, wherein the first conductivity-type layer is a p-type layer and the second and third conductivity- type layers are an n-type layer.