WO2009040707A3 - Method of manufacturing a finfet - Google Patents
Method of manufacturing a finfet Download PDFInfo
- Publication number
- WO2009040707A3 WO2009040707A3 PCT/IB2008/053801 IB2008053801W WO2009040707A3 WO 2009040707 A3 WO2009040707 A3 WO 2009040707A3 IB 2008053801 W IB2008053801 W IB 2008053801W WO 2009040707 A3 WO2009040707 A3 WO 2009040707A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- implant
- anneal
- extension regions
- diffusion
- regions
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 3
- 239000007943 implant Substances 0.000 abstract 3
- 239000002019 doping agent Substances 0.000 abstract 2
- 230000002401 inhibitory effect Effects 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 abstract 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract 1
- 229910052799 carbon Inorganic materials 0.000 abstract 1
- 230000005669 field effect Effects 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A method of fabricating a fin field effect transistor (finFET) (10) is provided wherein diffusion inhibiting species, e.g. carbon, ions are implanted from above into the extension regions (20) before spacers are formed adjacent the gate (15) and a thermal anneal is carried out to activate the source/drain dopants. The anneal conditions are selected to cause the dopant ions to diffuse from the source and drain regions (16,18) into the neighbouring extension regions (20), thus avoiding the need for a dedicated extension implant step and providing a conformal doping profile. Furthermore, by providing the diffusion inhibiting species implant, and optionally an amorphising implant to the extension regions, the rate and profile of the diffusion can be easily controlled by adjusting the anneal parameters.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0718983A GB2455054B (en) | 2007-09-27 | 2007-09-27 | Method of manufacturing a finfet |
GB0718983.0 | 2007-09-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009040707A2 WO2009040707A2 (en) | 2009-04-02 |
WO2009040707A3 true WO2009040707A3 (en) | 2009-06-25 |
Family
ID=38701852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2008/053801 WO2009040707A2 (en) | 2007-09-27 | 2008-09-18 | Method of manufacturing a finfet |
Country Status (2)
Country | Link |
---|---|
GB (1) | GB2455054B (en) |
WO (1) | WO2009040707A2 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5770944B2 (en) * | 2011-09-30 | 2015-08-26 | インテル・コーポレーション | Non-planar transistor fin manufacturing |
US9368628B2 (en) * | 2012-07-05 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with high mobility and strain channel |
US20140103437A1 (en) * | 2012-10-15 | 2014-04-17 | Gold Standard Simulations Ltd. | Random Doping Fluctuation Resistant FinFET |
US9847404B2 (en) | 2013-07-06 | 2017-12-19 | Semiwise Limited | Fluctuation resistant FinFET |
CN104576384A (en) * | 2013-10-14 | 2015-04-29 | 中国科学院微电子研究所 | FinFET structure and manufacturing method thereof |
CN104733314B (en) * | 2013-12-18 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
CN110610866B (en) | 2013-12-27 | 2023-05-30 | 英特尔公司 | Diffused tip extension transistor |
WO2015127697A1 (en) * | 2014-02-25 | 2015-09-03 | Tsinghua University | Method for forming fin field effect transistor |
US9564518B2 (en) * | 2014-09-24 | 2017-02-07 | Qualcomm Incorporated | Method and apparatus for source-drain junction formation in a FinFET with in-situ doping |
JP2015213183A (en) * | 2015-06-25 | 2015-11-26 | インテル・コーポレーション | Non-planar transistor fin fabrication |
CN107026126B (en) | 2016-02-02 | 2021-01-26 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
US10115728B1 (en) | 2017-04-27 | 2018-10-30 | International Business Machines Corporation | Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared PFET and NFET trench |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5885861A (en) * | 1997-05-30 | 1999-03-23 | Advanced Micro Devices, Inc. | Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor |
US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US20030109119A1 (en) * | 2001-12-12 | 2003-06-12 | Srinivasan Chakravarthi | Fabrication of ultra shallow junctions from a solid source with fluorine implantation |
US20030207542A1 (en) * | 2002-05-06 | 2003-11-06 | P.R. Chidambaram | Fabrication of abrupt ultra-shallow junctions using angled pai and fluorine implant |
US20050051825A1 (en) * | 2003-09-09 | 2005-03-10 | Makoto Fujiwara | Semiconductor device and manufacturing method thereof |
US20050186742A1 (en) * | 2004-02-24 | 2005-08-25 | Chang-Woo Oh | Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same |
US20070026615A1 (en) * | 2005-07-27 | 2007-02-01 | Sinan Goktepeli | Method of forming a FINFET structure |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5514902A (en) * | 1993-09-16 | 1996-05-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having MOS transistor |
JPH08335560A (en) * | 1995-06-08 | 1996-12-17 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
US6194259B1 (en) * | 1997-06-27 | 2001-02-27 | Advanced Micro Devices, Inc. | Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants |
WO2001091169A1 (en) * | 2000-05-24 | 2001-11-29 | Infineon Technologies North America Corp. | Suppression of lateral dopant diffusion from source/drain regions of mosfets |
KR100499954B1 (en) * | 2003-08-30 | 2005-07-05 | 동부아남반도체 주식회사 | Method for manufacturing Field-Effect-Transistor of semiconductor device |
US20060068556A1 (en) * | 2004-09-27 | 2006-03-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
CN101313395B (en) * | 2005-12-09 | 2013-03-27 | 山米奎普公司 | System and method for the manufacture of semiconductor devices by the implantation of carbon clusters |
-
2007
- 2007-09-27 GB GB0718983A patent/GB2455054B/en not_active Expired - Fee Related
-
2008
- 2008-09-18 WO PCT/IB2008/053801 patent/WO2009040707A2/en active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5885861A (en) * | 1997-05-30 | 1999-03-23 | Advanced Micro Devices, Inc. | Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor |
US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US20030109119A1 (en) * | 2001-12-12 | 2003-06-12 | Srinivasan Chakravarthi | Fabrication of ultra shallow junctions from a solid source with fluorine implantation |
US20030207542A1 (en) * | 2002-05-06 | 2003-11-06 | P.R. Chidambaram | Fabrication of abrupt ultra-shallow junctions using angled pai and fluorine implant |
US20050051825A1 (en) * | 2003-09-09 | 2005-03-10 | Makoto Fujiwara | Semiconductor device and manufacturing method thereof |
US20050186742A1 (en) * | 2004-02-24 | 2005-08-25 | Chang-Woo Oh | Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same |
US20070026615A1 (en) * | 2005-07-27 | 2007-02-01 | Sinan Goktepeli | Method of forming a FINFET structure |
Also Published As
Publication number | Publication date |
---|---|
GB2455054A (en) | 2009-06-03 |
GB2455054B (en) | 2011-12-07 |
GB0718983D0 (en) | 2007-11-07 |
WO2009040707A2 (en) | 2009-04-02 |
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