WO2009011956A2

WO2009011956A2 - Hybrid magnetoelectronic transistor

Info

Publication number: WO2009011956A2
Application number: PCT/US2008/062212
Authority: WO
Inventors: Jonathan P. Bird; Jong-Uk Bae; Teng-Yin Lin
Original assignee: The Research Foundation Of State University Of New York
Priority date: 2007-05-01
Filing date: 2008-05-01
Publication date: 2009-01-22
Also published as: WO2009011956A3

Abstract

The present invention may be embodied as a device that is realized by forming the gate of a field-effect transistor (FET) from a ferromagnetic material, forming a so-called 'Ferromag-FET.' In addition to its usual electrostatic action, the gate of this device generates FMF that provide an additional means to modulate its conductance. The device may be based on a MOSFET, an HFET, a MESFET, a JFET, or any field-effect transistor. The Ferromag-FET can operate as a traditional transistor, which will allow an easier transition to the use of this new technology within existing products. Due to the nature of the ferromagnetic gate, the Ferromag-FET may also be utilized for non-volatile storage of data.

Description

HYBRID MAGNETOELECTRONIC TRANSISTOR

Cross-Reference to Related Application

[0001] This application claims the benefit of priority to U.S. provisional patent application serial number 60/927,080, filed on May 1, 2007, the disclosure of which is incorporated herein by reference.

[0002] This work was supported by funding from the Government under grant number

DE-FG02-04ER46180 from the Department of Energy. The Government has certain rights in the invention.

Field of the Invention

[0003] The present invention relates generally to semiconductor devices for storage of memory and binary values in addition to traditional switching functions.

Background of the Invention

[0004] Modern electronic devices are based largely on the use of semiconductor field- effect transistors (FETs). The most common FET is the metal oxide semiconductor FET (MOSFET), which is built on a silicon substrate. Integrated circuits utilize thousands or millions of MOSFETs on a single silicon wafer to provide both logic and storage (memory) functions. FETs are also built with other semiconducting materials such as Gallium Arsenide (GaAs). GaAs-based devices offer enhanced performance at the expense of higher manufacturing and material costs.

[0005] The current MOSFET-based integrated circuits (ICs) are built using lithographic processes that have been refined over several decades to produce small devices on a production scale. Transistor components including gate layers, oxide layers and the like are deposited and etched onto wafers grown from single crystals of silicon using masks created by lithography. These techniques have been improved with each generation of fabrication technology so that an integrated circuit can be produced with millions of transistors at an affordable price to the consumer. [0006] The improvements have followed "Moore's law," wherein the number of transistors that may be placed on an IC grows exponentially. This number appears to approximately double every two years and is expected to continue on this pace for the next decade. Intel Corporation's newest Penryn microprocessors contain more than 200 million transistors in a single processing core. These ICs are based on a 45 nm manufacturing process. Approximately 400 transistors built using Intel's 45 nm process could fit on the surface of a single human red blood cell.

[0007] FETs are created to primarily perform logic. Hybrid magneto-electronic devices, combining the functionality of semiconductors and ferromagnets, offer the potential of integrating logic and memory functionalities in a single device, an advance that could allow for the realization of new generations of reprogrammable electronics.

[0008] Dynamic random access memory (DRAM) devices are the most common storage design in use today. Each storage location in a DRAM array includes a capacitor and a transistor. The capacitor has two states, either storing a charge or storing no charge, representing, for example, a binary "1" or "0" value (a bit). By assembling arrays of capacitors, multiple storage locations are created to store binary strings of four (a word) or eight (a byte) bits. Vast two-dimensional arrays are created to store millions of bytes (Megabytes) of binary values representing usable data. However, capacitors which are linked together will lose their charges to each other. Therefore, a transistor is necessary to isolate each capacitor from the array until the capacitor must be accessed, at which time the transistor is switched on.

[0009] Because capacitors also lose their charge over time, the charge must be refreshed periodically to maintain the storage integrity of the DRAM device. This periodic refresh makes the DRAM "volatile" in that when the power to a DRAM device is switched off, the device will lose the stored values. For this reason, when a computer is turned off, the data stored in the computer's random access memory (RAM) is lost and the computer must be "re-booted" from a non-volatile memory source such as a disk drive.

[0010] Attempts have been made in the recent past to use ferromagnetic materials combined with semiconducting materials to provide a non-volatile storage device. One example of such a device is the hybrid Hall sensor, which uses a surface magnet to generate a Hall voltage in a micro-scale junction, and which has been proposed as a universal device for Boolean logic. In this structure, information is represented by the magnetization state of the magnet, while the Hall voltage induced by its fringing magnetic fields (FMF) provides the state readout. However, the multi -terminal structure of the Hall junction is not desirable for integration with transistor-based circuits. See U.S. Pat. No. 6,064,083.

[0011] Some previous devices operate more like a traditional transistor and use ferromagnetic layers as sources, drains, or channels. However, such devices require changes to the lithographic techniques that may be costly to employ. See U.S. Pat. Appl. No. 2007/0201268.

[0012] FETs are also used to provide digital logic gates useful for computation. Several transistors are linked together in configurations which provide Boolean functions such as an AND gate. The simplest AND gate made from transistors requires six transistors and the requisite silicon area. Despite a transistor count in the hundreds of millions in modern ICs, the area required by each logic function is valuable and kept to an absolute minimum.

[0013] Previous devices that incorporate ferromagnetic materials as sources, drains, channels, or "Hall plates" may accomplish logic functions with one transistor or one hybrid Hall sensor rather than many (six in the case of an AND gate). However, as previously discussed, such devices require changes to lithographic techniques to incorporate the additional ferromagnetic layers and/or are not desirable for integration with transistor-based circuits.

[0014] Accordingly, there is a need for a device which has the capability to provide non-volatile storage and/or single-transistor logic functions while operating similar to a traditional FET and requiring only minimal changes in manufacturing processes.

Brief Summary of the Invention

[0015] The present invention may be embodied as a device that is realized by replacing the gate of a field-effect transistor (FET) with a nanoscale magnet, forming a so-called "Ferromag-FET." In addition to its usual electrostatic action, the gate of this device generates FMF that provide an additional means to modulate its conductance. The device may be based on a MOSFET, an HFET, a MESFET, a JFET, or any field-effect transistor. An advantage of this design is over previous ferromagnetic semiconductor devices is that less modification to mass production techniques would be necessary to implement the Ferromag-FET on a large scale. Additionally, the Ferromag-FET can operate as a traditional transistor, which will allow an easier transition to the use of this new technology within existing products.

[0016] Due to the magnetic characteristics of the ferromagnetic gate, the Ferromag-FET may also be utilized for non- volatile storage of data. The invention may also be embodied as a method of storing binary data in an FET or a method of performing logic functions with a single FET.

Description of the Drawings

[0017] For a fuller understanding of the nature and objects of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

Figure 1 is a schematic view of a device in accordance with an embodiment of the present invention; Figure 2 is a schematic view of a device in accordance with another embodiment of the present invention; Figure 3 a is a top view of a device in accordance with another embodiment of the present invention, showing a magnetic domain wall in a first position; Figure 3b is the top view of Figure 3a, showing the magnetic domain wall in a second position; Figure 3c is the top view of a device in accordance with another embodiment of the present invention; Figure 4a is a graph showing conductance of an experimental device according to the invention as a function of gate voltage; Figure 4b is a graph showing the magnetoresistance (MR) of the Cobalt gate of an experimental device according to an embodiment of the invention; Figure 4c is a contour plot showing the MR of an experimental device according to the invention as a function of the external magnetic field and the gate voltage; Figure 5a is a graph showing the calculated MR of a device compared to the actual MR of experiment devices according to the invention; Figure 5b is a graph showing the variation of activation energy of a device according to the invention; Figure 5 c is a contour plot showing the MR of an experimental device according to the invention as a function of the external magnetic field and the gate voltage; Figure 6a is a graph showing the temperature dependence of the MR of a device according to the invention; Figure 6b is a graph showing the conductance as a function of 1 /temperature of a device according to the invention; Figure 6c is a graph showing the MR at a temperature of 4.2 K of a device according to the invention; Figure 6d is a graph showing the MR at a temperature of 77 K of a device according to the invention; Figure 7 is a flow chart showing a method of storing and reading binary values according to another embodiment of the present invention; and Figure 8 is a flowchart showing a method of performing logic functions according to another embodiment of the present invention.

Detailed Description of the Invention

[0018] Figure 1 depicts a device 10 according to the invention which may include a substrate 12, which may be formed from a semiconductor such as silicon. The substrate 12 may be doped with impurities to form, for example, a p-doped region 14. Two n-doped wells, the source 16 and the drain 18, may also be formed in the substrate. Electrodes 20, 22 may be provided in electrical contact with the n-doped wells 16, 18. Electrodes 20, 22 are preferably made from a metal. An insulating layer 24 may be disposed on a region of the substrate 12 between the n-doped wells 16, 18, known as the channel 28. The insulating layer 24 may be, for example, an oxide such as silicon dioxide. A gate 26 may be disposed on the insulating layer 24. In a previous MOSFET device, the gate 26 is made from a metal similar to the electrical contacts 20, 22. In a device 10 according to the current invention, the gate 26 is made from a ferromagnetic material such as Cobalt or Permalloy (Py) (NiSiF₁₉). A MOSFET may alternatively be formed with p-doped source 16 and drain 18 wells in an n-doped substrate 12. As shown in Figure 3c, the device 70 may have more than one gate element 72, 74 which may be arranged along the channel.

[0019] The operation of the Ferromag-FET device 10 is as follows. When a voltage is applied between the source 16 and the drain 18, a current flows between the source 16 and the drain 18 through the channel 28. If at this time a voltage is applied to the gate 26, the conductance of the channel can be changed by the field effect. Accordingly, the source-drain current can be controlled. Separately or simultaneously, the conductance of the channel 28, and therefore the source-drain current, can also be changed by FMF created by a magnetic field 30 in the gate 26. FMF modify the conductance of the channel 28 when they emanate from the gate 26 into the channel 28. For example, FMF may impede the conductance of the channel 28 when the magnetic field 30 of the gate 26 is oriented in the plane of the channel 28 along the x-axis as shown in Figure 1. The simplicity of replacing the gate of a FET with a gate comprising a ferromagnetic material allows the current invention to be embodied by replacing the gate of any FET-based device. For example, the device may be a MOSFET, a MESFET, an HFET, or a JFET.

[0020] The magnetic field 30 of the gate 26 may be modified by an external magnetic field Bext- As shown in Figure 2, the gate 32 may have electrical contacts 34, 36 at each end such that a current may be applied through the gate 32 to modify the magnetic field. An applied current can be configured to generate a magnetic field, or to modify the magnetic field in a ferromagnetic material.

[0021] In another embodiment 40 shown in Figures 3a and 3b, the gate 42 may contain more than one magnetic orientation 44, 46 separated by at least one domain wall 48. In such an embodiment, the gate 42 would typically be a nanowire, meaning that the gate 42 is of sufficiently small cross-sectional area so as to permit the formation of single domain walls. In this way, the gate 42 may contain differing magnetic domains wherein a first domain 44 may be of an orientation which attenuates the channel conductance and another domain 46 may be of an orientation which does not attenuate the channel conductance. By applying a pulse of current 50 to the gate 42, each domain 44, 46 may selectively be moved into the region of the gate 42 which is disposed directly over the channel 52 as seen from the z direction. The gate 42 may also contain pinning sites 54, 56, for example, notches etched into the gate 42 or modulating the size of the gate 42, which allow more control over the spacing and location of the domain wall(s) 48. See, Stuart S. P. Parkin, Masamitsu Hayashi, Luc Thomas, Magnetic Domain-Wall Racetrack Memory, Science 320, 5873 (2008).

[0022] In another embodiment, the Ferromag-FET may be implemented in the high- mobility two-dimensional electron gas (2DEG) of a GaAs/AlGaAs heterostructure. Figure 2 depicts a device 60 in accordance with this embodiment. Using optical lithography and wet etching, a quantum wire 38 may be formed in the 2DEG of a GaAs/AlGaAs quantum well. The quantum wire 38 may be, for example, 2.3 μm wide and 26 μm. long, creating an electron density, mobility, and mean free path in the wire of 2.8 x IO¹¹ cm^"2, 4.5 x 10⁵ cm², and 3.8 μm, respectively (at 4.2 K), yielding a Fermi energy of 10 meV. Electron-beam lithography may then be used to define a thin Co gate 32, which may be, for example, 20 run thick and 500 nm wide, disposed across the middle portion of the quantum wire 38. The ends 35, 37 of the gate 32 may be connected to electrical contacts 34, 36.

[0023] On entering the pinch-off regime, there is a pronounced enhancement of the

FMF-induced magneto-resistance (MR). Analysis shows that the large (approaching 20%) MR in this regime results from the ability of the FMF to cause a small modulation of the potential barrier, generated in the FET channel by the electrostatic action of the gate 32. The strong sensitivity of the channel current to even small barrier modulations in the pinch-off regime leads to the large MR. The Ferromag-FET is therefore useful as a hybrid magneto-electronic device, whose transistor-like structure should make it amenable to integration in conventional circuits.

[0024] Recent proposals for spin devices, which aim to use challenging manipulation of spin-orbit coupling are reviewed in I. Zutic, J. Fabian, and S. Das Sarma, Rev. Mod. Phys. 76, 323 (2004). While not intending to be bound by any particular theory, it is considered that unlike these devices, the Ferromag-FET relies primarily on the coupling of the FMF to the orbital motion of its carriers. Physically, the normal component of the FMF converts some of the carrier kinetic energy into cyclotron energy, and so should modify the transmission probability through the gate-induced barrier, particularly in the pinch-off regime where current involves either tunneling or barrier activation. This sensitivity leads to a large, hysteretic, MR in the Ferromag-FET, which allows these devices to be used to implement integrated logic and non- volatile memory functionalities.

[0025] The invention may be embodied as a method of non-volatile storage, Figure 7, by utilizing the magnetic properties of the gate to store a binary value — a "0" or a "1." A Ferromag- FET device, as described above, is provided 100. A selected magnetic field orientation is induced 110 in the gate of the Ferromag-FET. The field orientation is selected from either a channel-attenuating orientation or a non-channel-attenuating orientation, representing either a binary "0" or a binary "1." Once a value is stored, the value may also be read from non-volatile storage by applying a voltage to the gate thereby inducing 120 an electrostatic field in the channel. The source-drain current flow through the channel may then be detected to determine 130 the attenuation state of the channel (attenuated or not). The channel state will relate to a magnetic field orientation (previously assigned a binary value) which can now be determined 140 which will now be known.

[0026] The invention may also be embodied as a method of providing an integrated logic function, Figure 8. In a simple example, a Ferromag-FET device, as described above, is provided 200. A first binary value may be stored in the magnetic gate by inducing 210 a selected magnetic field orientation in the gate of the Ferromag-FET. A voltage may be applied to the gate to induce 220 an electrostatic field, wherein the voltage, or lack thereof, represents a second binary value. A third binary value may be obtained 230 by a current flow between the source and the drain resulting from the combined effect of the magnetic field representing the first binary value and the electrostatic field representing the second binary value.

[0027] The invention is further described through Example 1 that is included to illustrate the invention and are not intended to be restrictive.

Example 1

[0028] In this example, two devices (device 1 & 2) were constructed according to the invention depicted in Figure 2. Magnetic fields were induced in the gate 32 by way of external magnetic fields B_ext. Magnetic fields may be induced and oriented in the gate 32 by other methods such as inducing a current through the gate 32.

[0029] In Figure 4a, the variation of the conductance (G) of device 60 is shown 300 as a function of gate voltage (V_g) at zero external magnetic field (B_ext = 0). The gate voltage raises the 2DEG conduction-band edge in the region close to the gate, forming a potential barrier that eventually rises above the Fermi level. This pinch off corresponds to the vanishing of the conductance in Figure 4a, and can be simulated by assuming that the gate voltage induces a parabolic potential barrier at the channel center:

[0030] V(x,y) = V₀ - ¹Am^* cm\² + 'Am ωfy², ( 1 )

[0031] where CU_X^ are oscillator frequencies, V₀ is the minimum barrier height, m is the carrier mass, and current in the wire flows along the x-direction (see schematic of Figure 2 for coordinate axis). For the parabolic saddle potential of Eq. (1), the transmission probability of the different one-dimensional subbands:

[0032] T_n(E) = (I + exp(-^))-¹, n = 0, 1, 2, ... (1)

[0033] In this expression, which is valid at B_ext = 0, E is the carrier energy, ε_n = (E - E_y(n

+ ¹A) - V₀)IE_x, E_x = YZHU)_X, E_y = ¹APiCO_y, and n is the subband index. For ballistic transmission, the conductance G = T ≡∑ _n T_n (in units of 2e²/h). In Figure 4a, a calculated conductance curve 410 obtained by varying Vo while keeping the barrier shape (cθχ_>y) fixed is shown. Although this approximation is not completely realistic, and in spite of quantitative differences, the calculation reproduces the basic behavior of experiment. To obtain such agreement, it is noted the physical width of the FET gate places a constraint on ω_x, while a constraint on ω_y follows from the fact that the experimental conductance data do not show the quantized conductance (in steps of 2e²/h) typical of quasi-one-dimensional channels (i.e. hω_y < k^ T). This can be ascribed to the weak confinement generated in the test devices, which have etched widths larger than 2 microns.

[0034] In J.-U. Bae, T.-Y. Lin, Y. Yoon, S. J. Kim, J. P. Bird, A. Imre, W. Porod, and J.

L. Reno, Appl. Phys. Lett. 91, 022105 (2007), it was shown that, with no electrostatic barrier (V₈ = 0), the Ferromag-FET resistance shows a minimum whenever B_ext is equal to the coercive field of the gate. For this condition, the FMF vanish and the associated suppression of scattering reduces the channel resistance. In Figures 4c and 5c, the MR of the devices is shown as a function of B_ext & V_g. In these contour plots, ΔR is the hysteretic difference in resistance obtained while sweeping B_ext in opposite directions and R_m the minimum resistance obtained during the sweeps. Within the experimental uncertainty of -1°, B_ext is applied in the plane of the 2DEG, being directed along the x-axis and so perpendicular to the gate axis. The variations in the contours therefore arise predominantly from the FMF. In both contours, a pair of peaks 350, 360 can be seen at B_ext ~ ±50 mT (note the different conductance scales), with each peak associated with a given sweep direction (see Figures 6c and 6d). In Figure 4b, the MR of the Co gate of Device 2 is plotted and it can be seen that this shows two peaks clearly correlated to those in the Ferromag-FET MR. The peaks in Rc₀ denote the coercive field of the gate, where the FMF vanish. Consistent with this, the MR peaks in Figure 4b occur at the same values of B_ext as in the contours in Figures 4c and 5c.

[0035] The panels of Figures 4c and 5c indicate a growth of the Ferromag-FET MR as pinch-off is approached (this effect is more pronounced in the contour of Figure 5c, only since this covers a wider range of G). In Figure 6a, we show that this onsets once the channel conductance (G ≡ 1/R) drops below 2e²/h, corresponding to the onset of tunneling. While the magnitude of the hysteretic MR is a few percent for G > 2e²/h, in the tunneling regime it grows to approach 20%. Over the range of G for which we have data for both devices, their values overlap very closely, indicating that this growth of the MR is indeed a generic effect. To provide an analysis of this effect, we note that Eq. (2) can be formally modified to determine the conductance in the presence of a uniform magnetic field. Since the FMF generated by the gate are highly non-uniform, however, we adopt a different approach to this problem. Namely, we express the saddle minimum as V_B ≡ V₀ + ΔV_B, where V₀ is the electrostatic component due to V_g and ΔV_B is the modulation induced by the FMF. The solid line 400 in Figure 5 a plots the MR expected from this model, where ΔT ≡ T(V₀) - T(V_B) and T_B ≡ T(V_B). The match with experiment is by no means perfect, and improving this will likely require the development of a more sophisticated model, which accounts fully for the self-consistent evolution of the FET barrier with V_g, and the spatially-inhomogeneous FMF generated by the gate. In spite of these issues, the curve 410 in Figure 2 does capture the key trend for the MR to increase in the tunneling regime. The curve was obtained for ΔV_B = 0.06 meV, and saturates at a value close to the maximum MR seen in experiment. For G < 10^"3, the experimental MR shows a sudden drop not reproduced in the calculations. This likely occurs once the depletion region generated by the electrostatic action of the gate 32 exceeds the spatial range of the FMF, so that a further variation of V_g reduces the average amplitude (B_f) of the FMF.

[0036] Figure 6a shows the temperature (T) dependence of the MR for a V_g for which the hysteresis is maximal. The MR weakens with increasing T, but still persists at 77 K where ΔR/R_m <1% (Figure 6d). Figure 6b plots G as a function of 1/T at the two coercive fields and shows activated behavior, G ∞ exp(-E_A/kβT), consistent with thermal activation over the FET barrier. Since the activation energy (E_A) should correspond to V_B, in Figure 5b we plot the variation of E_A(B_ext) obtained from the data of Figure 6a. Note how E_A is modulated by B_ext, and shows hysteresis consistent with that of the gate. The barrier height is minimal at the coercive- field points (±50 mT, no FMF) but increases as B_ext is increased away from these points. From Figure 5b we determine the electrostatically-induced potential barrier (V₀ = -1.88 meV), and a modulation of the barrier (ΔV_B = ~0.06 meV) that is in good agreement with our calculations. This small (3%) modulation yields a large (20%) change in conductance, which can be attributed to the strong sensitivity of electron transmission to the fringing fields in the tunneling (or thermally-activated) regime.

[0037] The bistable output of the Ferromag-FET may allow the realization of a universal reprogrammable device, capable of logic and non- volatile memory. This could be achieved by encoding information in the magnetization state of the gate, similar to proposals for the hybrid Hall device shown in U.S. Pat. No. 6,064,083, incorporated herein by reference, and reading it out via the FET conductance. Similar to that device, the Ferromag-FET could also be reprogrammed in a single clock cycle, by applying suitable current pulses to its gate.

[0038] Although the present invention has been described with respect to one or more particular embodiments, it will be understood that other embodiments of the present invention may be made without departing from the spirit and scope of the present invention. Hence, the present invention is deemed limited only by the appended claims and the reasonable interpretation thereof.

Claims

What is claimed is:

1. A field-effect transistor comprising: a source; a drain; a channel having a variable conductance, wherein the channel adjoins the source and the drain and acts as a current pathway therebetween; and a gate disposed on the channel, wherein the gate is made of a ferromagnetic material having magnetic properties and electrostatic properties, and the magnetic properties and/or the electrostatic properties of the gate material modulate the conductance of the channel.

2. The field-effect transistor of claim 1, wherein the field-effect transistor is selected from the group consisting of a MOSFET, an HFET, a MESFET, and a JFET.

3. The field-effect transistor of claim 2, wherein the field-effect transistor is an n-type MOSFET.

4. The field-effect transistor of claim 3, wherein the field-effect transistor is a p-type MOSFET.

5. The field-effect transistor of claim 1, wherein the ferromagnetic material is selected from the group consisting of cobalt and permalloy.

6. The field-effect transistor of claim 1, wherein the channel is less than approximately 3 μm in width.

7. The field-effect transistor of claim 1, wherein the channel is less than approximately 100 nm in width.

8. The field-effect transistor of claim 1, wherein the gate is less than approximately 100 nm in width.

9. The field-effect transistor of claim 1, wherein the gate is a nanowire having a first end, and a second end.

10. The field-effect transistor of claim 9, wherein the nanowire gate is connected at the first end to a first electrical contact, and at the second end to a second electrical contact.

11. The field-effect transistor of claim 10, wherein an electrical current is applied from the first electrical contact, through the nanowire, to the second end, and the electrical current induces an magnetic field of a first orientation in the gate.

12. The field-effect transistor of claim 10, wherein the nanowire gate contains a magnetic domain wall separating at least two magnetic domains, wherein each of the at least two magnetic domains modulate the channel conductance to represent different binary values.

13. The field-effect transistor of claim 12, wherein the nanowire gate contains at least two pinning sites.

14. The field-effect transistor of claim 13, wherein the domain wall is moved from a first pinning site to a second pinning site by applying a pulse of spin-polarized current to the nanowire gate and moving the domain wall will cause another of the at least two magnetic domains to effect the channel conductance.

15. The field-effect transistor of claim 1, wherein the gate includes at least two gate elements.

16. A method of storing a binary value in a hybrid field-effect transistor comprising the steps of: providing a field-effect transistor comprising: a source; a drain; a channel having a variable conductance, wherein the channel adjoins the source and the drain and acts as a current pathway therebetween; a gate disposed on the channel, wherein the gate is made of a ferromagnetic material having magnetic properties and electrostatic properties, and the magnetic properties and/or the electrostatic properties of the gate material modulate the conductance of the channel; and inducing a magnetic field of a selected orientation in the gate.

17. The method of claim 16, wherein the magnetic field is induced in the gate by applying a current through the gate.

18. The method of claim 16, wherein the gate is a nanowire, and the magnetic field is induced in the gate by applying a pulse of current to the nanowire gate.

19. The method of claim 16, further comprising the step of reading the stored binary value, including: inducing an electrostatic field in the gate; determining a channel state by detecting a current flow between the source and the drain; determining the orientation of the magnetic field of gate by the channel state.

20. A method for performing Boolean functions using a single transistor comprising the steps of: providing a field-effect transistor comprising: a source; a drain; a channel having a variable conductance, wherein the channel adjoins the source and the drain and acts as a current pathway therebetween; a gate disposed on the channel, wherein the gate is made of a ferromagnetic material having magnetic properties and electrostatic properties, and the magnetic properties and/or the electrostatic properties of the gate material modulate the conductance of the channel; inducing a magnetic field in the gate oriented to represent a first binary value; inducing an electrostatic field in the gate to represent a second binary value, the second binary value being the same as or different than the first binary value; obtaining a resulting current flow between the source and the drain representing a third binary value determined by a combined effect of the magnetic field representing the first binary value and the electrostatic field representing the second binary value.