WO2008008630A3 - Highly dense monolithic three dimensional memory array and method for forming - Google Patents

Highly dense monolithic three dimensional memory array and method for forming Download PDF

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Publication number
WO2008008630A3
WO2008008630A3 PCT/US2007/072301 US2007072301W WO2008008630A3 WO 2008008630 A3 WO2008008630 A3 WO 2008008630A3 US 2007072301 W US2007072301 W US 2007072301W WO 2008008630 A3 WO2008008630 A3 WO 2008008630A3
Authority
WO
WIPO (PCT)
Prior art keywords
forming
memory array
highly dense
dimensional memory
dense monolithic
Prior art date
Application number
PCT/US2007/072301
Other languages
French (fr)
Other versions
WO2008008630A2 (en
Inventor
Jack Yuan
George Samachisa
Original Assignee
Sandisk 3D Llc
Jack Yuan
George Samachisa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk 3D Llc, Jack Yuan, George Samachisa filed Critical Sandisk 3D Llc
Publication of WO2008008630A2 publication Critical patent/WO2008008630A2/en
Publication of WO2008008630A3 publication Critical patent/WO2008008630A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A method to form a highly dense monolithic three dimensional memory array is provided. In preferred embodiments, conductive or semiconductor spacers (116) can be formed, then used as hard masks to pattern underlying layer in a self -aligned manner, forming features at sublithographic pitch. Methods of the invention minimize photomasking steps and thus simplify fabrication. The method is used for forming crosspoint memory arrays comprising fuses, antif uses or chalcogenide switching elements. Several memory layers are stacked one on top of the other.
PCT/US2007/072301 2006-06-30 2007-06-28 Highly dense monolithic three dimensional memory array and method for forming WO2008008630A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/479,697 2006-06-30
US11/479,697 US20080017890A1 (en) 2006-06-30 2006-06-30 Highly dense monolithic three dimensional memory array and method for forming

Publications (2)

Publication Number Publication Date
WO2008008630A2 WO2008008630A2 (en) 2008-01-17
WO2008008630A3 true WO2008008630A3 (en) 2008-04-03

Family

ID=38924012

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/072301 WO2008008630A2 (en) 2006-06-30 2007-06-28 Highly dense monolithic three dimensional memory array and method for forming

Country Status (3)

Country Link
US (1) US20080017890A1 (en)
TW (1) TW200816395A (en)
WO (1) WO2008008630A2 (en)

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US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7629247B2 (en) * 2007-04-12 2009-12-08 Sandisk 3D Llc Method of fabricating a self-aligning damascene memory structure
JP2009267219A (en) * 2008-04-28 2009-11-12 Hitachi Ltd Semiconductor memory device and manufacturing method thereof
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US7732235B2 (en) * 2008-06-30 2010-06-08 Sandisk 3D Llc Method for fabricating high density pillar structures by double patterning using positive photoresist
WO2010019789A1 (en) * 2008-08-13 2010-02-18 Sandisk 3D, Llc Methods and apparatus for increasing memory density using diode layer sharing
WO2010019794A1 (en) * 2008-08-13 2010-02-18 Sandisk 3D, Llc Integration methods for carbon films in two-and three-dimensional memories and memories formed therefrom
US8921196B2 (en) * 2008-12-30 2014-12-30 Micron Technology, Inc. Double patterning method for creating a regular array of pillars with dual shallow trench isolation
TW201126572A (en) * 2009-10-26 2011-08-01 Sandisk 3D Llc Methods of forming pillars for memory cells using sequential sidewall patterning

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US6034882A (en) * 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
EP1355356A2 (en) * 2002-04-18 2003-10-22 Sony Corporation Memory device and method of production and method of use of same and semiconductor device and method of production of same
US20060054991A1 (en) * 2004-09-10 2006-03-16 Kuo Charles C Forming phase change memory arrays
US20060110877A1 (en) * 2004-11-10 2006-05-25 Park Yoon-Dong Memory device including resistance change layer as storage node and method(s) for making the same
US20060124916A1 (en) * 2004-12-09 2006-06-15 Macronix International Co., Ltd. Self-aligned small contact phase-change memory method and device

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US6420215B1 (en) * 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
KR100821456B1 (en) * 2000-08-14 2008-04-11 샌디스크 쓰리디 엘엘씨 Dense arrays and charge storage devices, and methods for making same
US6952043B2 (en) * 2002-06-27 2005-10-04 Matrix Semiconductor, Inc. Electrically isolated pillars in active devices
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
JP2006511965A (en) * 2002-12-19 2006-04-06 マトリックス セミコンダクター インコーポレイテッド Improved method for fabricating high density non-volatile memory
US8637366B2 (en) * 2002-12-19 2014-01-28 Sandisk 3D Llc Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
US20060250836A1 (en) * 2005-05-09 2006-11-09 Matrix Semiconductor, Inc. Rewriteable memory cell comprising a diode and a resistance-switching material

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034882A (en) * 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
EP1355356A2 (en) * 2002-04-18 2003-10-22 Sony Corporation Memory device and method of production and method of use of same and semiconductor device and method of production of same
US20060054991A1 (en) * 2004-09-10 2006-03-16 Kuo Charles C Forming phase change memory arrays
US20060110877A1 (en) * 2004-11-10 2006-05-25 Park Yoon-Dong Memory device including resistance change layer as storage node and method(s) for making the same
US20060124916A1 (en) * 2004-12-09 2006-06-15 Macronix International Co., Ltd. Self-aligned small contact phase-change memory method and device

Also Published As

Publication number Publication date
WO2008008630A2 (en) 2008-01-17
US20080017890A1 (en) 2008-01-24
TW200816395A (en) 2008-04-01

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