WO2008005892A3 - Nanocrystal formation - Google Patents

Nanocrystal formation Download PDF

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Publication number
WO2008005892A3
WO2008005892A3 PCT/US2007/072577 US2007072577W WO2008005892A3 WO 2008005892 A3 WO2008005892 A3 WO 2008005892A3 US 2007072577 W US2007072577 W US 2007072577W WO 2008005892 A3 WO2008005892 A3 WO 2008005892A3
Authority
WO
WIPO (PCT)
Prior art keywords
forming
layer
substrate
metallic nanocrystalline
metallic
Prior art date
Application number
PCT/US2007/072577
Other languages
French (fr)
Other versions
WO2008005892A2 (en
Inventor
Nety M Krishna
Ralf Hofmann
Kaushal K Singh
Karl J Armstrong
Original Assignee
Applied Materials Inc
Nety M Krishna
Ralf Hofmann
Kaushal K Singh
Karl J Armstrong
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc, Nety M Krishna, Ralf Hofmann, Kaushal K Singh, Karl J Armstrong filed Critical Applied Materials Inc
Priority to CN2007800246033A priority Critical patent/CN101479834B/en
Priority to JP2009518595A priority patent/JP5558815B2/en
Priority to EP07812513A priority patent/EP2047502A4/en
Publication of WO2008005892A2 publication Critical patent/WO2008005892A2/en
Publication of WO2008005892A3 publication Critical patent/WO2008005892A3/en

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Abstract

In one embodiment, a method for forming a metallic nanocrystalline material on a substrate is provided which includes exposing a substrate to a pretreatment process, forming a tunnel dielectric layer on the substrate, exposing the substrate to a post-treatment process, forming a metallic nanocrystalline layer on the tunnel dielectric layer, and forming a dielectric capping layer on the metallic nanocrystalline layer. The method further provides forming the metallic nanocrystalline layer having a nanocrystalline density of at least about 5×1012 cm-2, preferably, at least about 8×1012 cm-2. In one example, the metallic nanocrystalline layer contains platinum, ruthenium, or nickel. In another embodiment, a method for forming a multi-layered metallic nanocrystalline material on a substrate is provided which includes forming a plurality of bi-layers, wherein each bi-layer contains an intermediate dielectric layer deposited on a metallic nanocrystalline layer. Some of the examples include 10, 50, 100, 200, or more bi-layers.
PCT/US2007/072577 2006-06-30 2007-06-29 Nanocrystal formation WO2008005892A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2007800246033A CN101479834B (en) 2006-06-30 2007-06-29 Nanocrystal formation
JP2009518595A JP5558815B2 (en) 2006-06-30 2007-06-29 Nanocrystal formation
EP07812513A EP2047502A4 (en) 2006-06-30 2007-06-29 Nanocrystal formation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80644606P 2006-06-30 2006-06-30
US60/806,446 2006-06-30

Publications (2)

Publication Number Publication Date
WO2008005892A2 WO2008005892A2 (en) 2008-01-10
WO2008005892A3 true WO2008005892A3 (en) 2008-12-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/072577 WO2008005892A2 (en) 2006-06-30 2007-06-29 Nanocrystal formation

Country Status (7)

Country Link
US (1) US20080135914A1 (en)
EP (1) EP2047502A4 (en)
JP (1) JP5558815B2 (en)
KR (1) KR101019875B1 (en)
CN (1) CN101479834B (en)
TW (1) TWI395335B (en)
WO (1) WO2008005892A2 (en)

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EP2047502A2 (en) 2009-04-15
CN101479834A (en) 2009-07-08
JP2009543359A (en) 2009-12-03
WO2008005892A2 (en) 2008-01-10
EP2047502A4 (en) 2009-12-30
KR20090026352A (en) 2009-03-12
TWI395335B (en) 2013-05-01
JP5558815B2 (en) 2014-07-23
CN101479834B (en) 2011-06-08
TW200812091A (en) 2008-03-01
KR101019875B1 (en) 2011-03-04

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