WO2007038575A3 - Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby - Google Patents

Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby Download PDF

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Publication number
WO2007038575A3
WO2007038575A3 PCT/US2006/037634 US2006037634W WO2007038575A3 WO 2007038575 A3 WO2007038575 A3 WO 2007038575A3 US 2006037634 W US2006037634 W US 2006037634W WO 2007038575 A3 WO2007038575 A3 WO 2007038575A3
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Prior art keywords
planar
integrating
article made
bulk substrate
cmos transistors
Prior art date
Application number
PCT/US2006/037634
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French (fr)
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WO2007038575A2 (en
Inventor
Jack Kavalieros
Justin Brask
Brian Doyle
Uday Shah
Suman Datta
Mark Doczy
Matthew Metz
Robert Chau
Original Assignee
Intel Corp
Jack Kavalieros
Justin Brask
Brian Doyle
Uday Shah
Suman Datta
Mark Doczy
Matthew Metz
Robert Chau
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Application filed by Intel Corp, Jack Kavalieros, Justin Brask, Brian Doyle, Uday Shah, Suman Datta, Mark Doczy, Matthew Metz, Robert Chau filed Critical Intel Corp
Priority to CN2006800355214A priority Critical patent/CN101292346B/en
Priority to EP06815547A priority patent/EP1929516A2/en
Priority to KR1020087007431A priority patent/KR101095188B1/en
Publication of WO2007038575A2 publication Critical patent/WO2007038575A2/en
Publication of WO2007038575A3 publication Critical patent/WO2007038575A3/en

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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7851Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

A process capable of integrating both planar (10) and non-planar (20, 30) transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
PCT/US2006/037634 2005-09-28 2006-09-26 Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby WO2007038575A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2006800355214A CN101292346B (en) 2005-09-28 2006-09-26 Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby
EP06815547A EP1929516A2 (en) 2005-09-28 2006-09-26 Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby
KR1020087007431A KR101095188B1 (en) 2005-09-28 2006-09-26 Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/238,444 US7479421B2 (en) 2005-09-28 2005-09-28 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US11/238,444 2005-09-28

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WO2007038575A2 WO2007038575A2 (en) 2007-04-05
WO2007038575A3 true WO2007038575A3 (en) 2007-07-19

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US (2) US7479421B2 (en)
EP (1) EP1929516A2 (en)
KR (1) KR101095188B1 (en)
CN (1) CN101292346B (en)
TW (1) TWI321830B (en)
WO (1) WO2007038575A2 (en)

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