WO2006083546A3 - In situ formed halo region in a transistor device - Google Patents

In situ formed halo region in a transistor device Download PDF

Info

Publication number
WO2006083546A3
WO2006083546A3 PCT/US2006/001596 US2006001596W WO2006083546A3 WO 2006083546 A3 WO2006083546 A3 WO 2006083546A3 US 2006001596 W US2006001596 W US 2006001596W WO 2006083546 A3 WO2006083546 A3 WO 2006083546A3
Authority
WO
WIPO (PCT)
Prior art keywords
epitaxial growth
region
halo region
semiconductor region
transistor device
Prior art date
Application number
PCT/US2006/001596
Other languages
French (fr)
Other versions
WO2006083546A2 (en
Inventor
Thorsten Kammler
Andy Wei
Helmut Bierstedt
Original Assignee
Advanced Micro Devices Inc
Thorsten Kammler
Andy Wei
Helmut Bierstedt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102005004411A external-priority patent/DE102005004411B4/en
Application filed by Advanced Micro Devices Inc, Thorsten Kammler, Andy Wei, Helmut Bierstedt filed Critical Advanced Micro Devices Inc
Publication of WO2006083546A2 publication Critical patent/WO2006083546A2/en
Publication of WO2006083546A3 publication Critical patent/WO2006083546A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

By performing a sequence of selective epitaxial growth processes with at least two different species, or by introducing a first dopant species prior to the epitaxial growth of a drain and source region, a halo region may be formed in a highly efficient manner, while at the same time the degree of lattice damage in the epitaxially grown semiconductor region is maintained at a low level. The method of forming a first semiconductor region (211) by a first epitaxial growth process, forming a second semiconductor region (210) by performing a second epitaxial growth process, whereas the first and second semiconductor regions compose different dopant species.
PCT/US2006/001596 2005-01-31 2006-01-17 In situ formed halo region in a transistor device WO2006083546A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102005004411.5 2005-01-31
DE102005004411A DE102005004411B4 (en) 2005-01-31 2005-01-31 A method of fabricating an in-situ formed halo region in a transistor element
US11/203,848 2005-08-15
US11/203,848 US20060172511A1 (en) 2005-01-31 2005-08-15 In situ formed halo region in a transistor device

Publications (2)

Publication Number Publication Date
WO2006083546A2 WO2006083546A2 (en) 2006-08-10
WO2006083546A3 true WO2006083546A3 (en) 2006-12-14

Family

ID=36260351

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/001596 WO2006083546A2 (en) 2005-01-31 2006-01-17 In situ formed halo region in a transistor device

Country Status (1)

Country Link
WO (1) WO2006083546A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7534689B2 (en) * 2006-11-21 2009-05-19 Advanced Micro Devices, Inc. Stress enhanced MOS transistor and methods for its fabrication
US7687337B2 (en) * 2007-07-18 2010-03-30 Freescale Semiconductor, Inc. Transistor with differently doped strained current electrode region
KR102261642B1 (en) 2014-08-07 2021-06-08 삼성디스플레이 주식회사 Thin film transistor and method for manufacturing of the same
CN105742187A (en) * 2016-05-13 2016-07-06 上海华力微电子有限公司 Method for inhibiting short-channel effect of PMOSFET device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
US6274894B1 (en) * 1999-08-17 2001-08-14 Advanced Micro Devices, Inc. Low-bandgap source and drain formation for short-channel MOS transistors
US6372583B1 (en) * 2000-02-09 2002-04-16 Intel Corporation Process for making semiconductor device with epitaxially grown source and drain
US6787852B1 (en) * 2001-02-06 2004-09-07 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions
US20050012146A1 (en) * 1998-11-12 2005-01-20 Murthy Anand S. Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
US20050012146A1 (en) * 1998-11-12 2005-01-20 Murthy Anand S. Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US6274894B1 (en) * 1999-08-17 2001-08-14 Advanced Micro Devices, Inc. Low-bandgap source and drain formation for short-channel MOS transistors
US6372583B1 (en) * 2000-02-09 2002-04-16 Intel Corporation Process for making semiconductor device with epitaxially grown source and drain
US6787852B1 (en) * 2001-02-06 2004-09-07 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions

Also Published As

Publication number Publication date
WO2006083546A2 (en) 2006-08-10

Similar Documents

Publication Publication Date Title
TW200631104A (en) In situ formed halo region in a transistor device
TW200723563A (en) Nitride semiconductor element and method for growing nitride semiconductor crystal layer
TW200603294A (en) Method of making transistor with strained source/drain
TW200618076A (en) Low temperature selective epitaxial growth of silicon germanium layers
WO2006088766A3 (en) Highly conductive shallow junction formation
TW200506117A (en) Semi-insulating GaN and method of making the same
SG138528A1 (en) Mosfets comprising source/drain regions with slanted upper surfaces, and method for fabricating the same
GB2442689A (en) Methods for fabricating a stressed MOS device
WO2008094653A3 (en) Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss
EP1693897A3 (en) Semiconductor device
SG144827A1 (en) Method of forming source and drain of field-effect-transistor and structure thereof
JP2011530167A5 (en)
TW200520106A (en) Technique for forming transistors having raised drain and source regions with different heights
WO2007078957A3 (en) Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers
ATE535010T1 (en) METHOD FOR PRODUCING SELF-ALIGNED TRANSISTOR TOPOLOGIES IN SILICON CARBIDE BY USING SELECTIVE EPITAXY
WO2006039038A3 (en) Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
EP1777737A4 (en) High-electron-mobility transistor, field-effect transistor, epitaxial substrate, method for manufacturing epitaxial substrate, and method for manufacturing group iii nitride transistor
WO2007065018A3 (en) Doped aluminum nitride crystals and methods of making them
TW200633022A (en) Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device
US20160005657A1 (en) Semiconductor structure with increased space and volume between shaped epitaxial structures
TW201712873A (en) High electron mobility transistors with localized sub-fin isolation
US10134900B2 (en) SiGe source/drain structure and preparation method thereof
EP2119815A4 (en) Method for producing self-supporting nitride semiconductor substrate and self-supporting nitride semiconductor substrate
EP1703550A4 (en) Vapor growth device and production method for epitaxial wafer
US20090242989A1 (en) Complementary metal-oxide-semiconductor device with embedded stressor

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06718646

Country of ref document: EP

Kind code of ref document: A2