WO2006070154A1

WO2006070154A1 - Improved semiconductor thin-film transistor structure

Info

Publication number: WO2006070154A1
Application number: PCT/FR2005/051119
Authority: WO
Inventors: Thomas Ernst; Olivier Weber
Original assignee: Commissariat A L'energie Atomique; Centre National De La Recherche Scientifique
Priority date: 2004-12-24
Filing date: 2005-12-20
Publication date: 2006-07-06
Also published as: FR2880190A1; FR2880190B1

Abstract

The invention concerns a microelectronic device comprising: a substrate (100) coated with at least one first semiconductor film based on a first semiconductor material (108) wherein is formed at least one channel (110) of a transistor (T1) and whereon is mounted at least one grid (130) of said transistor (T1); at least one first block (113) and at least one second block (114) made of a second semiconductor material (112), mounted on the first semiconductor film, formed on either side of the grid (130), the first block (113) and the second block (114) being respectively provided with at least one first inclined flank (115) opposite the grid and with at least one second inclined flank (116) opposite the grid, the inclined flanks forming a non-null angle with a normal (n) to the main plane of the substrate (100).

Description

IMPROVED STRUCTURE OF TRANSISTOR STJR THIN FILM

SEMI-CONDUCTEtJR

DESCRIPTION

TECHNICAL FIELD AND PRIOR ART

The invention relates to a microelectronic device and in particular to an improved transistor structure, for example in CMOS technology

(CMOS for Complementary Metal-oxide Semiconductor or Complementary Metal Oxide Semiconductor), in which sloping-edge semiconductor blocks capable of serving as a source region or a drain region are separated by an opening at enlarged mouth in which is made a grid. These blocks are based on a thin semiconductor layer, for example the upper layer of a semiconductor-on-insulator type substrate, in which a channel is formed at the bottom of said opening. The invention can be applied to the formation of improved transistors in terms of consumption and speed. It can notably enable the formation of gate-type transistors and access resistors between source and channel and / or between improved drain and channel, as well as the formation of thin-film semiconductor film transistors of very small dimension.

The invention also relates to a method for producing such a microelectronic device. In order to improve the performance of the transistors, and in particular MOS or CMOS transistors, it is known to form them on a thin or ultrathin semiconductor film, for example of thickness less than 20 nanometers or less than 10 nanometers , in particular to obtain improved electrostatic control of the conduction channel by the gate, and to reduce the so-called "short channel" effects. A disadvantage related to the formation of thin or ultrathin semiconductor film transistors, in particular on insulators, is that these transistors generally comprise, in particular in a region located under the spacers ("spacers" according to the English terminology "). , an access resistance between the channel and the source region or between the relatively high drain region and the channel.

The document "Double Raised Source / Drain transistor with 50 nm gat length on 17 nm UTF-SOI for 1.1 μm ² embedded SRAM technology, CB Oh, IEDM 2003, p 31-34" proposes a semiconductor film transistor structure. thin conductor, with an improvement, vis-à-vis the access resistance problem mentioned above.

Such a transistor structure is illustrated in FIG. 1 and comprises, first of all, a substrate 2 of SOI type (SOI for "silicon on insulator" or "silicon on insulator") provided on the surface with a first semiconductor layer 4 based on silicon, in which a transistor channel 6 is formed. A gate 8 resting on a gate dielectric 10 made on the first half layer 4, is surrounded on either side by first insulating zones of spacings 12 or first spacers ("spacers" according to the English terminology) formed on the sides of the grid 8 and resting on the first semi-circular layer. The gate 10 and the channel 6 are lowered relative to the source 14 and drain 16 regions of the transistor 1. These source 14 and drain 16 regions have been made in a second semiconductor layer 18. based on silicon, formed after the gate 10 by resumption of epitaxy on the first semiconductor layer 4. Second spacers 20 designed around the first spacers 12, after growth of the second semiconductor layer 18, for their part to a thickness of this second semi-conductive layer 18. The base of these second spacers 20 is thus raised relative to that of the first spacers 12, so as to form, under these second spacers 20, a first access zone 22 between the source region 14 and the channel 10, and a second access zone 24 between the drain region 16 and the channel 10, each thicker than the first semiconductor layer 4 in which represents the channel 10. These zones 20 and 22 make it possible to reduce the access resistances between the source region and the channel on the one hand and between the drain region and the channel on the other hand.

The implementation of such an architecture is however delicate, insofar as it involves in particular performing steps of selective epitaxy recovery on ultrathin film, for example based on silicon and thickness less than 10 nanometers, to form the second semiconductor layer 18 and doping of the second semiconductor layer 18, all after forming the gate 8. Such an epitaxy can cause problems including d agglomeration of the ultra-thin film and inhomogeneity of the thickness of the layer formed by epitaxy. Such a doping step is tricky to achieve, insofar as, the first semiconductor layer having a small thickness, the risk of making this amorphous layer by doping is important.

There is the problem of finding a new thin semiconductor film transistor structure, wherein the access resistors between source and channel regions and between drain and channel regions are specifically optimized, as well as an improved method of realization of such a structure.

STATEMENT OF THE INVENTION

The present invention aims to provide a microelectronic device comprising one or more transistors formed on a film of small thickness ^¬ semi conductive or very low, for example less than 20 nanometers and 10 nanometers.

These transistors are provided with a structure giving them improved performances in terms of speed and consumption, in particular in terms of resistance of access between the source and the source regions. drain and channel, as well as in terms of gate resistance.

To achieve these objects, the present invention relates to a microelectronic device comprising:

a substrate coated with at least a first semiconductor layer based on a first semiconductor material in which at least one channel of a transistor is formed and on which at least one gate of said transistor rests,

at least one first block and at least one second block made of a second semiconductor material formed on either side of the gate and each resting on the first semiconductor layer, the first block and the second block being respectively endowed with at least a first inclined flank and at least one second inclined flank located opposite the grid, the inclined flanks forming a non - zero angle with a normal to the main plane of the substrate or the first semiconductor layer.

The microelectronic device may also further comprise at least one source region of said transistor formed at least partially in the first semiconductor block and at least one drain region of said transistor formed at least partially in the second semiconductor block.

The minimum distance or critical dimension between the inclined flanks of the first and second semiconductor blocks may be smaller than the critical dimensions usually obtained by photolithography methods. The inclined flanks of said first block and said second block, can realize with the first semiconductor layer, a bevel-shaped opening having a bottom revealing the first semiconductor material and a mouth wider than the bottom or having a critical dimension greater than that of the bottom.

By critical dimension, throughout the present description, the minimum dimension of an etched zone or block of a thin layer or of a stack of thin layers, measured in a plane parallel to the main plane of this thin layer or thin film stack, or the minimum dimension, of a zone or a block resulting from a thin layer or a stack of thin layers, measured in a plane parallel to the main plane of this thin layer or this stack of thin layers.

The first semiconductor material and the second semiconductor material may be different. The first semiconductor material may be chosen for its electrical properties, and may be a material in which the charge carrier mobility is good even when the thickness of the material is thin or ultra thin, for example less than 10 nanometers. The first semiconductor material may be SiGe or Ge.

The second semiconductor material may be an easy-to-model material such as Si.

Said first sidewall and said second sidewall can realize a non-zero angle with respect to main plane of the substrate or the first semiconductor layer.

According to a particular embodiment, the angle α may be 54.72 °. Thus, said first sidewall and said second sidewall may be parallel to the crystallographic plane (111) of the second semiconductor material.

The grid may be formed of a block having a base located opposite the first semiconductor layer and parallel to the main plane of the latter or to a main plane of the substrate and an apex opposite the base, whose critical dimension or minimum coast is greater than the critical dimension or the minimum coast of the base. The grid may be provided with at least one first lateral flank joining the top and the base of the gate block and at least one second lateral flank opposite the first flank and forming a non-zero angle with the first flank. Thus, the invention provides transistors with optimized grid shapes, to allow a high integration density. Such grid shapes may also make it possible to reduce the access resistance between the gate and the gate contact and to improve the switching speed of the transistor or transistors having such gates.

According to an alternative embodiment of the microelectronic device, the first lateral flank and the second lateral flank of the gate may have a curved shape. This curved shape can possibly follow the form of insulating spacers provided for the transistors.

Thus, the microelectronic device may further comprise: at least a first insulating zone or a first insulating spacer, located between the first inclined flank of said first semiconductor block and the gate dielectric, and at least one second insulating zone or a second insulating spacer, located between the second inclined flank of said second semiconductor block and the gate dielectric.

The invention also implements a method for producing a microelectronic device comprising the steps of: a) providing a substrate covered with at least a first semiconductor layer based on a first semiconductor material, in which at least one transistor channel is capable of being formed, and at least one second semiconductor layer on the first semiconductor layer, based on a second semiconductor material, b) realize in the second semiconductor material a bevel-shaped opening having a bottom revealing the first semiconductor material and a mouth of critical dimension greater than the critical dimension of the bottom, c) producing at least one gate on the first semi-layer -conductive in the bevel-shaped opening. The bevel-shaped opening can separate at least one first semiconductor block in which at least one drain region is capable of being formed and at least one second semiconductor block in which at least one source region is capable of to be formed. The first block and the second block may be respectively provided with at least one inclined first side and at least one second inclined side opposite one another and the gate, the first inclined side and the second side. tilted forming a non-zero angle to a normal to a main plane of the first semiconductor layer. Thus, the method according to the invention can allow the formation of source regions and drains with improved shape, and also the formation of channels of transistors of shorter length than the critical dimensions that are usually obtained by photolithography.

According to a particular implementation of the method, the walls of the bevel-shaped opening can make an angle of about 54.72 ° with a plane parallel to the main plane of the substrate or be parallel to the crystallographic plane (111) of the second material semiconductor. The method may further comprise, prior to step b): a step of doping the second semiconductor material. This doping step when it is performed at the beginning of the process may make it possible to avoid making the first semiconductor material amorphous, or to use the formation of a replacement grid. After doping the second semiconductor material ^¬ conductor, a silicidation step of the second semiconductor layer to complete the formation of drain and source regions of transistor regions.

The method may comprise, between step a) and step b):

depositing an insulating layer on the second semiconductor material, forming a hole in said insulating layer,

etching the second semiconductor material through the hole to form the bevel-shaped opening in the extension of the hole.

As for the step of forming the grid, the latter can be made with a base located opposite the first semiconductor layer and a top, opposite the base, having a critical dimension greater than the critical dimension from the base.

The method may further comprise the production of spacers prior to step c) of forming the grid.

According to one possibility of implementing the method, wherein the bevel-shaped opening has walls inclined at an angle normal to a parallel to the main plane of the substrate, and wherein the second semiconductor layer has a thickness e ₂ , the formation of the spacers may comprise: a deposition step of at least a thickness e ₃ of dielectric material in the bevel-shaped opening, such that e ₃ is chosen for etching to be substantially equal to: (e _{2 /} tan ( at ) ) ,

a step of etching the dielectric material.

According to another possibility, the spacers can be made, by at least one oxidation of the second semiconductor material, or by preferential oxidation of the second semiconductor material vis-à-vis the first material, in the bevel-shaped opening .

The first semiconductor material and the second semiconductor material may be different. This may make it possible, for example, to use the semiconductor layer based on the first semiconductor material as a stop layer when making the bevel-shaped opening, and to obtain a transistor channel produced in a semi-conductor film of both low and very low thickness, and precisely controlled.

The first semiconductor material may be a semiconductor material retaining good electrical properties, even at low thickness, such as SiGe or Ge.

The second semiconductor material can be a material that can be easily modeled, such as Si. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which:

FIG. 1, already described, represents an example of a microelectronic device according to the known art; FIGS. 2 and 3 illustrate an exemplary microelectronic device according to the invention;

FIGS. 4A-4G illustrate an exemplary method of producing a microelectronic device according to the invention; FIGS. 5A-5B show an alternative method of producing a microelectronic device according to the invention;

Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.

The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

An example of a microelectronic device according to the invention will now be described with reference to FIGS. 2 and 3. FIG. 2 represents a semiconductor-on-insulator substrate formed of a support 100 based on a semiconductor material, for example silicon, covered with an insulating layer 104, for example based on SiO ₂ , itself covered by a first semiconductor layer, based on a first semiconductor material 108, such as for example Ge, or SiGe. The first semiconductor layer 108 may have a thickness of between 1 nanometer and 30 nanometers, for example of the order of 10 nanometers.

Semiconductor zones or blocks 113 and 114, based on a second semiconductor material 112, cover the upper face of the first semiconductor layer. The second semiconductor material 112 may be different from the first semiconductor material 108, for example Si.

The semiconductor blocks 113 and 114 are also provided with sloping flanks and comprise in particular respectively at least one inclined first flank 115 and at least one second inclined flank 116 situated opposite the first flank 115. Each of the flanks 115 and 116 forms an angle non-zero with a normal n to the main plane of the substrate 100 or the main plane of the layer 108, or an angle α different from 90 ° with a plane parallel to the main plane of the substrate 100 or the main plane of the layer 108 (the plane principal of the substrate 100 being a plane belonging to the latter and parallel to the plane [O; i; k] of an orthogonal reference [O; i; j; k] defined in FIG. 2). The angle α between each of the flanks 115 and 116 and the main plane of the substrate 100 may be such that: 0 ° <a <90 °, and preferably between 20 ° <a <70 °. According to one particular embodiment, each of the flanks 115 and 116 can make an angle (X with the main plane of the substrate 100, of the order of 54.72 ° or have a direction parallel to the crystalline plane (111) of the second material semiconductor 112.

The inclined flanks 115 and 116 form, with the upper face of the layer based on the first semiconductor material 108, an enlarged aperture 117, in the form of a bevel, the bottom 118 of which has a critical dimension or a minimum dimension less than that from its mouth 119.

As illustrated in FIG. 3, the microelectronic device according to the invention can for example be made in CMOS (CMOS for "complementary metal-oxide semiconductor" or "complementary metal oxide semiconductor") technology and comprise at least one transistor Ti, having a channel 110, formed in the first semiconductor material 108, opposite the bottom of the bevel-shaped opening. The channel 110 may have a length L (measured in a direction parallel to the vector i of an orthogonal reference mark [O; i; j; k] defined in FIG. 3) equal to or substantially equal to the critical dimension of the background of the aperture in the form of bevel, or the minimum length separating the semiconductor blocks 113 and 114. The length of the channel L can be less than critical dimensions that can be obtained by a conventional method of photolithography and for example between 1 and 20 nanometers, for example of the order of 10 nanometers. The semiconductor blocks 113 and 114 can themselves be doped so that they belong to, or form, respectively, a drain region and a source region of the transistor Ti. The blocks 113 and 114 may for example be N-doped, and belong respectively to a drain region and a source region of a NMOS type transistor T ₁ . In another example, the blocks 113 and 114 may be P-doped and belong to, or form, respectively, a drain region and a source region of a PMOS type transistor T ₁ .

The drain and source regions of the transistor T ₁ may possibly extend into the first semiconductor material 108. Thus, regions of the layer based on the first semiconductor material 108, lying in the extension in an orthogonal direction. at the main plane of the substrate 100 (parallel to the vector j of the orthogonal reference [0; i; j; k]) semiconductor blocks 113 and 114 may optionally be also doped.

The semiconductor blocks 113 and 114 are also covered with an insulating material. On an upper face and parallel to a main plane of the substrate 100, each of the semiconductor blocks 113 and 114, notably rests an insulating material, for example based on HTO type silicon oxide (HTO for "High Temperature Oxide" or "high temperature oxide") of an insulating layer 120. The insulating layer 120 is perforated and in particular provided with at least one hole, in the extension of the bevel-shaped opening. This hole may have walls orthogonal to the main plane of the substrate 100 (the main plane of the substrate 100 being a plane belonging to the latter and parallel to the plane [O; i; k] defined in FIG. 4). The walls of the hole, and the walls of the bevel-shaped opening, realize an angle different from 180 °, and for example of the order of 145 °. Thus, the inclined flanks 115 and 116 of the semiconductor blocks 113 and 114, and the sides noted 123 and 124 of the insulating layer 120, achieve an angle other than 180 °. The hole and the bevel-shaped opening in its extension form an orifice, in which there is a gate 130 of the transistor Ti. The gate 130 rests on a region of the first semiconductor layer located at the bottom of the bevel-shaped opening, between the semiconductor blocks 113 and 114.

This gate 130 is formed of a block based on a gate material 134, for example based on a semiconductor such as polysilicon or germanium polysilicide, or a metal such as molybdenum or TiN, or the TaN. The block of gate material 134 has a bottom face or a base 135 facing the first semiconductor material 108, and of critical width or dimension di, and an upper face or an apex 136 opposite the base 135, of width or critical dimension d ₂ greater than di. The critical dimension or minimum dimension di base 135, may be for example of the order of 10 nanometers, or between 5 nm and 100 nm, while the critical dimension or minimum side d ₂ of the summit 136, may be for example of the order of 30 nanometers, or between 15 nm and 300 nm (the critical dimensions di and d ₂ are each defined in a direction parallel to the vector i orthogonal reference [O; i; j; k]). The grid material block 130 also has opposite side flanks 137 and 138, joining the base 135 and the apex 136, and forming at least one non-zero angle β between them. The lateral flanks 137 and 138 of the grid material block 134 may furthermore (as illustrated in FIG. 3) each have a curved shape, and give the grid 130 a flared shape or shape.

According to a particular implementation of the gate 130, the critical dimension di of the base 135 can be possibly much smaller than the critical dimension d ₂ of the peak 136, for example so that d ₂ > 2 * di or / and for example so that from the top 136 to the base 135, the grid 130 provides a pointed shape.

The base 135 and the lateral flanks 137 and 138 of the grid material block 134 are furthermore coated with a gate-based dielectric layer 132, for example SiO ₂ or a material of high dielectric constant ("high-k"). According to the English terminology) such as HfO ₂ , or ZrO ₂ , or Al ₂ O ₃ , or ZrO ₂ . Insulating spacing zones 140 commonly called "spacers"("spacers according to the Anglo-Saxon terminology) can also be made around the grid 130.

The spacers 140 may be formed first of a thickness, which may be fine and conformal, based on a first dielectric material 142, for example SiO ₂ , resting on the inclined sides 115 and 116 of the semi-circular zones. Conductors 113 and 114 and optionally on the panels 123 and 124 of the insulating layer 120. The spacers 140 may also comprise blocks based on a second dielectric material 144, located between the first dielectric material 142 and the gate dielectric 132. According to the etching method used, the blocks based on the second dielectric material 144 may optionally have a curved shape, which matches the flared shape of the grid 130.

In the transistor architecture Ti which has just been described, the first semiconductor material 108 in which the channel 110 is formed has a thin thickness, which in particular makes it possible to reduce the short channel effects. The thickness of the semiconductor material 108 located under the gate 130 is moreover controlled or adjusted precisely. With regard to the distance between the drain and source regions of the transistor due to the inclination of the sidewalls 117 and 118 of the semiconductor blocks, this distance may be smaller than the critical dimensions between the drain region and the region. of source, which is usually obtained using conventional photolithography processes. Of similarly, the base 135 of the grid 130 has a minimum or critical dimension smaller than the critical dimensions usually obtained by photolithography. By the inclination of the flanks 117 and 118 of the semiconductor blocks 113 and 114, regions 160 and 162 respectively of access between the drain region and the channel and between the source region and the channel, located under the spacers 140, have an improved sharp shape, which gives the transistor structure Ti channel-to-drain and channel-source access resistances, reduced compared to those of the structures of the prior art.

By the shape of the gate 130, the base 135 has a critical dimension di smaller than d ₂ of the top 136, the access resistance between the gate 130 and channel is also improved. This may make it possible to give the transistor Ti an increased switching speed. An exemplary method for producing a microelectronic device according to the invention, of the type just described, will now be given in connection with FIGS. 4A-4G.

The starting material of this process may be a semiconductor-on-insulator substrate formed of a semiconductor substrate 200, for example based on silicon, covered with an insulating layer 204, for example based on SiO ₂ , itself covered with a first semiconductor layer, of fine and controlled thickness, for example between 5 and 10 nanometers and based on a first semiconductor material ^¬ conductor 208, e.g., Ge, or SiGe.

In the first semiconductor material 208 is intended to be formed at least one transistor channel.

A second semiconductor layer, of thickness e ₂ , for example between 10 and 50 nanometers, or for example of the order of 15 nanometers based on a second semiconductor material 212, is then formed on the first semiconductor material 208. The second semiconductor material 212 may be different from the first semiconductor material 208, for example Si. The second semiconductor material 212 may optionally be formed by transfer or bonding to the support 200, same time as the first semiconductor material 208, or using, for example, an epitaxy (Figure 4A).

In particular in the context of the formation of active areas of transistors, and in particular of the production of drain regions and of transistor source regions, one or more doping steps of the second semiconductor material 212 may or may to be carried out, for example by implantation or by diffusion. According to a first example, the doping can be carried out by implantation of regions located on the surface or in the upper part of the layer based on the second semiconductor material 212 in order to produce at least source region 213 and at least one drain region. 214 in the latter. According to a second example, a doping of the entire thickness of the layer based on the second semiconductor material 212 may be performed (the regions 213 and 214 being delimited by discontinuous lines in FIG. 4B). In the second case, the doping can be carried out so that the doping species do not diffuse or diffuse little in the first semiconductor material 208. For this, an insitu doping, performed during an epitaxial formation step second semiconductor material 212 can be performed. To limit the doping of the first semiconductor material 208, it is also possible to produce implantation profiles in the second semiconductor material 212. The doping of the second semiconductor material 212 can be specifically carried out at the beginning of the process in order to avoid making amorphous the first semiconductor material 208 or having to form a replacement grid. The microelectronic device, which one wishes to achieve may be intended to include components in CMOS technology. In this case, at least one N type doping step of the second semiconductor material 212 can be performed, for example through masking (not shown in FIG. 4B), to form source regions and NMOS transistors drain regions in predetermined areas of this material. At least one other P-type doping step, for example through another masking (not shown in FIG. 4B), may be also planned for the realization of regions of drains and sources of PMOS transistors.

For a subsequent etching of the layer based on the second semiconductor material 212 to be possible, the concentration of charged impurities introduced during the doping may be chosen to be less than a predetermined threshold, for example of the order of 10 ^19. cm ^"3 .

In order to complete the formation of the drain regions and transistor sources, a silicidation step of the latter can then be performed. This siliciding can be carried out by depositing a material such as, for example, Ni or Ti or Co on the second semiconductor material 212 on top of the source and drain regions.

Then, in order to delimit active zones and to isolate between them these active zones, isolation zones (not shown) are produced in the layer based on the second semiconductor 212 and in the layer based on the first semiconductor 208. ) by means of a conventional insulation method, for example of STI (STI for Shallow Trench Isolation) or LOCOS type for local oxidation of silicon), or by producing zones of MESA type insulations.

Then, on the assembly, the deposition of a layer 220 based on an insulating material, for example a silicon oxide HTO (HTO for "High Temperature Oxide" or high temperature oxide), of thickness which can be for example between 10 nanometers and 100 nanometers, for example of the order of 30 nanometers.

Then, for example by means of a photolithography process, holes 221 are formed in the insulating layer 220, revealing the second semiconductor material 212. The holes 221 may be provided with walls 223 and 224 which are orthogonal to the plane of the substrate 200 and have a minimum or critical dimension noted Lt, for example between 20 nanometers and 40 nanometers, for example of the order of 30 nanometers (the main plane of the substrate and the critical dimension Lt being respectively defined on the 4C, by a plane belonging to the substrate 100 and parallel to a plane [O; i; k] of an orthogonal reference [O; i; j; k], and by a dimension measured in a direction parallel to a vector i landmark

[O;?; j; k]).

Anisotropic etching of the second semiconductor material 212 is then carried out in the extension of the holes 221, so as to make openings 225 whose bottom 230 unveils the first semiconductor material 208, and to form semiconductor blocks 226. and 227 separated by the apertures 225. The layer based on the first semiconductor material 208 may serve as a barrier layer during this etching step. The etching of the second semiconductor material 212 is moreover carried out so that the openings 225 comprise a mouthpiece (not referenced), having a critical dimension or a minimum edge Lt higher than the critical dimension or the minimum Lc of their bottom 230.

The walls 223 and 224 of the holes 221 form an angle different from 180 ° with those of the openings 225. Thus, the semiconductor blocks 226 and 227 respectively comprise at least one first side 228 and at least one second side 229 forming a different angle. 180 ° with the walls 223 and 224 of the holes 221. The flanks 228 and 229 of the semiconductor blocks 226 and 227 are located opposite one another and each realize an angle of inclination a with a parallel plane. at the main plane of the substrate 200 or with the upper face of the layer based on the first semiconductor material 208, such that: 0 ° <a <90 °, preferably such that a is between 20 ° and 70 °.

Due to the inclination of the flanks 228 and 229, relative to the bottom 230 of the openings 225, the latter have a shape called "bevel".

According to a particular implementation of the method, the etching of the second semiconductor material 212 may be carried out in the direction of the crystalline plane (111), so that the angle α is substantially equal to 54.73 °. In the case, for example, where the second semiconductor material 212 is based on silicon and the first semiconductor material 208 is based on germanium or an alloy of silicon and germanium, the openings 225 in the form of bevel can be achieved by means chemical etching, for example using TMAH (TMAH for tetra-methylammonium hydroxyl).

With regard to the bottom 230 of the openings 225, the critical dimension Lc of this bottom 230 or the minimum distance Lc separating the flanks 228 and

229 of the semiconductor blocks 226 and 227 may be smaller than the minimum critical dimensions or dimensions obtainable by a conventional photolithography method (the critical dimension Lc being defined in FIG. dimension measured in a direction parallel to the vector i of the reference

[0; i; j; k]). The critical dimension Lc of the bottom 230 of the openings 225 may be modulated as a function in particular of the thickness e ₂ of the second semiconductor material 212 and be such that:

Lc ≈ Lt-2 * e ₂ / tan (α).

The critical dimension Lc of the openings 225 can be between 2 nanometers and 20 nanometers, or be for example of the order of 10 nanometers. From a functional point of view, the semiconductor blocks 226 and 227 may respectively form or be respectively comprised in a source region and a drain region of a transistor. These source and drain regions may, depending on the manner in which the semiconductor layers 208 and 212 have been doped, possibly extend into regions of the semiconductor layer 208 facing the semiconductor blocks 226 and 227. The location of a channel 232 of the transistor, is in turn provided in a region of the first semiconductor material 208, located opposite the bottom 230 of the openings 225. This channel 232 may have a length substantially equal to the critical dimension Lc separating the flanks 228 and 229 of the semiconductor blocks 226 and 227.

The bottom 230 of each of the openings 225 made in the second semiconductor material 212, further defines a location for a gate to be subsequently formed on the first semiconductor material 208.

After delimiting a transistor gate location, spacing insulating zones or "spacers" 244 (spacers according to the English terminology) may be realized, in particular to avoid forming parasitic capacitances between the source region and the future. grid and / or between the drain region and the future grid.

According to one possible implementation of these spacers 244, first of all the conformal deposition of a thin layer of thickness of the order of several nanometers, for example of the order of 3 nanometers, based on a first dielectric material 240, for example a silicon oxide HTO, so as to cover the upper face of the insulating layer 220, as well as the walls of the holes 221 and openings 225, and the bottom 230 of the latter.

Then, the deposition of a layer based on a second dielectric material 242, for example Si3N ₄ , on the first dielectric material 240. This deposit may be consistent and of thickness noted θ3, chosen according to the angle of inclination of walls of the apertures 225 bevel-shaped (Figure 4E).

According to a particular embodiment of the spacers 244, so that the latter, once formed, cover, preferably entirely, the flanks 228 and 229 of the semiconductor blocks 226 and 227, without being in contact, or so as to have a very small contact area with the first semiconductor material 208, the thickness e ₃ of the second dielectric material 242 is chosen to be close to, or substantially equal to, or equal to e ₂ / tanα

(With e ₂ the thickness of the layer based on the second semiconductor material 212 and the angle of inclination of the flanks 228 and 229 with respect to the layer 208).

In the case, for example, where the second semiconductor material 212 has a thickness e ₂ of the order of 15 nanometers, the thickness e ₃ of the layer based on the second dielectric material 242 may for example be order of 10 nanometers.

An anisotropic etching step of the second dielectric material 242, for example by dry etching, for example anisotropic plasma etching, is then performed. This etching can be carried out using a RIE (RIE for "Reactive Ion Etching" or "reactive ion etching") method, so as to remove the second dielectric material 242 from the top of the insulating layer 220, and from the bottom 230 apertures 225 in the form of a bevel. According to a first condition, the etching of the second dielectric material 242 can be made, so that the flanks 228 and 229 of the semiconductor blocks 226 and 227 are not exposed or the second dielectric material 242 is preserved against the inclined sides 228 and 229. According to a second condition, the etching of the second Dielectric material 242 can also be made, so that the bottom of the bevel-shaped opening is unveiled or the second dielectric material 242 is not kept at the bottom of this opening.

The first and second conditions can be followed in particular by choosing the thickness e ₃ ≈ e ₂ / tanα of the second dielectric material. To complete the formation of spacers

244, an etching of the first dielectric material 240, can then be performed, so as to remove this material from the bottom 230 of the apertures 225 shaped bevel. This etching may be, for example a wet etching using hydrofluoric acid (HF), selective both vis-à-vis the second dielectric material 242 and the first semiconductor material 208. After etching the second material dielectric and the first dielectric material, the hole and the bevel-shaped opening, have walls covered with dielectric material, which form a flared orifice 246. The spacers 244 made against the flanks 228 and 229 of the semiconductor blocks 226 and 227 may have a curved shape. Thus, the flared orifice 246 may have curved walls.

The orifices 246 are also provided with a mouth 247 of critical dimension close to the critical dimension Lt and a bottom 248 of critical dimension smaller than that of the mouth 247 and close to the critical dimension Lc (Figure 4F).

After formation of the spacers 244, and prior to the formation of a gate 250, a step of cleaning the bottom 248 of the orifices 246 can be carried out for example using hydrofluoric acid.

Subsequently, a conformal deposition of a dielectric material 252 of a grid, for example based on SiO ₂ , or a high dielectric constant material ("high-k"), such as HfO ₂ , or ZrO ₂ , or Al ₂ O ₃ , or La ₂ O ₃ , on the walls and at the bottom 248 of the orifices 246.

Another deposit is then made in order to fill the orifices 246 with a material 254 of a grid, for example based on a semiconductor such as polysilicon or poly-SiGe or a metallic material such as TiN or such as a refractory metal. The deposition of the gate material 254 may be made so that this material 254 protrudes from the mouth 247 of the orifices 246 and covers the upper face of the insulating layer 220. In this case, a mechano-chemical planarization step ( CMP for "Chemical Mechanical Planarization") can be performed in order to conserve the material of grid 254 only up to the level of the mouth 247 of the orifices 246.

Contacts for the source and drain regions, and possibly for the grid 250, can then be produced by deposition of an insulating layer on the assembly and then by photolithography and etching of holes, facing the source regions, drain, and possibly for the grid 250, implantation steps through the holes, optionally siliciding, then deposition of a conductive material can then be performed.

According to a variant of the process example described above, the formation of the spacers 234 described with reference to FIGS. 4E-4F can be carried out after formation of the openings 225 in the second semiconductor material 212 by oxidation of the first and second semiconductor material. An oxide layer 260 is thus formed, in particular on the inclined sides of the semiconductor blocks 226 and 227 (FIG. 5A). In the case, especially where the second semiconductor material 212 is based on Si, and the first semiconductor material 208 is based on SiGe or Ge, the oxidation may be a preferential oxidation of the second semiconductor material 208 in relation to the first semiconductor material 212. In this case, the oxide formed on the layer based on the first semiconductor material 208 is very volatile and removed with the aid of an appropriate cleaning (FIG. 5B). According to another variant of the example of the method described above, the formation of the source and drain zones, and in particular the silicidation step described above in connection with FIG. 4B, can be carried out after the formation of the grid 230.

For this, the insulating layer 220 covering the second semiconductor material 212 and surrounding the spacers 120, can be removed, so as to reveal the second semiconductor material 212. A Ni-based layer can then be deposited on parts unveiled second semiconductor material 212 to perform this silicidation. The method which has just been described makes it possible to unveil the first semiconductor material 208 only during the production of the grid. Thus, during the process, the first semiconductor material 208 can be protected by the second semiconductor material 212 cleaning solutions used during possible steps of silicidation of source and drain regions, and making contacts sources and drain.

The first semiconductor material 208 being protected or encapsulated by the second material 212, during a possible siliciding, only the material 212 is silicided. In a case where the activation of the doping is more difficult to achieve in the first material 208 than in the second material 212, the layer based on the second material 212 once doped and activated can serve as a conduction layer for the source and drain regions.

Claims

A microelectronic device comprising: a substrate (100) covered with at least a first semiconductor layer formed of a first semiconductor material (108) based on SiGe or Ge, in which at least one channel

(110) of a transistor (Tl) and on which rests at least one gate (130) of said transistor (Tl),

at least one first block (113) and at least one second block (114) made of a second semiconductor material (112) based on Si formed on either side of the gate (130) and resting on the first semiconductor layer, the first block (113) and the second block (114) being respectively provided with at least one inclined flank (115) and at least one second inclined flank (116) located opposite the grid, the inclined flanks forming a non-zero angle with a normal ( ⁿ ) to the main plane of the substrate (100).

2. Microelectronic device according to claim 1, the inclined sides (115,116) of said first block (113) and said second block (114), making with the first semiconductor layer, a bevel-shaped opening with a revealing bottom. the first semiconductor material (108) and a mouthpiece, the mouth being wider than the bottom.

3. microelectronic device according to one of claims 1 or 2, wherein the gate (130) is formed of a block having a base (135) located opposite the first semiconductor layer and a vertex (136) opposite the base (135), the base (135) having a critical dimension (di) smaller than the critical dimension (d ₂ ) of the apex (136).

4. microelectronic device according to one of claims 1 to 3, wherein the gate (130) is provided with at least a first side flank (137) joining the top (136) and the base (135) of the gate block (130) and at least a second side flank (138) opposite to the first, the first side flank (137) and the second side flank (138) forming between them at least a non-zero angle (β).

5. Microelectronic device according to claim 4, the first lateral flank (137) and the second lateral flank (138) having a curved shape.

The microelectronic device according to one of claims 1 to 5, further comprising: at least one source region of said transistor formed at least partially in the first semiconductor block (113) and at least one drain region of the formed transistor at least partially in the second semiconductor block (114).

7. Microelectronic device according to one of claims 1 to 6, wherein the grid is encapsulated in a gate dielectric material (132), further comprising: at least a first insulating area located between the first inclined sidewall (115) of said first semiconductor block (113) and the gate dielectric (132), and minus a second insulating zone between the second inclined flank (116) of said second semiconductor block (114) and the gate dielectric (132).

8. Microelectronic device according to one of claims 1 to 7, said first sidewall (115) and said second sidewall (116) producing an angle (a) of 54.72 ° neighboring a plane parallel to the main plane of the substrate (100). ) or being parallel to the crystallographic plane (Hl) 'of the second semi ^¬ conductive material (112).

9. A method of producing a microelectronic device comprising the steps of: a) providing a substrate covered with at least a first semiconductor layer made of a first semiconductor material (208) based on SiGe or Ge in which at least one transistor channel is capable of being formed and on this first semiconductor layer of at least one second semiconductor layer made of a second semiconductor material based on Si, b) producing in the second material semiconductor a bevel-shaped opening (225) having a bottom (230) revealing the first semiconductor material (208) and a mouthpiece (Lt) of critical size greater than the critical dimension (LC) of the bottom, c) providing at least one gate (250) on the first semiconductor layer in the opening (225) in bevel shape.

10. A method of producing a microelectronic device according to claim 9, the opening

Wedge-shaped member (225) separating at least one first semiconductor block (226) in which at least one drain region is capable of being formed and at least one second semiconductor block (227) in which at least one source region is capable of being formed, the first block (226) and the second block (227) respectively having at least one inclined first edge (228) and at least one second inclined edge (229) facing one of the other and the grid

(250), the first inclined flank and the second inclined flank achieving a non-zero angle with respect to a normal (n) in the main plane of the first semiconductor layer.

11. A method of producing a microelectronic device according to one of claims 9 or 10, the walls of the aperture (225) shaped bevel forming an angle (a) of 54.72 ° with a parallel plane to main plane of the substrate (200) or being parallel to the crystallographic plane ^Λ (111) 'of the second semiconductor material (212).

12. A method of producing a microelectronic device according to one of claims 9 to 11, further comprising, prior to step b): a step of doping the second semiconductor material (212).

13. A method of producing a microelectronic device according to claim 12, further comprising, after doping the second semiconductor material (212): a siliciding step of the second semiconductor layer.

14. A method of producing a microelectronic device according to one of claims 9 to 13, comprising, between step a) and step b):

depositing an insulating layer (220) on the second semiconductor material (212),

- forming a hole (221) in said insulating layer (220), - etching the second semiconductor material (212) through the hole (221) to form the bevel-shaped opening (225) in the extension of the hole (221).

15. A method of producing a microelectronic device according to one of claims 10 to 14, wherein the gate (250) is provided with a base located opposite the first semiconductor layer and a top to the top. opposite of the base, the base having a critical dimension smaller than the critical dimension of the vertex.

16. A method of producing a microelectronic device according to one of claims 9 to 15, further comprising: a step of forming spacers (244), prior to step c) of forming the grid (250) .

A method of making a microelectronic device according to claim 16, wherein the bevel-shaped opening has walls inclined at an angle OC with respect to a parallel to the main plane of the substrate, and wherein the second layer semiconductor has a thickness e ₂ , the formation of the spacers (244) comprising:

a deposition step of at least a thickness e ₃ of the order or substantially equal to (e _{2 /} tan (α)) of dielectric material (242) in the bevel-shaped opening,

a step of etching the dielectric material (242),

18. A method of producing a microelectronic device according to claim 17, the spacers (244) being made by at least one oxidation of the second semiconductor material (212) in the aperture (225) beveled.