WO2006060978A1 - Wide band-gap, high relative permittivity material - Google Patents

Wide band-gap, high relative permittivity material Download PDF

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Publication number
WO2006060978A1
WO2006060978A1 PCT/DE2005/002090 DE2005002090W WO2006060978A1 WO 2006060978 A1 WO2006060978 A1 WO 2006060978A1 DE 2005002090 W DE2005002090 W DE 2005002090W WO 2006060978 A1 WO2006060978 A1 WO 2006060978A1
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gate
compounds
dielectric constant
layer
substrate
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PCT/DE2005/002090
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German (de)
French (fr)
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Jürgen Schubert
Tassilo Heeg
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Forschungszentrum Jülich GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the invention relates to a material with a high bandgap and dielectric constant.
  • materials with a higher dielectric constant can be used.
  • sistors with respect to high charge carrier mobility is not sufficient.
  • an HfO 2 isolation layer reduces carrier mobility in silicon by a factor of two due to soft phonons. These are a material-specific property and couple to the charge carriers in the transistor channel.
  • titanates z. B. (Ba, Sr) TiO 3 , to produce DRAM.
  • the object of the invention is to provide a material for a
  • Semiconductor device in particular to provide a suitable gate material, which has a significantly increased dielectric constant of K> 5 and SiO 2 over an optical band gap of> 4 eV.
  • the object is achieved by a material according to the main claim.
  • Advantageous embodiments will be apparent from the claims referring back to each of them.
  • the material comprises at least two compounds, of which the first has a dielectric constant K> 5 and the second has an optical band gap> 4 eV at room temperature.
  • the material has both a high dielectric constant of K> 5 and a comparison with the prior art
  • the material can be used in particular to form a gate.
  • the material advantageously comprises at least one compound from the group of scandates and titanates.
  • the material has a dielectric constant of about K> 40 selected from the titanates by the compound selected.
  • the material has an optical bandgap> 4 eV due to the scandate.
  • titanate BaTiO 3 and / or SrTiO 3 may be provided. It is possible to provide both compounds in the material according to the invention in addition to another compound from the group of scandates.
  • GdScO 3 may be provided.
  • Other rare earth elements such as Pr, Nd, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb or Lu instead of Gd may also be provided.
  • the at least two compounds of the material can form the gate homogeneously distributed.
  • This term also encompasses a gate in which the connections are applied repeatedly alternately on the substrate to form the gate.
  • the at least two compounds of the material according to the invention are homogeneously distributed or mixed in the gate.
  • the at least two compounds for producing a functional layer can also be applied only once in succession to a suitable substrate.
  • the compounds are not homogeneously distributed, but depending on the selected layer thickness and the compounds form a single functional layer, such.
  • a gate By the disclosed procedures is thus advantageously effected that on the substrate of z.
  • B. silicon a layer sequence of at least two compounds is arranged in the advantageous the Eigen- shafts of a large dielectric constant with K> 5 are connected with an optical band gap> 4 eV.
  • the material or gate oxide according to the invention is a material with thermodynamic stability on a semiconductor substrate, for. As silicon, and thus ensures compatibility with the CMOS technology.
  • a method for producing a gate oxide provides, on a substrate made of in particular silicon, first to deposit the scandate and then the titanate at least once. This advantageously ensures that no elements of the titanate diffuse into the silicon substrate.
  • FIG. 1 shows an RBS spectrum of a 100 nm thick layer which is deposited on silicon by means of pulsed laser deposition. Position was made. The deposition temperature was about 400 ° C. Rutherford backscatter experiments (RBS) allow analysis of element distribution and layer thickness.
  • the layer consists of BaTiO 3 and GdScO 3 .
  • the two compounds were mutually deposited 20 times each on the silicon substrate to form GdScO 3 and BaTiO 3 layers, so that there is a homogeneous distribution of both compounds in the layer on the substrate.
  • the individual layers are thinner than 3 nm in order to ensure the best possible mixing of the compounds.
  • the signals of the individual elements are assigned by symbols.
  • the stoichiometry of this layer was determined by comparison with a simulation, which is shown as a solid curve. The result is a composition of (BaTiO 3 ) 0. 7 (GdScO 3 ) 0.3.
  • This layer was subsequently provided with gold contacts for electrical characterization.
  • a capacitance measurement was carried out at 1 MHz operating frequency (FIG. 2).
  • the measured capacitance of the layer is plotted against the applied voltage. With negative voltages of - 3 V, a dielectric constant can be determined from the capacitance.
  • the substrate may be provided as shown silicon. In this case, starting with a GdScO 3 layer on silicon. Subsequently, the BaTiO 3 layer is deposited thereon.
  • a hysteresis characteristic in the capacitance measurement (Fig. 2) to obtain an anneal at 500 0 C in a Forminggas atmosphere with 80% N 2 and 20% H 2 is carried out.
  • the layer withstands an applied voltage of 20 V, which corresponds to a breakdown of 2 MV / cm. This is to be regarded as the lower value of the breakdown field strength.
  • the invention is not limited thereto. It is possible to arrange the two compounds not 3 nanometers thin and multiply alternating as described above, but successively and immediately in the desired layer thickness on the substrate, so that the gate consists of a layer system of only two individual layers.
  • the gate is then preferably by a direct formed on the substrate scandate and a titanate arranged thereon.

Abstract

The invention relates to a wide band-gap, high relative permittivity material for semiconductor components. The inventive material comprises at least two compounds, the first of which has a relative permittivity of κ > 5 and the second of which has an optical band gap of > 4 eV.

Description

B e s c h r e i b u n g Description
Material mit hoher Bandlücke und DielektrizitätskonstanteHigh band gap material and dielectric constant
Die Erfindung betrifft ein Material mit hoher Bandlücke und Dielektrizitätskonstante.The invention relates to a material with a high bandgap and dielectric constant.
Aus dem Stand der Technik ist bekannt, SiO2 als Gatematerial für einen Transistor zu verwenden. SiO2 weist eine vergleichsweise niedrige Dielektrizitätskonstante von nur K = 3,9 bei einer optischen Bandlücke von etwa 9 eV auf.From the prior art it is known to use SiO 2 as the gate material for a transistor. SiO 2 has a comparatively low dielectric constant of only K = 3.9 at an optical band gap of about 9 eV.
Mit weiter fortschreitender Miniaturisierung mikroelektronischer Bauelemente ist es ein Ansatz, die Schichtdicke des Gates auf weniger als 1 nm zu reduzieren. Nachteilig werden im Falle von SiO2 als Gatematerial bei derartigen Schichtdicken die Leckströme in Transistoren sehr groß. In der Isolationsschicht sollten aber nur geringe Leckströme vorliegen.With advancing miniaturization of microelectronic devices, it is an approach to reduce the layer thickness of the gate to less than 1 nm. A disadvantage in the case of SiO 2 as a gate material with such layer thicknesses, the leakage currents in transistors very large. In the insulation layer but should be present only low leakage currents.
Alternativ können Materialien mit höherer Dielektrizi- tätskonstante verwendet werden.Alternatively, materials with a higher dielectric constant can be used.
Aus dem Stand der Technik sind Oxide, z. B. HfO2, ZrO2 oder REScO3 (mit RE=Dy, Gd, La) bekannt. Diese weisen eine Dielektrizitätskonstante von etwa K = 20-25 bei einer optischen Bandlücke von > 5 eV auf.From the prior art oxides, z. As HfO 2 , ZrO 2 or REScO 3 (with RE = Dy, Gd, La) known. These have a dielectric constant of about K = 20-25 at an optical band gap of> 5 eV.
Eine Dielektrizitätskonstante von K = 25 ist für dieA dielectric constant of K = 25 is for the
Anforderungen insbesondere an das Gateoxid eines Tran- sistors in Bezug auf hohe Ladungsträgerbeweglichkeit jedoch nicht ausreichend. Beispielsweise reduziert eine Hf02-lsolationsschicht die Ladungsträgerbeweglichkeit im Silizium auf Grund weicher Phononen um den Faktor zwei. Diese sind eine materialspezifische Eigenschaft und koppeln an die Ladungsträger im Transistorkanal an.Requirements in particular for the gate oxide of a trans- However, sistors with respect to high charge carrier mobility is not sufficient. For example, an HfO 2 isolation layer reduces carrier mobility in silicon by a factor of two due to soft phonons. These are a material-specific property and couple to the charge carriers in the transistor channel.
Ebenfalls bekannt sind Titanate, z. B. (Ba, Sr)TiO3, zur Erzeugung von DRAM.Also known are titanates, z. B. (Ba, Sr) TiO 3 , to produce DRAM.
Diese Materialien weisen sehr hohe Dielektrizitäts- konstanten von K = 300-10000 bei Raumtemperatur auf.These materials have very high dielectric constants of K = 300-10000 at room temperature.
Nachteilig zeigen diese Materialien aber optische Bandlücken von < 4 eV.Disadvantageously, however, these materials show optical band gaps of <4 eV.
Aus Schlom und Haeni ist bekannt (Schlom, D.G., Haeni, J.H. (2002) . A thermodynamically approach to selecting alternative gate materials. MRS Bulletin 198-204) , dass Titanate in direktem Kontakt mit Silizium thermodyna- misch instabil sind. Bei Temperaturen großer Raumtemperatur, insbesondere von bis zu 1000 0C, die bei der Erzeugung moderner MOSFET angewendet werden, erfolgt nachteilig eine Legierungsbildung zwischen den Titana- ten und dem Silizium. Weiterhin ist bei diesen Materialien die Bandlücke von etwa 3,5 eV zu gering, um ausreichend niedrige Leckstrδme zu gewährleisten. Titanate werden daher als Gatematerial als ungeeignet angesehen.It is known from Schlom and Haeni (Schlom, DG, Haeni, JH, 2002) that titanates in direct contact with silicon are thermodynamically unstable. At temperatures large room temperature, in particular up to 1000 0 C, the modern in the generation MOSFET are applied, is carried adverse alloy formation between the Titana- th and silicon. Furthermore, in these materials, the band gap of about 3.5 eV is too low to ensure sufficiently low leakage currents. Titanates are therefore considered as gate material unsuitable.
Aufgabe der Erfindung ist es, ein Material für einThe object of the invention is to provide a material for a
Halbleiter-Bauelement, insbesondere ein geeignetes Gatematerial bereit zu stellen, das gegenüber SiO2 eine signifikant erhöhte Dielektrizitätskonstante von K > 5 und eine optische Bandlücke von > 4 eV aufweist. Die Aufgabe wird durch ein Material gemäß Hauptanspruch gelöst. Vorteilhafte Ausgestaltungen ergeben sich aus den darauf jeweils rückbezogenen Patentansprüchen.Semiconductor device, in particular to provide a suitable gate material, which has a significantly increased dielectric constant of K> 5 and SiO 2 over an optical band gap of> 4 eV. The object is achieved by a material according to the main claim. Advantageous embodiments will be apparent from the claims referring back to each of them.
Erfindungsgemäß umfasst das Material mindestens zwei Verbindungen, von denen die erste eine Dielektrizitätskonstante K > 5 und die zweite eine optische Bandlücke > 4 eV bei Raumtemperatur aufweist . Auf diese Weise wird vorteilhaft gewährleistet, dass das Material sowohl eine hohe Dielektrizitätskonstante von K > 5 als auch eine im Vergleich zum Stand derAccording to the invention, the material comprises at least two compounds, of which the first has a dielectric constant K> 5 and the second has an optical band gap> 4 eV at room temperature. In this way, it is advantageously ensured that the material has both a high dielectric constant of K> 5 and a comparison with the prior art
Technik erhöhte optische Bandlücke > 4 eV aufweist. Das Material kann insbesondere zur Bildung eines Gate verwendet werden.Technique has increased optical band gap> 4 eV. The material can be used in particular to form a gate.
Das Material umfasst vorteilhaft mindestens eine Ver- bindung aus jeweils der Gruppe der Scandate und Titana- te.The material advantageously comprises at least one compound from the group of scandates and titanates.
Durch Wahl mindestens einer Verbindung aus je einer dieser Gruppen wird besonders vorteilhaft bewirkt, dass das Material eine Dielektrizitätskonstante von etwa K > 40 durch die Verbindung ausgewählt, aus den Titanaten aufweist . Darüber hinaus weist das Material durch das Scandat eine optische Bandlücke > 4 eV auf.By selecting at least one compound from one of these groups, it is particularly advantageous that the material has a dielectric constant of about K> 40 selected from the titanates by the compound selected. In addition, the material has an optical bandgap> 4 eV due to the scandate.
Als Titanat kann BaTiO3 und/oder SrTiO3 vorgesehen sein. Es ist möglich, beide Verbindungen in dem erfin- dungsgemäßen Material neben einer weiteren Verbindung aus der Gruppe der Scandate vorzusehen.As titanate BaTiO 3 and / or SrTiO 3 may be provided. It is possible to provide both compounds in the material according to the invention in addition to another compound from the group of scandates.
Als Scandat kann z. B. GdScO3 vorgesehen sein. Weitere Seltenerde Elemente wie Pr, Nd, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb oder Lu an Stelle von Gd können ebenfalls vorgesehen werden.As a scandate z. B. GdScO 3 may be provided. Other rare earth elements such as Pr, Nd, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb or Lu instead of Gd may also be provided.
Sofern das Material zur Bildung des Gate eines Transistors verwendet wird, können die mindestens zwei Verbin- düngen des Materials homogen verteilt das Gate bilden. Mit diesem Begriff ist auch ein Gate umfasst, in dem die Verbindungen mehrfach alternierend auf dem Substrat zur Bildung des Gate aufgebracht vorliegen.If the material is used to form the gate of a transistor, the at least two compounds of the material can form the gate homogeneously distributed. This term also encompasses a gate in which the connections are applied repeatedly alternately on the substrate to form the gate.
Die einzelnen alternierenden Schichten weisen dabei be- sonders vorteilhaft jeweils eine Schichtdicke vonThe individual alternating layers particularly advantageously have a respective layer thickness of
< 3 nm auf. Bei mehrfacher Auftragung auf das Substrat wird somit ein Gate gebildet, dessen Dicke von der Anzahl der einzelnen Schichten und deren Schichtdicken abhängt. Durch die mehr- oder vielfach alternierenden Schichten liegen die mindestens zwei Verbindungen des erfindungsgemäßen Materials homogen verteilt bzw. durchmischt im Gate vor.<3 nm. With multiple application to the substrate thus a gate is formed, the thickness of which depends on the number of individual layers and their layer thicknesses. As a result of the multiple or multiple alternating layers, the at least two compounds of the material according to the invention are homogeneously distributed or mixed in the gate.
Es ist aber auch denkbar, die Verbindungen vorab zu homogenisieren und sodann durch geeignete Verfahren auf einem Substrat aufzubringen oder abzuscheiden.But it is also conceivable to homogenize the compounds in advance and then applied by suitable methods on a substrate or deposit.
Alternativ zu dieser Vorgehensweise können die mindestens zwei Verbindungen zur Erzeugung einer funktionellen Schicht auch jeweils nur einmal nacheinander auf einem geeigneten Substrat aufgebracht werden. In diesem Fall liegen die Verbindungen nicht homogen verteilt vor, bilden aber in Abhängigkeit von der gewählten Schichtdicke und der Verbindungen eine einzige funktionelle Schicht, wie z. B. ein Gate. Durch die offenbarten Vorgehensweisen wird demnach vorteilhaft bewirkt, dass auf dem Substrat aus z. B. Silizium, eine Schichtenfolge aus wenigstens zwei Verbindungen angeordnet ist, in der vorteilhaft die Eigen- Schäften einer großen Dielektrizitätskonstante mit K > 5 mit einer optischen Bandlücke > 4 eV verbunden sind.As an alternative to this procedure, the at least two compounds for producing a functional layer can also be applied only once in succession to a suitable substrate. In this case, the compounds are not homogeneously distributed, but depending on the selected layer thickness and the compounds form a single functional layer, such. A gate. By the disclosed procedures is thus advantageously effected that on the substrate of z. B. silicon, a layer sequence of at least two compounds is arranged in the advantageous the Eigen- shafts of a large dielectric constant with K> 5 are connected with an optical band gap> 4 eV.
Sofern als Titanat BaTiO3 und/oder SrTiO3 und als Scan- dat GdScO3 vorgesehen ist, wird vorteilhaft ein Gatematerial bereitgestellt, welches eine Dielektrizitäts- konstante -von wenigstens K = 60 und eine optische Bandlücke > 5,5 eV aufweist.If BaTiO 3 and / or SrTiO 3 and scan data GdScO 3 are provided as titanate, it is advantageous to provide a gate material which has a dielectric constant of at least K = 60 and an optical band gap of> 5.5 eV.
Besonders vorteilhaft ist durch das erfindungsgemäße Material bzw. Gateoxid ein Material mit thermodynami- scher Stabilität auf einem Halbleiter-Substrat, z. B. Silizium, und damit Kompatibilität mit der CMOS- Technologie gewährleistet.By the material or gate oxide according to the invention is a material with thermodynamic stability on a semiconductor substrate, for. As silicon, and thus ensures compatibility with the CMOS technology.
Ein Verfahren zur Herstellung eines Gateoxids sieht vor, auf einem Substrat aus insbesondere Silizium zunächst das Scandat und darauf das Titanat je mindestens einmal abzuscheiden. Dadurch wird vorteilhaft gewährleistet, dass keine Elemente des Titanats in das Silizium-Substrat diffundieren.A method for producing a gate oxide provides, on a substrate made of in particular silicon, first to deposit the scandate and then the titanate at least once. This advantageously ensures that no elements of the titanate diffuse into the silicon substrate.
Im Weiteren wird die Erfindung an Hand eines Ausführungsbeispiels und der beigefügten Figuren näher be- schrieben.The invention will be described in more detail below with reference to an exemplary embodiment and the attached figures.
Fig. 1 zeigt ein RBS-Spektrum einer 100 nm dicken Schicht, welche auf Silizium mittels gepulster Laserde- Position hergestellt wurde. Die Abscheidetemperatur betrug etwa 400 0C. Rutherfordrückstreuungsexperimente (RBS) ermöglichen die Analyse bezüglich der Elementverteilung und der Schichtdicke. Die Schicht besteht aus BaTiO3 und GdScO3. Die beiden Verbindungen wurden wechselseitig je 20 mal zur Bildung von GdScO3- und BaTiO3- Schichten auf das Siliziumsubstrat abgeschieden, so dass eine homogene Verteilung beider Verbindungen in der Schicht auf dem Substrat vorliegt. Die einzelnen Schichten sind dünner als 3 nm, um eine möglichst gute Durchmischung der Verbindungen zu gewährleisten.FIG. 1 shows an RBS spectrum of a 100 nm thick layer which is deposited on silicon by means of pulsed laser deposition. Position was made. The deposition temperature was about 400 ° C. Rutherford backscatter experiments (RBS) allow analysis of element distribution and layer thickness. The layer consists of BaTiO 3 and GdScO 3 . The two compounds were mutually deposited 20 times each on the silicon substrate to form GdScO 3 and BaTiO 3 layers, so that there is a homogeneous distribution of both compounds in the layer on the substrate. The individual layers are thinner than 3 nm in order to ensure the best possible mixing of the compounds.
Die Signale der einzelnen Elemente sind durch Symbole zugeordnet . Die Stöchiometrie dieser Schicht wurde über einen Vergleich mit einer Simulation, welche als durch- gezogene Kurve dargestellt ist, ermittelt. Es ergibt sich eine Zusammensetzung von (BaTiO3) 0.7(GdScO3) 0.3 •The signals of the individual elements are assigned by symbols. The stoichiometry of this layer was determined by comparison with a simulation, which is shown as a solid curve. The result is a composition of (BaTiO 3 ) 0. 7 (GdScO 3 ) 0.3.
Diese Schicht wurde nachfolgend mit Gold-Kontakten zur elektrischen Charakterisierung versehen. Eine Kapazitätsmessung wurde bei 1 MHz Betriebsfrequenz durchge- führt (Fig. 2) .This layer was subsequently provided with gold contacts for electrical characterization. A capacitance measurement was carried out at 1 MHz operating frequency (FIG. 2).
In Fig. 2 ist die gemessene Kapazität der Schicht gegen die angelegte Spannung aufgetragen. Bei negativen Spannungen von - 3 V lässt sich aus der Kapazität eine Dielektrizitätskonstante ermitteln. Auf Silizium erhält man eine Dielektrizitätskonstante von etwa K = 40, während man bei gut kristallin gewachsenem Material auf einem elektrisch leitfähigen Substrat SrTiO3(IOO) bedeckt mit dem Elektrodenmaterial SrRuO3 eine Dielektrizitätskonstante von etwa κ= 60 ermittelt. Als Substrat kann wie dargestellt Silizium vorgesehen sein. In diesem Fall, wird mit einer GdScO3-Schicht auf Silizium begonnen. Anschließend wird hierauf die Ba- TiO3-Schicht abgeschieden. Durch diese Maßnahme wird vorteilhaft bewirkt, dass keine Reaktion zwischen dem Titanat und dem Silizium erfolgt und die Bandlücke auf einem hohen Wert von 5,5 eV dauerhaft eingestellt wird.In Fig. 2, the measured capacitance of the layer is plotted against the applied voltage. With negative voltages of - 3 V, a dielectric constant can be determined from the capacitance. On silicon, a dielectric constant of about K = 40 is obtained, while a well-crystalline material grown on an electrically conductive substrate SrTiO 3 (IOO) covered with the electrode material SrRuO 3 a dielectric constant of about κ = 60 determined. As the substrate may be provided as shown silicon. In this case, starting with a GdScO 3 layer on silicon. Subsequently, the BaTiO 3 layer is deposited thereon. By this measure is advantageously effected that no reaction between the titanate and the silicon takes place and the band gap is set permanently to a high value of 5.5 eV.
Weiterhin wird vorteilhaft bewirkt, dass die Diffusion von Elementen aus der BaTiO3-Schicht in das Silizium- Substrat vollständig verhindert wird. Dadurch können im Gegensatz zum Stand der Technik Ti-haltige Materialien zur Bildung eines Gate eingesetzt werden.Furthermore, it is advantageously effected that the diffusion of elements of the BaTiO 3 layer into the silicon substrate is completely prevented. As a result, in contrast to the prior art, Ti-containing materials can be used to form a gate.
Um einen hysteresefreien Verlauf in der Kapazitätsmessung (Fig. 2) zu erhalten, wird ein Tempervorgang bei 500 0C in einer Forminggas Atmosphäre mit 80 % N2 und 20 % H2 durchgeführt. Die Schicht hält eine angelegte Spannung von 20 V aus, was einer Durchbruchfeidstärke von 2 MV/cm entspricht. Dies ist als unterer Wert der Durchbruchfeidstärke anzusehen.A hysteresis characteristic in the capacitance measurement (Fig. 2) to obtain an anneal at 500 0 C in a Forminggas atmosphere with 80% N 2 and 20% H 2 is carried out. The layer withstands an applied voltage of 20 V, which corresponds to a breakdown of 2 MV / cm. This is to be regarded as the lower value of the breakdown field strength.
Die Erfindung ist hierauf nicht beschränkt . Es ist möglich, die beiden Verbindungen nicht 3 Nanometer dünn und mehrfach alternierend wie oben beschrieben, sondern nacheinander und sofort in der erwünschten Schichtdicke auf dem Substrat anzuordnen, so dass das Gate aus einem Schichtsystem aus nur zwei Einzelschichten besteht.The invention is not limited thereto. It is possible to arrange the two compounds not 3 nanometers thin and multiply alternating as described above, but successively and immediately in the desired layer thickness on the substrate, so that the gate consists of a layer system of only two individual layers.
Auch dies führt dazu, ein Gate mit verbesserten Eigenschaften in Bezug auf die beiden Eigenschaften Dielektrizitätskonstante und optische Bandlücke zu bilden. Das Gate ist dann vorzugsweise durch ein unmittelbar auf dem Substrat angeordnetes Scandat und einem hierauf angeordneten Titanat gebildet. This, too, results in the formation of a gate with improved properties in terms of the two properties of dielectric constant and optical bandgap. The gate is then preferably by a direct formed on the substrate scandate and a titanate arranged thereon.

Claims

P a t e n t a n s p r ü c h e Patent claims
1. Material für ein Halbleiter-Bauelement, umfassend mindestens zwei Verbindungen, von denen die erste eine Dielektrizitätskonstante K > 5 und die zweite eine optische Bandlücke > 4 eV aufweist.1. A material for a semiconductor device, comprising at least two compounds, of which the first has a dielectric constant K> 5 and the second has an optical bandgap> 4 eV.
2. Material nach Anspruch 1, umfassend je mindestens eine Verbindung aus der Gruppe der Scandate und Titanate.2. Material according to claim 1, comprising in each case at least one compound from the group of scandates and titanates.
3. Material nach einem der vorhergehenden Ansprüche, umfassend BaTiO3 und/oder SrTiO3.3. Material according to one of the preceding claims, comprising BaTiO 3 and / or SrTiO 3 .
4. Material nach einem der vorhergehenden Ansprüche, umfassend GdScO3.4. Material according to one of the preceding claims, comprising GdScO 3 .
5. Halbleiter-Bauelement, umfassend ein Material nach einem der vorhergehenden Ansprüche, in dem die mindestens zwei Verbindungen ein Gate mit einer Dielektrizitätskonstante K > 5 und einer optischen Bandlücke > 4 eV bilden.5. A semiconductor device comprising a material according to any one of the preceding claims, in which the at least two connections form a gate having a dielectric constant K> 5 and an optical bandgap> 4 eV.
6. Halbleiter-Bauelement, nach vorhergehendem Anspruch, mit homogener Verteilung der Verbindungen im Gate.6. Semiconductor component, according to the preceding claim, with homogeneous distribution of the compounds in the gate.
7. Halbleiter-Bauelement nach einem der vorhergehenden Ansprüche 5 bis 6, mit Schichtdicken < 3 Nanometer aus den Verbindun- gen. 7. Semiconductor component according to one of the preceding claims 5 to 6, with layer thicknesses <3 nanometers from the compounds gene.
8. Halbleiter-Bauelement nach einem der vorhergehenden Ansprüche 5 bis 7, bei dem zur Bildung eines Gate auf einem Substrat zunächst ein Scandat und hierauf ein Titanat mindestens einmal alternierend angeordnet vorliegt . 8. The semiconductor device according to any one of the preceding claims 5 to 7, wherein for forming a gate on a substrate, first a scandate and then a titanate is present alternately at least once.
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