WO2005114716A3 - Process for metallic contamination reduction in silicon wafers - Google Patents
Process for metallic contamination reduction in silicon wafers Download PDFInfo
- Publication number
- WO2005114716A3 WO2005114716A3 PCT/US2005/014529 US2005014529W WO2005114716A3 WO 2005114716 A3 WO2005114716 A3 WO 2005114716A3 US 2005014529 W US2005014529 W US 2005014529W WO 2005114716 A3 WO2005114716 A3 WO 2005114716A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- silicon wafer
- interior
- contaminant
- layer
- silicon wafers
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007511422A JP5238251B2 (en) | 2004-05-07 | 2005-04-26 | Method for reducing metal contamination in silicon wafers |
EP05739906A EP1743364B1 (en) | 2004-05-07 | 2005-04-26 | Process for metallic contamination reduction in silicon wafers |
KR1020067025661A KR101165108B1 (en) | 2004-05-07 | 2005-04-26 | Process for metallic contamination reduction in silicon wafers |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/840,854 | 2004-05-07 | ||
US10/840,854 US7084048B2 (en) | 2004-05-07 | 2004-05-07 | Process for metallic contamination reduction in silicon wafers |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005114716A2 WO2005114716A2 (en) | 2005-12-01 |
WO2005114716A3 true WO2005114716A3 (en) | 2006-02-09 |
Family
ID=34967282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/014529 WO2005114716A2 (en) | 2004-05-07 | 2005-04-26 | Process for metallic contamination reduction in silicon wafers |
Country Status (7)
Country | Link |
---|---|
US (1) | US7084048B2 (en) |
EP (2) | EP2259291B1 (en) |
JP (2) | JP5238251B2 (en) |
KR (1) | KR20120040756A (en) |
CN (1) | CN100466200C (en) |
TW (1) | TWI393168B (en) |
WO (1) | WO2005114716A2 (en) |
Families Citing this family (33)
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---|---|---|---|---|
JP2005333090A (en) * | 2004-05-21 | 2005-12-02 | Sumco Corp | P-type silicon wafer and method for heat-treatment thereof |
JP2006040972A (en) * | 2004-07-22 | 2006-02-09 | Shin Etsu Handotai Co Ltd | Silicon epitaxial wafer and its manufacturing method |
JP2007194232A (en) * | 2006-01-17 | 2007-08-02 | Shin Etsu Handotai Co Ltd | Process for producing silicon single crystal wafer |
US20070295357A1 (en) * | 2006-06-27 | 2007-12-27 | Lovejoy Michael L | Removing metal using an oxidizing chemistry |
US7968148B2 (en) * | 2006-09-15 | 2011-06-28 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit system with clean surfaces |
JP5350623B2 (en) * | 2006-12-28 | 2013-11-27 | グローバルウェーハズ・ジャパン株式会社 | Heat treatment method for silicon wafer |
US20080171449A1 (en) * | 2007-01-15 | 2008-07-17 | Chao-Ching Hsieh | Method for cleaning salicide |
US7888142B2 (en) * | 2007-09-28 | 2011-02-15 | International Business Machines Corporation | Copper contamination detection method and system for monitoring copper contamination |
US7957917B2 (en) * | 2007-09-28 | 2011-06-07 | International Business Machines Corporation | Copper contamination detection method and system for monitoring copper contamination |
US20090211623A1 (en) * | 2008-02-25 | 2009-08-27 | Suniva, Inc. | Solar module with solar cell having crystalline silicon p-n homojunction and amorphous silicon heterojunctions for surface passivation |
US8076175B2 (en) * | 2008-02-25 | 2011-12-13 | Suniva, Inc. | Method for making solar cell having crystalline silicon P-N homojunction and amorphous silicon heterojunctions for surface passivation |
JP5276863B2 (en) * | 2008-03-21 | 2013-08-28 | グローバルウェーハズ・ジャパン株式会社 | Silicon wafer |
JP2009231429A (en) * | 2008-03-21 | 2009-10-08 | Covalent Materials Corp | Method of manufacturing silicon wafer |
JP5134586B2 (en) * | 2009-05-18 | 2013-01-30 | 濱田重工株式会社 | Silicon wafer recycling method |
JP5544859B2 (en) * | 2009-12-15 | 2014-07-09 | 信越半導体株式会社 | Manufacturing method of silicon epitaxial wafer |
US20110146717A1 (en) * | 2009-12-23 | 2011-06-23 | Memc Electronic Materials, Inc. | Systems And Methods For Analysis of Water and Substrates Rinsed in Water |
DE112012000576B4 (en) * | 2011-01-26 | 2023-06-07 | Sumco Corp. | Method of manufacturing a solar cell wafer, a solar cell, and a solar cell module |
WO2012102755A1 (en) * | 2011-01-28 | 2012-08-02 | Applied Materials, Inc. | Carbon addition for low resistivity in situ doped silicon epitaxy |
US8796116B2 (en) * | 2011-01-31 | 2014-08-05 | Sunedison Semiconductor Limited | Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods |
GB201105953D0 (en) * | 2011-04-07 | 2011-05-18 | Metryx Ltd | Measurement apparatus and method |
DE102011016366B4 (en) * | 2011-04-07 | 2018-09-06 | Nasp Iii/V Gmbh | III / V-Si template, its use and process for its preparation |
US8969119B2 (en) * | 2011-06-03 | 2015-03-03 | Memc Singapore Pte. Ltd. (Uen200614794D) | Processes for suppressing minority carrier lifetime degradation in silicon wafers |
JP6065366B2 (en) * | 2012-01-30 | 2017-01-25 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
CN102766908B (en) * | 2012-07-25 | 2016-02-24 | 苏州阿特斯阳光电力科技有限公司 | The Boron diffusion method of crystal silicon solar energy battery |
CN104733337B (en) * | 2013-12-23 | 2017-11-07 | 有研半导体材料有限公司 | A kind of method of testing for being used to analyze metal contamination in wafer bulk |
CN103871871A (en) * | 2014-02-21 | 2014-06-18 | 上海华力微电子有限公司 | Method for removing metallic purities of silicon chip |
CN105869988B (en) * | 2015-01-20 | 2019-09-24 | 无锡华润上华科技有限公司 | A kind of manufacturing method of semiconductor devices |
CN109872941A (en) * | 2017-12-05 | 2019-06-11 | 上海新昇半导体科技有限公司 | A kind of processing method of silicon wafer |
CN111886213B (en) * | 2018-03-22 | 2022-12-09 | 住友大阪水泥股份有限公司 | Composite sintered body, electrostatic chuck member, electrostatic chuck device, and method for producing composite sintered body |
DE102020107236B4 (en) * | 2019-09-30 | 2023-05-04 | Taiwan Semiconductor Manufacturing Co. Ltd. | METHOD OF MAKING A SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE |
CN112539982B (en) * | 2020-12-03 | 2023-11-03 | 西安奕斯伟材料科技股份有限公司 | Manufacturing method of silicon wafer sample and silicon wafer sample |
CN112683988B (en) * | 2020-12-28 | 2023-06-02 | 上海新昇半导体科技有限公司 | Method for detecting metal impurities in wafer |
CN113506733A (en) * | 2021-06-22 | 2021-10-15 | 华虹半导体(无锡)有限公司 | Method for reducing metal impurities of silicon wafer |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6055629A (en) * | 1983-09-07 | 1985-03-30 | Fujitsu Ltd | Preparation of miller wafer |
JPS63129633A (en) * | 1986-11-20 | 1988-06-02 | Fujitsu Ltd | Surface treatment for semiconductor |
US6100167A (en) * | 1997-05-29 | 2000-08-08 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron doped silicon wafers |
US20030104680A1 (en) * | 2001-11-13 | 2003-06-05 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron-doped silicon wafers |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6055629B2 (en) | 1983-03-15 | 1985-12-05 | グンゼ株式会社 | Device for turning over tubular clothing articles |
JPH01244621A (en) * | 1988-03-25 | 1989-09-29 | Shin Etsu Handotai Co Ltd | Method of cleaning surface of silicon single crystal substrate |
ES2084606T3 (en) * | 1988-12-21 | 1996-05-16 | At & T Corp | MODIFIED GROWTH THERMAL OXIDATION PROCEDURE FOR THIN OXIDES. |
DE3939661A1 (en) | 1989-11-30 | 1991-06-13 | Wacker Chemitronic | Controlling copper incorporation into silicon wafers - during polishing by adding complexing ligands |
JPH05275436A (en) * | 1992-03-24 | 1993-10-22 | Shin Etsu Handotai Co Ltd | Heat treatment of silicon wafer |
JP3095519B2 (en) * | 1992-04-22 | 2000-10-03 | 株式会社東芝 | Method for manufacturing semiconductor device |
US5869405A (en) * | 1996-01-03 | 1999-02-09 | Micron Technology, Inc. | In situ rapid thermal etch and rapid thermal oxidation |
US6482269B1 (en) * | 1997-05-29 | 2002-11-19 | Memc Electronic Materials, Inc. | Process for the removal of copper and other metallic impurities from silicon |
JP3211747B2 (en) * | 1997-09-30 | 2001-09-25 | 日本電気株式会社 | Method for manufacturing semiconductor device |
KR20060093740A (en) * | 1998-01-09 | 2006-08-25 | 에이에스엠 아메리카, 인코포레이티드 | In situ growth of oxide and silicon layers |
JP3173655B2 (en) * | 1999-01-18 | 2001-06-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JP2000294549A (en) * | 1999-02-02 | 2000-10-20 | Nec Corp | Semiconductor device and manufacture of the same |
JP3601383B2 (en) * | 1999-11-25 | 2004-12-15 | 信越半導体株式会社 | Epitaxial growth silicon wafer, epitaxial wafer and manufacturing method thereof |
US6599815B1 (en) * | 2000-06-30 | 2003-07-29 | Memc Electronic Materials, Inc. | Method and apparatus for forming a silicon wafer with a denuded zone |
-
2004
- 2004-05-07 US US10/840,854 patent/US7084048B2/en active Active
-
2005
- 2005-04-26 CN CNB2005800228233A patent/CN100466200C/en not_active Expired - Fee Related
- 2005-04-26 EP EP10179629A patent/EP2259291B1/en not_active Expired - Fee Related
- 2005-04-26 EP EP05739906A patent/EP1743364B1/en not_active Expired - Fee Related
- 2005-04-26 JP JP2007511422A patent/JP5238251B2/en not_active Expired - Fee Related
- 2005-04-26 KR KR1020127009189A patent/KR20120040756A/en not_active Application Discontinuation
- 2005-04-26 WO PCT/US2005/014529 patent/WO2005114716A2/en active Application Filing
- 2005-05-06 TW TW094114777A patent/TWI393168B/en not_active IP Right Cessation
-
2012
- 2012-11-14 JP JP2012250402A patent/JP2013058784A/en not_active Ceased
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6055629A (en) * | 1983-09-07 | 1985-03-30 | Fujitsu Ltd | Preparation of miller wafer |
JPS63129633A (en) * | 1986-11-20 | 1988-06-02 | Fujitsu Ltd | Surface treatment for semiconductor |
US6100167A (en) * | 1997-05-29 | 2000-08-08 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron doped silicon wafers |
US20030104680A1 (en) * | 2001-11-13 | 2003-06-05 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron-doped silicon wafers |
Non-Patent Citations (6)
Title |
---|
BAI P ET AL: "INTRINSIC CU GETTERING AT A THERMALLY GROWN SIO2/SI INTERFACE", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 68, no. 7, 1 October 1990 (1990-10-01), pages 3313 - 3316, XP001108893, ISSN: 0021-8979 * |
GRAEF D ET AL: "IMPROVEMENT OF CZOCHRALSKI SILICON WAFERS BY HIGH-TEMPERATURE ANNEALING", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, vol. 142, no. 9, September 1995 (1995-09-01), pages 3189 - 3192, XP002045230, ISSN: 0013-4651 * |
HOZAWA K ET AL: "Copper distribution near a SiO2/Si interface under low-temperature annealing", JAPANESE JOURNAL OF APPLIED PHYSICS, PART 1 (REGULAR PAPERS, SHORT NOTES & REVIEW PAPERS) JAPAN SOC. APPL. PHYS JAPAN, vol. 41, no. 10, October 2002 (2002-10-01), pages 5887 - 5893, XP002355833, ISSN: 0021-4922 * |
PATENT ABSTRACTS OF JAPAN vol. 009, no. 185 (E - 332) 31 July 1985 (1985-07-31) * |
PATENT ABSTRACTS OF JAPAN vol. 012, no. 385 (E - 668) 14 October 1988 (1988-10-14) * |
TAMATSUKA M ET AL: "HIGH PERFORMANCE SILICON WAFER WITH WIDE GROWN-IN VOID FREE ZONE AND HIGH DENSITY INTERNAL GETTERING SITE ACHIEVED VIA RAPID CRYSTALGROWTH WITH NITROGEN DOPING AND HIGH TEMPERATURE HYDROGEN AND/OR ARGON ANNEALING", ELECTROCHEMICAL SOCIETY PROCEEDINGS, ELECTROCHEMICAL SOCIETY, PENNINGTON, NJ, US, vol. 99, no. 1, May 1999 (1999-05-01), pages 456 - 467, XP002934357, ISSN: 0161-6374 * |
Also Published As
Publication number | Publication date |
---|---|
WO2005114716A2 (en) | 2005-12-01 |
JP2013058784A (en) | 2013-03-28 |
CN100466200C (en) | 2009-03-04 |
CN1981369A (en) | 2007-06-13 |
TWI393168B (en) | 2013-04-11 |
US7084048B2 (en) | 2006-08-01 |
EP1743364B1 (en) | 2011-12-28 |
US20050250297A1 (en) | 2005-11-10 |
TW200603224A (en) | 2006-01-16 |
EP2259291B1 (en) | 2012-03-14 |
EP1743364A2 (en) | 2007-01-17 |
EP2259291A2 (en) | 2010-12-08 |
JP5238251B2 (en) | 2013-07-17 |
JP2007536738A (en) | 2007-12-13 |
KR20120040756A (en) | 2012-04-27 |
EP2259291A3 (en) | 2011-02-23 |
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