WO2005098929A3 - Method of forming sidewall spacers - Google Patents

Method of forming sidewall spacers Download PDF

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Publication number
WO2005098929A3
WO2005098929A3 PCT/US2005/010475 US2005010475W WO2005098929A3 WO 2005098929 A3 WO2005098929 A3 WO 2005098929A3 US 2005010475 W US2005010475 W US 2005010475W WO 2005098929 A3 WO2005098929 A3 WO 2005098929A3
Authority
WO
WIPO (PCT)
Prior art keywords
feature
sidewall spacers
protective layers
etchant
forming sidewall
Prior art date
Application number
PCT/US2005/010475
Other languages
French (fr)
Other versions
WO2005098929A2 (en
Inventor
Markus Lenski
Falk Graetsch
Carsten Reichel
Christoph Schwan
Helmut Bierstedt
Thorsten Kammler
Martin Mazur
Original Assignee
Advanced Micro Devices Inc
Markus Lenski
Falk Graetsch
Carsten Reichel
Christoph Schwan
Helmut Bierstedt
Thorsten Kammler
Martin Mazur
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102004015864A external-priority patent/DE102004015864B4/en
Application filed by Advanced Micro Devices Inc, Markus Lenski, Falk Graetsch, Carsten Reichel, Christoph Schwan, Helmut Bierstedt, Thorsten Kammler, Martin Mazur filed Critical Advanced Micro Devices Inc
Priority to GB0619080A priority Critical patent/GB2427076A/en
Priority to JP2007506459A priority patent/JP2007532001A/en
Publication of WO2005098929A2 publication Critical patent/WO2005098929A2/en
Publication of WO2005098929A3 publication Critical patent/WO2005098929A3/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

The present invention allows the formation of sidewall spacers (217,218) adjacent a feature (206) on a substrate (201) without there being an undesirable erosion of the feature. The feature (206) is covered by one or more protective layers (220,207). A layer of a spacer material (211) is deposited over the feature (206) and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers (220, 207) are substantially not affected by the etchant. Thus, the one or more protective layers (220, 207) protect the feature from being exposed to the etchant.
PCT/US2005/010475 2004-03-31 2005-03-29 Method of forming sidewall spacers WO2005098929A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0619080A GB2427076A (en) 2004-03-31 2005-03-29 Method of forming sidewall spacers
JP2007506459A JP2007532001A (en) 2004-03-31 2005-03-29 Method for forming sidewall spacer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102004015864.9 2004-03-31
DE102004015864A DE102004015864B4 (en) 2004-03-31 2004-03-31 Method for forming sidewall spacers
US11/039,084 2005-01-19
US11/039,084 US20050233532A1 (en) 2004-03-31 2005-01-19 Method of forming sidewall spacers

Publications (2)

Publication Number Publication Date
WO2005098929A2 WO2005098929A2 (en) 2005-10-20
WO2005098929A3 true WO2005098929A3 (en) 2005-12-15

Family

ID=34965334

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/010475 WO2005098929A2 (en) 2004-03-31 2005-03-29 Method of forming sidewall spacers

Country Status (4)

Country Link
JP (1) JP2007532001A (en)
KR (1) KR20060134190A (en)
GB (1) GB2427076A (en)
WO (1) WO2005098929A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100847831B1 (en) * 2006-12-29 2008-07-23 동부일렉트로닉스 주식회사 Method of Manufacturing Semiconductor Device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013569A (en) * 1997-07-07 2000-01-11 United Microelectronics Corp. One step salicide process without bridging
US6049114A (en) * 1998-07-20 2000-04-11 Motorola, Inc. Semiconductor device having a metal containing layer overlying a gate dielectric
US6063704A (en) * 1999-08-02 2000-05-16 National Semiconductor Corporation Process for incorporating silicon oxynitride DARC layer into formation of silicide polysilicon contact
US6200886B1 (en) * 1999-10-28 2001-03-13 United Silicon Incorporated Fabricating process for polysilicon gate
US6465853B1 (en) * 2001-05-08 2002-10-15 Motorola, Inc. Method for making semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224363A (en) * 1987-03-13 1988-09-19 Nec Corp Manufacture of semiconductor integrated circuit
JPH0779101B2 (en) * 1989-05-24 1995-08-23 株式会社東芝 Manufacturing method of semiconductor device
JPH03101238A (en) * 1989-09-14 1991-04-26 Toshiba Corp Mos type semiconductor device and its manufacture
JPH06177148A (en) * 1992-12-08 1994-06-24 Sony Corp Fabrication of insulated gate field-effect transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013569A (en) * 1997-07-07 2000-01-11 United Microelectronics Corp. One step salicide process without bridging
US6049114A (en) * 1998-07-20 2000-04-11 Motorola, Inc. Semiconductor device having a metal containing layer overlying a gate dielectric
US6063704A (en) * 1999-08-02 2000-05-16 National Semiconductor Corporation Process for incorporating silicon oxynitride DARC layer into formation of silicide polysilicon contact
US6200886B1 (en) * 1999-10-28 2001-03-13 United Silicon Incorporated Fabricating process for polysilicon gate
US6465853B1 (en) * 2001-05-08 2002-10-15 Motorola, Inc. Method for making semiconductor device

Also Published As

Publication number Publication date
KR20060134190A (en) 2006-12-27
GB0619080D0 (en) 2006-11-08
WO2005098929A2 (en) 2005-10-20
JP2007532001A (en) 2007-11-08
GB2427076A (en) 2006-12-13

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