WO2005067221A1 - Serial ethernet device-to-device interconnection - Google Patents
Serial ethernet device-to-device interconnection Download PDFInfo
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- WO2005067221A1 WO2005067221A1 PCT/US2004/041105 US2004041105W WO2005067221A1 WO 2005067221 A1 WO2005067221 A1 WO 2005067221A1 US 2004041105 W US2004041105 W US 2004041105W WO 2005067221 A1 WO2005067221 A1 WO 2005067221A1
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- WIPO (PCT)
- Prior art keywords
- code groups
- control message
- data
- code
- differential pair
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/4013—Management of data rate on the bus
- H04L12/40136—Nodes adapting their rate to the physical link properties
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
Definitions
- the subject matter disclosed herein relates to devices capable of transmitting or receiving data in device-to-device interconnections.
- DDI device-to-device interconnection
- PCB printed circuit board
- DDI device-to-device interconnection
- a device may be coupled to a DDI by solder bonding or a device socket secured to the PCB.
- Cisco Systems has promoted a Serial Gigabit Media Independent Interface
- SGMII Gigabit Attachment Unit
- XAUI Gigabit Media Independent Interface
- XGMII 10 Gigabit Media Independent Interface
- the XAUI format may be used in transmitting data over an Inf ⁇ niband 4x cable as described in the proposed 10GBASE-CX4 standard presently being explored by the IEEE P802.3ak working group.
- FIG. 1 shows a schematic diagram of devices coupled by a device-to- device interconnection (DDI) according to an embodiment of the present invention.
- DCI device-to- device interconnection
- a "device-to-device interconnection" as referred to herein relates to a data link to transmit data between devices.
- a DDI may be formed by conductive traces formed on a circuit board between device sockets to receive devices.
- a DDI may traverse multiple devices coupled between two devices over a backplane and comprise conductive traces coupling the devices to one another.
- a DDI may comprise a cable coupled between two connectors at opposite ends of the cable. Each connector may then transmit data between the cable and a device coupled to the connector by conductive traces.
- a "serial data signal" as referred to herein relates to a signal comprising information encoded into a series of symbols.
- a serial data signal may comprise a series of symbols transmitted in a transmission medium where each symbol is transmitted in a symbol period.
- a "differential pair signal" as referred to herein relates to a pair of synchronized signals to transmit encoded data to a destination.
- differential pair signal may transmit a serial data signal comprising symbols to be decoded for data recovery at a destination.
- Such a differential pair signal may transmit each symbol as a voltage on each of two transmission media.
- An "8B/10B encoding scheme" as referred to herein relates to a process by which eight-bit data bytes may be encoded into ten-bit "code groups” (e.g., 8B/10B code groups), or a process by which ten-bit code groups may be decoded to eight-bit data bytes according to a predetermined "8B/10B code group mapping.”
- An "8B/10B encoder” as referred to herein relates to logic to encode an eight-bit data byte to a ten-bit code group
- an “8B/10B decoder” as referred to herein relates to logic to decode an eight-bit byte from a ten-bit code group.
- Transmission medium as referred to herein relates to a medium capable of transmitting data from a source to a destination.
- a transmission medium may comprise cabling (e.g., coaxial, unshielded twisted wire pair or fiber optic cabling), printed circuit board traces or a wireless transmission medium.
- cabling e.g., coaxial, unshielded twisted wire pair or fiber optic cabling
- printed circuit board traces e.g., a wireless transmission medium.
- An "Ethernet data frame" as referred to herein relates to a format for transmitting data in a data link according to a protocol provided in versions of IEEE Std. 802.3 (e.g., to transmit data frames according to 10BASE-X, 100BASE-X, 1000BASE-X or 10GBASE-X protocols).
- An Ethernet data frame may include, for example, a header portion including a media access control (MAC) address and a payload portion including content data to be processed at a destination.
- MAC media access control
- this is merely an example of an Ethernet data frame and embodiments of the present invention are not limited in these respects.
- An Ethernet data frame may be used to transmit content data between devices or nodes in a data channel.
- a "control message" as referred to herein relates to messages that may be transmitted between devices or nodes other than content data to notify a node or device receiving the control message of events, status, requests or configuration commands.
- a control message may be transmitted in a communication channel which is distinct from a data channel as an "out-of-band” message.
- a control message may be inserted or interleaved among content data transmitted in a data channel as an "in-band” message.
- an embodiment of the present invention relates to the transmission of 8B/10B code groups including Ethernet data frames in a DDI. Control messages may be inserted among the 8B/10B code groups for transmission to a destination device.
- FIG 1 shows a schematic diagram of a system 10 for transmitting data to and receiving data from a node 34 through a transmission medium 32.
- the transmission medium 32 may comprise any one of several mediums suitable for transmitting data in a data link such as, for example, a cable (e.g., coaxial, unshielded twisted wire pair or fiber optic) or a wireless transmission medium.
- the transmission medium 32 may transmit data between the node 34 and a data transceiver 12 in Ethernet data frames according to versions of IEEE Std. 802.3 (e.g., 10BASE-X, 100BASE-X, lOOOBASE-X or 10GBASE- X).
- the data transceiver 12 may be coupled to a controller 18 by a DDI.
- the DDI may transmit a first differential pair signal 14 from the data transceiver 12 to the controller 18 and transmit a second differential pair signal 16 from the controller 18 to the data transceiver 12.
- each of the first and second differential pair signals 14 and 16 may be transmitted in a single pair of conductive traces (e.g., formed in a printed circuit board, not shown) in the DDI coupled between the data transceiver 12 and the controller 18.
- components containing the data transceiver 12 and the controller 18 may be coupled to one another by four device pins (not shown) on each component (where each component comprises two device pins to transmit or receive differential pair signal 14 and two devices pins to transmit or receive differential pair signal 16).
- the device pins may be coupled to the DDI by solder bonding or device sockets which are mounted to the DDI and adapted to receive the components containing the data transceiver 12 and controller 18.
- solder bonding or device sockets which are mounted to the DDI and adapted to receive the components containing the data transceiver 12 and controller 18.
- the data transceiver 12 may comprise a physical media dependent (PMD) section (not shown) for transmitting data to and receiving data from the transmission medium 32 according to a physical layer data transmission protocol such as Gigabit Ethernet over unshielded twisted wire pair cabling (or 1000BASE-T) or 10 Gigabit Ethernet over unshielded twisted wire pair cabling (or 10GBASE-T).
- PMD physical media dependent
- the PMD section may comprise circuitry to detect individual bits in Ethernet data frames received from the transmission medium 32 (e.g., clock and data recovery circuitry) and circuitry to transmit individual bits in Ethernet data frames transmitted to the node 34.
- the data transceiver 12 may also comprise circuitry (not shown) to encode eight bit bytes making up Ethernet data frames received from the transmission medium 32 (via the PMD section) into ten bit code groups for transmission to the controller 18 on differential pair signal 14 as a serial data signal.
- the data transceiver 12 may encode the eight bit bytes into ten bit code groups (e.g., 8B/10B code groups) as described in IEEE 802.3 - 2002, Clause 36.
- the data transceiver 12 may comprise circuitry to decode 8B/10B code groups received from the differential pair signal 16 into eight bit bytes for transmission in the transmission medium 32 via the PMD section.
- the controller 18 may comprise a deserializer 20 to recover 8B/10B code groups from the differential pair signal 14 and a serializer 22 to transmit 8B/10B code groups to the data transceiver 12 as a serial data signal over the differential pair signal 16.
- a physical coding sublayer (PCS) section 18 may decode the 8B/10B code groups recovered from the deserializer 20 to reconstruct eight-bit bytes of Ethernet data frames received at the data transceiver 12 from node 34.
- the PCS section 18 may encode eight-bit bytes of Ethernet data frames into 8B/10B code groups for the serializer
- the PCS section 24 may be coupled to a media access control (MAC) receive block 26 to provide Ethernet data frames reassembled from eight-bit bytes decoded from 8B/10B code groups.
- the PCS section 24 may also be coupled a MAC transmit block 28 to receive Ethernet data frames for transmission through the transmission medium 32.
- the MAC receive block 26 and MAC transmit block 28 may be coupled at a signaling interface providing a Gigabit Media Independent Interface (GMII) as defined in IEEE Std. 802.3 - 2000, Clause 36.
- GMII Gigabit Media Independent Interface
- the differential pair signals 14 and 16 may transmit Ethernet data frames as
- Such code groups used for the transmission of Ethernet data frames may include, for example, ordered code group sets for establishing bit and code group synchronization, data code groups, idle code group (III), start of packet delimiter code group (/S/), end of packet delimiter code group (/T ), carrier extend code group (/R/) and error propagation code group (/V/).
- the controller 18 and data transceiver 12 may transmit in-band control messages in the differential pair signals 14 and 16 along with encoded portions of Ethernet data frames.
- Such in-band control messages may be transmitted as 8B/10B code groups inserted among 8B/10B code groups transmitting encoded eight-bit bytes of Ethernet data frames.
- control messages which would otherwise be transmitted in a management data input/output (MDIO) interface (either at the data transceiver 12 or controller 18) may be transmitted as the inserted 8B/10B code groups.
- MDIO management data input/output
- the code group sequence: /T/R/K28.5/Dx.y/(six byte control message)/K28.5/Dx.y/ may be substituted for the typical code group sequence following an Ethernet data frame: /T/R/I 28.5/Dx.y/K28.5/Dx.y/ K28.5/Dx.y/ K28.5/Dx.y/ K28.5/Dx.y/ K28.5/Dx.y/ K28.5/Dx.y/.
- a six byte idle code group sequence "/K28.5/Dx.y/ K28.5/Dx.y/ K28.5/Dx.y/” in the typical code group sequence may be substituted with six bytes forming the control message.
- a first byte of the six byte control message may include a special symbol to indicate the presence of a control message (e.g., to access MDIO registers at the destination device) such as "/K28.1/" including a comma.
- a second byte may specify read or write access to specific MDIO registers.
- Third and fourth bytes may specify information to be written to an MDIO register and a fifth byte may be reserved.
- a sixth byte may include a cyclic redundancy code for error correction (excluding the special symbol /K28.1/). Similar six byte packets may be formatted for read access acknowledge/response control messages or write access acknowledge control messages. However, these are merely an example of how a control message may be inserted among 8b/10B code groups for transmitting Ethernet data frames and embodiments of the present invention are not limited in these respects.
- the PCS section 24 may comprise circuitry
- the circuitry 30 may encode control messages for transmission to the data transceiver 12 as 8B/10B code groups (e.g., inserted among 8B/10B code groups on differential pair signal 16 containing Ethernet data frames) according to the predetermined mapping of 8B/10 code groups to control messages.
- the data transceiver 12 may also comprise circuitry (not shown) to detect
- the data transceiver 12 may also comprise circuitry to encode control messages for transmission to the data controllerl8 as 8B/10B code groups (e.g., inserted among 8B/10B code groups on differential pair signal 14 containing Ethernet data frames) according to the predetermined mapping of 8B/10 code groups to control messages.
- the data transceiver 12 and controller 18 may support multiple Ethernet protocols at different bit rates including 10BASE-X (at
- the data transceiver 12 and controller 18 may support an autonegotiation feature to select a data transmission protocol for use between the data transceiver 12 and the node 34 for transmitting Ethernet data frames in the transmission medium 32 as provided in IEEE Std. 802.3 - 2000, Clause 28. Accordingly, the data transceiver 12 may be capable of negotiating with the node 34 to select the data transmission protocol having the highest data rate from among common data transmission protocols (e.g., 10BASE-X, 100BASE-X
- the controller 18 may communicate with the node 34 to identify and negotiate additional capabilities (e.g., abilities to transmit in full or half duplex modes) while communicating according to the selected data transmission protocol as provided in IEEE Std. 802.3 - 2000, Clause 37.
- additional capabilities e.g., abilities to transmit in full or half duplex modes
- control messages that may be transmitted from the data transceiver 12 to the controller 18 in 8B/10B code groups over the differential pair signal 14
- the data transceiver 12 may transmit one or more control messages to the controller 18 indicating a data transmission protocol or data rate selected through autonegotiation, or status of the data link between the data transceiver 12 and the node 34 (e.g., active versus inactive, connected versus unconnected, changes in data transmission mode from lOGbps to lGbps, etc.).
- the controller 18 my respond by transmitting an acknowledgement in one or more 8B/10B code groups over the differential pair signal 16.
- these are merely examples of control messages that may be transmitted from a data transceiver to a controller in 8B/10B code groups over a differential pair signal and embodiments of the present invention are not limited in these respects.
- the data transceiver 12 and controller 18 may configure the data rate of the differential pair signals 14 and 16 according to the selected data rate. For example, if the data rate selected through autonegotiation is 1000 Mbps (e.g., from a selected 1000BASE-
- the data transceiver 12 and controller 18 may configure the differential pair signals 14 and 16 to transmit at a data rate of 1.25 Gbps. (allowing 250 Mbps of overhead for transmitting 8B/10B code groups encoded from eight-bit bytes of Ethernet data frames). For a selected data rate of 10 or 100 Mbps, the data transceiver 12 and controller 18 may transmit duplicate Ethernet data frames or code groups in differential pair signals 14 and 16 transmitting at 1.25 Gbps. Alternatively, if the data rate selected through autonegotiation is 10 or 100 Mbps (e.g., from a selected 10BASE-X or 100BASE-X protocol), the data transceiver 12 and controller 18 may configure the differential pair signals 14 and 16 at a data rate of 125 Mbps.
- the data rate selected through autonegotiation is 10 or 100 Mbps (e.g., from a selected 10BASE-X or 100BASE-X protocol)
- the data transceiver 12 and controller 18 may configure the differential pair signals 14 and 16 at a data rate of 125 Mbps
- the controller 18 may be included as part of a computing platform and coupled to a host processing system (e.g., including a host processor, I/O core logic and system memory) hosting an operating system and/or application programs.
- a host processing system e.g., including a host processor, I/O core logic and system memory
- the computing platform may define certain states and events such as, for example, a software reset event, power states (e.g., full power, standby, snooze, etc.) and events indicating a transition between power states.
- control messages that may be transmitted from the controller 18 to the data transceiver 12 in 8B/10B code groups over the differential pair signal 16
- the controller 18 may transmit control messages indicating a change in the power state of the computing platform (e.g., change from full power to standby or snooze, or from standby or snooze to resume operation full power) enabling the data transceiver to operate at low voltage when the computing platform is not operating at a full power state.
- control messages indicating a change in the power state of the computing platform (e.g., change from full power to standby or snooze, or from standby or snooze to resume operation full power) enabling the data transceiver to operate at low voltage when the computing platform is not operating at a full power state.
- these are merely examples of control messages that may be transmitted from a controller to a data transceiver in 8B/10B code groups over a differential pair signal and embodiments of the present invention are not limited in these respects.
- the controller 18 may perform code group and bit synchronization in response to the differential pair signal 14 to ensure the alignment of 8B/10B code groups from the data transceiver 12.
- the data transceiver 12 may also perform code group and bit synchronization in response to the differential pair signal 16 to ensure alignment of 8B/10B code groups from the controller 18.
- the controller 18 and data transceiver 12 may perform this code group and bit synchronization as provided in IEEE Std. 802.3 - 2000, Clauses 36.2.4 and 36.2.5.2.6 to ensure synchronization of multi-code group ordered sets to code group boundaries.
- IEEE Std. 802.3 - 2000 Clauses 36.2.4 and 36.2.5.2.6
- the controller 18 and data transceiver 12 need only communicate with each other through four device pins (i.e., four device pins on each device to enable transmission of the differential pair signals 14 and 16 between the data transceiver 12 and controller 18). For example, the use of separate pins for an MDIO interface may be avoided by transmitting control messages in-band over the differential pair signals 14 and 16.
- the differential pair signals 14 and 16 may be transmitted in a DDI extending thirty inches or more over a circuit board coupling the data transceiver 12 and controller 18 to the DDI.
- the system 10 may be provided on a line card in a switch, router or other platform that may be used for forwarding the contents of an Ethernet data frame from the node 34 and another node.
- the system 10 may provide a single port among multiple ports coupled by switching circuitry (e.g., switch fabric or Ethernet switch, not shown) to forward data frames from a source port (or ingress port) to a destination port (or egress port).
- switching circuitry e.g., switch fabric or Ethernet switch, not shown
- the system 10 may be provided in a system board or motherboard including a host processor (e.g., microprocessor for hosting an operating system and applications) and an I/O core logic chipset (e.g., system memory controller and peripheral I/O controller, not shown).
- a host processor e.g., microprocessor for hosting an operating system and applications
- an I/O core logic chipset e.g., system memory controller and peripheral I/O controller, not shown.
- the controller 18 may be integrated with one or more portions of an I/O core logic chipset while the data transceiver 12 is located near a physical port connection (e.g., cable connection) separated from the I/O core logic chipset.
- the controller 18 may be coupled to a multiplex data bus as defined in versions of the Peripheral Components Interconnect (PCI) Local Bus Specification 2.3, PCI-X or PCI-Express (e.g., coupled to a "switch" entity).
- PCI Peripheral Components Interconnect
- PCI-X Peripheral Components Interconnect
- PCI-Express e.g., coupled to a "switch" entity.
- the system board or motherboard of the presently illustrated embodiment may be combined with a system memory for storing machine-readable instructions of an operating system or application programs to be executed by the host processor.
- the host processor and system memory may host a device driver that defines buffer locations in the system memory that are used to store data packets received from the controller 18 in data frames or store data packets to be transmitted by the controller as Ethernet data frames.
- the controller 18 may comprise a TCP/IP offload engine (not shown) for performing TCP/IP protocol processing on TCP/IP packets received in Ethernet data frames from the node 34.
- 8B/10B code groups (e.g., including Ethernet data frames and control messages) between the data transceiver 12 and controller 18 in single differential pair signals 14 and 18.
- the 8B/10B code groups may be transmitted between such a data transceiver and controller in multiple differential pair signals.
- a data transceiver and controller may be coupled by a DDI comprising a 10 Gigabit Attachment Unit Interface (XAUI) providing four differential pair signals to transmit 8B/10B code groups from the data transceiver to the controller and four differential pair signals to transmit 8B/10B code groups from the controller to the data transceiver.
- XAUI 10 Gigabit Attachment Unit Interface
- the data transceiver and controller may each comprise sixteen device pins for coupling to the DDI, eight pins for transmitting 8B/10B code groups and eight pins for receiving 8B/10B code groups. Accordingly, 8B/10B code groups containing control messages may be inserted among 8B/10B code groups (containing Ethernet data frames) transmitted between the controller and data transceiver (in multiple differential pair signals) to obviate the need for an out-of band channel for transmitting the control messages between the data transceiver and the controller.
Abstract
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE112004002503T DE112004002503B4 (en) | 2003-12-19 | 2004-12-08 | Serial Ethernet device-to-device connection |
Applications Claiming Priority (2)
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US10/741,314 | 2003-12-19 | ||
US10/741,314 US7751442B2 (en) | 2003-12-19 | 2003-12-19 | Serial ethernet device-to-device interconnection |
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WO2005067221A1 true WO2005067221A1 (en) | 2005-07-21 |
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PCT/US2004/041105 WO2005067221A1 (en) | 2003-12-19 | 2004-12-08 | Serial ethernet device-to-device interconnection |
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US (2) | US7751442B2 (en) |
CN (1) | CN1894906A (en) |
DE (1) | DE112004002503B4 (en) |
TW (1) | TWI264232B (en) |
WO (1) | WO2005067221A1 (en) |
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US20050135421A1 (en) | 2005-06-23 |
US20060153238A1 (en) | 2006-07-13 |
TW200524446A (en) | 2005-07-16 |
TWI264232B (en) | 2006-10-11 |
DE112004002503B4 (en) | 2011-09-15 |
DE112004002503T5 (en) | 2006-11-02 |
US7751442B2 (en) | 2010-07-06 |
CN1894906A (en) | 2007-01-10 |
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