WO2004068589A1 - Narrow fin finfet - Google Patents
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- WO2004068589A1 WO2004068589A1 PCT/US2004/000963 US2004000963W WO2004068589A1 WO 2004068589 A1 WO2004068589 A1 WO 2004068589A1 US 2004000963 W US2004000963 W US 2004000963W WO 2004068589 A1 WO2004068589 A1 WO 2004068589A1
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- WO
- WIPO (PCT)
- Prior art keywords
- layer
- finfet
- fin structure
- fin
- polysilicon
- Prior art date
Links
- 239000010410 layer Substances 0.000 claims description 102
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 33
- 229920005591 polysilicon Polymers 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 18
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- 238000009966 trimming Methods 0.000 claims description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 abstract description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 206010010144 Completed suicide Diseases 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910005091 Si3N Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- -1 eribium Chemical compound 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- JZLMRQMUNCKZTP-UHFFFAOYSA-N molybdenum tantalum Chemical compound [Mo].[Ta] JZLMRQMUNCKZTP-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Definitions
- the present invention relates generally to semiconductor devices and methods of manufacturing semiconductor devices and, more particularly, to double-gate metal oxide semiconductor field-effect transistors (MOSFETs).
- MOSFETs metal oxide semiconductor field-effect transistors
- Transistors such as MOSFETs
- MOSFETs are the core building block of the vast majority of semiconductor devices.
- double-gate MOSFETs offer better characteristics than the conventional bulk silicon MOSFETs. These improvements arise because the double-gate MOSFET has a gate electrode on both sides of the channel, rather than only on one side as in conventional MOSFETs.
- One aspect of the invention is directed to a MOSFET device that includes a source and a drain structure formed on an insulating layer.
- a fin structure is formed on the insulating layer between the source and the drain.
- the fin structure includes a thinned region formed from a channel area of the fin structure.
- a protective layer is formed over at least the thinned region of the fin structure.
- the protective layer has a wider width than a width of the thinned region.
- a dielectric layer is formed around at least a portion of the fin structure and a gate is formed around the dielectric layer and the fin structure.
- Another aspect of the of the invention is directed to a method for forming a MOSFET device.
- the method includes forming a source, a drain, and a fin structure on an insulating layer. Portions of the fin structure act as a channel for the MOSFET.
- the method further includes forming a protective layer above the fin structure and trimming the fin structure to a width of about 3 nm to 6 nm without significantly trimming the protective layer.
- the method further includes growing a dielectric layer around the fin structure and depositing a polysilicon layer around the dielectric layer. The polysilicon layer acts as a gate area for the MOSFET.
- FIGs. 1 and 2 are cross-section views illustrating formation of a FinFET consistent with aspects of the invention
- Fig. 3 is a perspective view of the FinFET shown in Fig. 2
- Fig. 4 is a top view of the FinFET shown in Fig. 3
- Fig. 5 is a cross-section view taken along the line A-A' in Fig. 4
- Fig. 6 is a top view of the FinFET shown in Fig. 3
- Fig. 7 is a cross-section view taken along the line A-A' in Fig. 4;
- Fig. 8 is a top view of the FinFET shown in Fig. 7;
- Figs. 9 and 10 are cross-section views of the FinFET;
- Fig. 11 is a top view of a complete FinFET;
- Figs. 12-15 are cross-section views of a FinFET consistent with a second embodiment of the invention.
- Figs. 16-18 are cross-section views of a double-gate FinFET built around an SiGe layer.
- a FinFET refers to a type of MOSFET in which a conducting channel is formed in a vertical Si "fin.” FinFETs are generally known in the art.
- Fig. 1 is a cross-section illustrating doping of a starting structure for a FinFET 100.
- FinFET 100 may include a silicon-on-insulation (SOI) structure that includes buried oxide (BOX) layer 120 formed on a silicon and/or germanium substrate 110, with a silicon layer 130 over BOX layer 120.
- layer 130 may comprise germanium or silicon-germanium.
- BOX layer 120 may have a thickness ranging from about 200 nm to about 400 nm and silicon layer 130 may have a thickness ranging from about 30 nm to about 100 nm.
- a protective layer such as an oxide layer (e.g., Si0 2 ) and/or a nitride layer (e.g., S1 3 N 4 ) may next be deposited to act as a protective cap during subsequent etching.
- the silicon layer 130 and protective layers may then be etched to form a silicon fin 140 with protective layers 150 and 160 over top of fin 140 (see Fig. 2).
- Protective layer 150 may be an oxide layer and protective layer 160 may be a nitride layer.
- Layer 150 may have a thickness of, for example, approximately 15 nm and layer 160 may have a thickness ranging from about 50 - 75 nm.
- Source/drain regions may then be formed adjacent the ends of fin 140.
- silicon layer 130 may be patterned and etched to form source and drain regions simultaneously with fin 140.
- another layer of silicon may be deposited and etched in a conventional manner to form source and drain regions.
- Fig. 3 is a perspective view of FinFET 100 with source and drain regions 310 and 320 formed adjacent the ends of fin 140.
- Fig. 4 is a schematic top-level view of FinFET 100 with source region 310, drain region 320, and fin 140. .
- the cross-sectional views in Figs 1 and 2 are taken along the line A-A' in Fig. 4.
- a TEOS (tetraethylorthosilicate) layer 501 may next be deposited over FinFET 100.
- Fig. 5 is a cross- sectional-view of FinFET 100, taken along the line A-A' in Fig. 4, illustrating TEOS layer 501.
- the TEOS layer 501 may be annealed and planarized to produce a relatively flat surface across the top of FinFET 100.
- a damascene gate mask may be defined and patterned in TEOS 501.
- a trench may be formed in TEOS 501.
- the gate area may then be opened in TEOS 501 via etching.
- Fig. 6 is a diagram illustrating a top-level view of FinFET 100 in which area 602 in TEOS 501 is illustrated as the opened portion. More particularly the mask may be used to allow the TEOS in area 602 to be etched while maintaining the remaining TEOS 501.
- patterning the gate area to obtain small gate lengths may be performed by depositing a polysilicon layer to a depth of about 50 to 70 nm on the TEOS in area 602. This polysilicon layer may be patterned, leaving very thin polysilicon lines.
- a layer of oxide may then be deposited to about 120 to 150 nm and then polished back to the top of the polysilicon.
- the polysilicon is etched away.
- the TEOS in area 602 is then etched, using the remaining oxide layer as a mask for the TEOS etch.
- Fin 140 may next be thinned.
- fin 140 may be thinned by exposing FinFET 100 to NH OH until fin 140 is reduced from a width of 10 nm to 15 nm to a width of approximately 3 nm to 6 nm. This thinning process may be performed at a relatively slow and controlled pace such that the fin is trimmed at a rate of approximately 2 A/min.
- Fig. 7 is a cross- sectional view taken along the line A-A' in Fig. 4.
- Fig. 8 is a corresponding top-view of Fig. 7. As shown if Figs.
- FinFET 100 after thinning of fin 140, includes a cavity, formed beneath oxide layer 150 and nitride layer 160.
- a gate dielectric layer 901 may be grown on the side surfaces of fin 140 as illustrated in Fig. 9. Gate dielectric layer 901 may be as thin as 0.6 to 1.2 nm. Alternatively, a high-k layer with an equivalent oxide thickness (EOT) of 0.6 to 1.2 nm may be formed on the side surfaces of fin 140.
- EOT equivalent oxide thickness
- a layer of polysilicon may next be deposited on FinFET 100 in a conventional manner.
- the layer of polysilicon may be doped using gate doping masks. NMOS devices may be doped with phosphorous and PMOS devices may be doped with boron.
- the polysilicon may be planarized to the level of nitride layer 160, forming two separate polysilicon areas 1001A and 1001B.
- the polysilicon areas 1001A and 100 IB may be patterned and etched to form the gates of FinFET 100. Polysilicon areas 1001 A and 100 IB may thus form two electrically independent gates.
- polysilicon areas 1001 A and 1001B may not be polished to the level of S1 3 N 4 layer 160. Instead, a single polysilicon layer may cover Si 3 N layer 160. In this situation, the polysilicon layer forms a single addressable gate for FinFET 100.
- a mask may next be applied to the gate area 602. Using the mask to protect the gate area 602, the TEOS layer 501 and protective Si0 2 and Si 3 N layers 150 and 160 deposited over the source/drain region 310 and 320, may then be etched using an isotropic wet etch to remove the TEOS layer 501.
- ion implantation may be performed on FinFET 100.
- phosphorous may be implanted at a dosage of 10 15 atoms/cm 2 at 5-10 keV.
- boron may be implanted at a dosage of 10 15 atoms/cm 2 at 2-5 keV.
- salicidation i.e., a self-aligned suicide process
- a metal such as tungsten, cobalt, titanium, tantalum molybdenum, nickel, eribium, or platinum may be deposited over the polysilicon (gate) area 1001A and 1001B and source and drain regions 310 and 320.
- a thermal annealing may then be performed to create a metal-silicide compound.
- Fig. 11 illustrates a top- view of FinFET 100 after the annealing. Referring to Fig. 11, the cross-hatching represents the metal- silicide compound over source/drain regions 310 and 320 and the two gate regions.
- the gate regions may include gate pads 1101 and 1102 formed at the end of polysilicon areas 1001 A and 1001B.
- the resulting FinFET 100 includes a thin fin channel area 140, as indicated by the dotted lines in Fig. 11.
- the protective layers 150 and 160 are wider than fin 140, as illustrated in Fig. 10.
- the resulting thin channel MOSFETs provides improved short channel control.
- fin 140 may be trimmed through a reactive ion etching (RIE) process.
- RIE reactive ion etching
- the fin 140 may initially be thinned by RIE to reduce the width of fin 140 to a width of approximately 3 nm to 6 nm.
- Protective layers 150 and 160 may next be removed through an etch process to expose the fin, labeled as fin 1240 in Fig. 12.
- a sacrificial oxidation layer 1301 may next be formed on the exposed surfaces of fin 1240, as illustrated in Fig. 13.
- Sacrificial oxide layer may be grown or formed to a thickness of about 0.6 nm to 1.2 nm and may also function as a gate dielectric layer.
- an additional oxide layer or high-k layer with an equivalent oxide thickness (EOT) of 0.6 to 1.2 nm may be formed on the side surfaces of fin 140, labeled as layers 1401.
- a layer of polysilicon may next be deposited on FinFET 1200 in a conventional manner.
- the polysilicon may be planarized to the level of oxide layer 1301, forming two separate polysilicon areas 1201 A and 1201B.
- the polysilicon areas 1201A and 1201B may form the gates of FinFET 1200.
- Polysilicon areas 1201A and 1201B may thus form two electrically independent gates.
- polysilicon areas 1201A and 1201B may not be polished to the level of oxide layer 1301.
- a single polysilicon layer may cover oxide layer 1301.
- the polysilicon layer forms a single addressable gate for FinFET 1200.
- a mask may next be applied to the gate area of FinFET 1200. With the mask to protect the gate area, TEOS layer 501 and the additional protective layers deposited over the source/drain region 310 and 320 may then be etched away from the rest of the FinFET 1200.
- ion implantation may be performed on FinFET 1200. This effectively dopes the source 310 and drain 320. More specifically, for an NMOS FinFET, phosphorous may be implanted at a dosage of 10 15 atoms/cm 2 at 5-10 keV. For a PMOS FinFET, boron may be implanted at a dosage of 10 15 atoms/cm 2 at 2-5 keV. After ion implantation, salicidation (i.e., a self-aligned suicide process) may be performed on FinFET
- a metal such as tungsten, cobalt, titanium, tantalum or molybdenum, may be deposited over the polysilicon (gate) area 1201A and 1201B and source and drain regions 310 and 320. A thermal annealing may then be performed to create a metal-silicide compound.
- a top- view of FinFET 1200 is similar to the FinFET 200 shown in Fig. 11. OTHER IMPLEMENTATIONS In some situations it may be desirable to form strained silicon FinFETs.
- Figs. 16-18 are cross- sectional views of a FinFET 1600 taken along the line A-A' in Fig. 4.
- a SiGe layer 1610 may be formed on a buried-oxide layer 1601.
- a nitride layer 1620 may be formed above the SiGe layer 1610.
- the arrangement of SiGe layer 1610 and nitride layer 1620 may be formed, for example, in a manner similar to the thin fin shown in Fig. 7.
- SiGe layer 1610 and nitride layer 1620 may be initially etched to have the same width and SiGe layer 1610 may then be laterally etched to form a thin SiGe layer 1610.
- SiGe layer 1610 may be about 5 nm to 15 nm wide.
- Si layers 1611 may next be epitaxially grown around the SiGe layer to a width of about 5 nm to 10 nm.
- the growth of Si layers 1611 may be followed by the formation of gate dielectric layers 1612.
- Gate dielectric layers 1612 may be as thin as 0.6 to 1.2 nm.
- a polysilicon layer 1801 may next be deposited on FinFET 1600 in a conventional manner.
- the polysilicon layer may then be patterned and etched to form gates of FinFET 1600.
- Polysilicon layer 1801 may also be planarized down to the level of nitride layer 1620. At this point, FinFET 1600 may be completed in the manner described above.
- Some MOSFETs have both PMOS and NMOS FinFETS placed on a single buried oxide layer.
- selective salicidation may be achieved by electroless plating of an appropriate metal.
- two or more different suicides may be used.
- One silicide e.g., Co, Ni, rare earth metals Er, Eu, Ga, Sm
- another silicide e.g., Pt
- the PMOS FinFETs may first be covered by a photoresist and then the NMOS metal may be deposited.
- the photoresist over the PMOS FinFETs may then be removed and another photresist layer may be applied over the NMOS FinFETs. At this point, the PMOS metal may be applied. A thermal annealing may then be performed to create the metal- silicide compound.
- FinFETs having a narrow fin and methods of making the narrow fin FinFETs, were described herein.
- the narrow fin provides a number of advantages to the FinFET, including better short channel control.
- numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention.
- the present invention can be practiced without resorting to the specific details set forth herein.
- well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention.
- the dielectric and conductive layers used in manufacturing a semiconductor device in accordance with the present invention can be deposited by conventional deposition techniques.
- metallization techniques such as various types of chemical vapor deposition (CVD) processes, including low pressure chemical vapor deposition (LPCVD) and enhanced chemical vapor deposition (ECVD) can be employed.
- CVD chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- ECVD enhanced chemical vapor deposition
- the present invention is applicable in the manufacturing of semiconductor devices and particularly in semiconductor devices with design features of 100 nm and below, resulting in increased transistor and circuit speeds and improved reliability.
- the present invention is applicable to the formation of any of various types of semiconductor devices, and hence, details have not been set forth in order to avoid obscuring the thrust of the present invention.
- conventional photolithographic and etching techniques are employed and, hence, the details of such techniques have not been set forth herein in detail.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006502826A JP2006516820A (en) | 2003-01-23 | 2004-01-15 | Method for forming fin FET with narrow fin structure |
CN2004800026970A CN1759488B (en) | 2003-01-23 | 2004-01-15 | Narrow fin finfet |
EP04702507A EP1588422A1 (en) | 2003-01-23 | 2004-01-15 | Narrow fin finfet |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/348,910 US6762483B1 (en) | 2003-01-23 | 2003-01-23 | Narrow fin FinFET |
US10/348,910 | 2003-01-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004068589A1 true WO2004068589A1 (en) | 2004-08-12 |
Family
ID=32681618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/000963 WO2004068589A1 (en) | 2003-01-23 | 2004-01-15 | Narrow fin finfet |
Country Status (7)
Country | Link |
---|---|
US (2) | US6762483B1 (en) |
EP (1) | EP1588422A1 (en) |
JP (1) | JP2006516820A (en) |
KR (1) | KR101035421B1 (en) |
CN (1) | CN1759488B (en) |
TW (1) | TW200418180A (en) |
WO (1) | WO2004068589A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005048339A1 (en) * | 2003-11-04 | 2005-05-26 | Advanced Micro Devices, Inc. | Self aligned damascene gate |
WO2005071727A1 (en) * | 2004-01-12 | 2005-08-04 | Advanced Micro Devices, Inc. | Narrow-body damascene tri-gate finfet having thinned body |
US6967175B1 (en) | 2003-12-04 | 2005-11-22 | Advanced Micro Devices, Inc. | Damascene gate semiconductor processing with local thinning of channel region |
JP2006080529A (en) * | 2004-09-10 | 2006-03-23 | Samsung Electronics Co Ltd | Semiconductor device having joining region extended by seg film and manufacturing method therefor |
EP1643560A1 (en) * | 2003-05-30 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing same |
JP2008219002A (en) * | 2007-02-28 | 2008-09-18 | Internatl Business Mach Corp <Ibm> | FinFET WITH OVERLAP SENSITIVITY BETWEEN GATE AND FIN REDUCED |
WO2009036273A3 (en) * | 2007-09-12 | 2009-05-22 | Univ Arizona State | Horizontally depleted metal semiconductor field effect transistor |
US7692246B2 (en) | 2006-01-12 | 2010-04-06 | Infineon Technologies Ag | Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement |
Families Citing this family (169)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6503783B1 (en) * | 2000-08-31 | 2003-01-07 | Micron Technology, Inc. | SOI CMOS device with reduced DIBL |
US6657276B1 (en) * | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
US20060170053A1 (en) * | 2003-05-09 | 2006-08-03 | Yee-Chia Yeo | Accumulation mode multiple gate transistor |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
KR100517559B1 (en) * | 2003-06-27 | 2005-09-28 | 삼성전자주식회사 | Fin field effect transistor and method for forming of fin therein |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
DE10348007B4 (en) * | 2003-10-15 | 2008-04-17 | Infineon Technologies Ag | Method for structuring and field effect transistors |
US7105390B2 (en) | 2003-12-30 | 2006-09-12 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US7268058B2 (en) * | 2004-01-16 | 2007-09-11 | Intel Corporation | Tri-gate transistors and methods to fabricate same |
US6894337B1 (en) * | 2004-02-02 | 2005-05-17 | Advanced Micro Devices, Inc. | System and method for forming stacked fin structure using metal-induced-crystallization |
KR100598099B1 (en) * | 2004-02-24 | 2006-07-07 | 삼성전자주식회사 | Vertical channel fin fet having a damascene gate and method for fabricating the same |
US7060539B2 (en) * | 2004-03-01 | 2006-06-13 | International Business Machines Corporation | Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby |
US6872640B1 (en) * | 2004-03-16 | 2005-03-29 | Micron Technology, Inc. | SOI CMOS device with reduced DIBL |
US7115947B2 (en) * | 2004-03-18 | 2006-10-03 | International Business Machines Corporation | Multiple dielectric finfet structure and method |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
DE102004027691B4 (en) * | 2004-06-07 | 2008-04-30 | Infineon Technologies Ag | Method for producing a web made of a semiconductor material |
US7042009B2 (en) * | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7009250B1 (en) * | 2004-08-20 | 2006-03-07 | Micron Technology, Inc. | FinFET device with reduced DIBL |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7332439B2 (en) | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
US7361958B2 (en) | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7274053B2 (en) * | 2004-11-05 | 2007-09-25 | International Business Machines Corporation | Fin device with capacitor integrated under gate electrode |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US20060118892A1 (en) * | 2004-12-02 | 2006-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Structures to Produce a Strain-Inducing Layer in a Semiconductor Device |
US7193279B2 (en) * | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US9153645B2 (en) | 2005-05-17 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7288802B2 (en) * | 2005-07-27 | 2007-10-30 | International Business Machines Corporation | Virtual body-contacted trigate |
US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US7396711B2 (en) * | 2005-12-27 | 2008-07-08 | Intel Corporation | Method of fabricating a multi-cornered film |
US7666741B2 (en) | 2006-01-17 | 2010-02-23 | International Business Machines Corporation | Corner clipping for field effect devices |
WO2007112066A2 (en) | 2006-03-24 | 2007-10-04 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures and related methods for device fabrication |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
WO2008030574A1 (en) | 2006-09-07 | 2008-03-13 | Amberwave Systems Corporation | Defect reduction using aspect ratio trapping |
WO2008039495A1 (en) | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Tri-gate field-effect transistors formed by aspect ratio trapping |
US7875958B2 (en) | 2006-09-27 | 2011-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
WO2008051503A2 (en) | 2006-10-19 | 2008-05-02 | Amberwave Systems Corporation | Light-emitter-based devices with lattice-mismatched semiconductor structures |
US7772048B2 (en) * | 2007-02-23 | 2010-08-10 | Freescale Semiconductor, Inc. | Forming semiconductor fins using a sacrificial fin |
US8304805B2 (en) | 2009-01-09 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
WO2008124154A2 (en) | 2007-04-09 | 2008-10-16 | Amberwave Systems Corporation | Photovoltaics on silicon |
US7825328B2 (en) | 2007-04-09 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
KR101443215B1 (en) * | 2007-06-13 | 2014-09-24 | 삼성전자주식회사 | Field effect transistor using ambipolar material and logic circuit |
US8329541B2 (en) | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
US7923337B2 (en) | 2007-06-20 | 2011-04-12 | International Business Machines Corporation | Fin field effect transistor devices with self-aligned source and drain regions |
KR101093588B1 (en) | 2007-09-07 | 2011-12-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Multi-junction solar cells |
US20090124097A1 (en) * | 2007-11-09 | 2009-05-14 | International Business Machines Corporation | Method of forming narrow fins in finfet devices with reduced spacing therebetween |
US8003466B2 (en) * | 2008-04-08 | 2011-08-23 | Advanced Micro Devices, Inc. | Method of forming multiple fins for a semiconductor device |
US8183667B2 (en) | 2008-06-03 | 2012-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial growth of crystalline material |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US20090321833A1 (en) * | 2008-06-25 | 2009-12-31 | International Business Machines Corporation | VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC |
US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
US8981427B2 (en) | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
US7994020B2 (en) * | 2008-07-21 | 2011-08-09 | Advanced Micro Devices, Inc. | Method of forming finned semiconductor devices with trench isolation |
US20100072515A1 (en) | 2008-09-19 | 2010-03-25 | Amberwave Systems Corporation | Fabrication and structures of crystalline material |
KR101216541B1 (en) | 2008-09-19 | 2012-12-31 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Formation of devices by epitaxial layer overgrowth |
US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
US7871873B2 (en) * | 2009-03-27 | 2011-01-18 | Global Foundries Inc. | Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material |
CN101853882B (en) | 2009-04-01 | 2016-03-23 | 台湾积体电路制造股份有限公司 | There is the high-mobility multiple-gate transistor of the switch current ratio of improvement |
US8816391B2 (en) * | 2009-04-01 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain engineering of devices with high-mobility channels |
JP5705207B2 (en) | 2009-04-02 | 2015-04-22 | 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. | Device formed from non-polar surface of crystalline material and method of manufacturing the same |
US8455860B2 (en) | 2009-04-30 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing source/drain resistance of III-V based transistors |
US9768305B2 (en) * | 2009-05-29 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gradient ternary or quaternary multiple-gate transistor |
US8617976B2 (en) * | 2009-06-01 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain re-growth for manufacturing III-V based transistors |
US8258577B2 (en) * | 2009-06-04 | 2012-09-04 | International Business Machines Corporation | CMOS inverter device with fin structures |
US7985639B2 (en) * | 2009-09-18 | 2011-07-26 | GlobalFoundries, Inc. | Method for fabricating a semiconductor device having a semiconductive resistor structure |
US8101486B2 (en) | 2009-10-07 | 2012-01-24 | Globalfoundries Inc. | Methods for forming isolated fin structures on bulk semiconductor material |
JP5404812B2 (en) * | 2009-12-04 | 2014-02-05 | 株式会社東芝 | Manufacturing method of semiconductor device |
CN102263131B (en) * | 2010-05-25 | 2013-05-01 | 中国科学院微电子研究所 | Semiconductor device and formation method thereof |
CN102315269B (en) * | 2010-07-01 | 2013-12-25 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
US8551829B2 (en) | 2010-11-10 | 2013-10-08 | United Microelectronics Corp. | Method for manufacturing multi-gate transistor device |
US8361854B2 (en) | 2011-03-21 | 2013-01-29 | United Microelectronics Corp. | Fin field-effect transistor structure and manufacturing process thereof |
US8597994B2 (en) | 2011-05-23 | 2013-12-03 | GlobalFoundries, Inc. | Semiconductor device and method of fabrication |
US8614152B2 (en) | 2011-05-25 | 2013-12-24 | United Microelectronics Corp. | Gate structure and a method for forming the same |
US8772860B2 (en) | 2011-05-26 | 2014-07-08 | United Microelectronics Corp. | FINFET transistor structure and method for making the same |
US9184100B2 (en) | 2011-08-10 | 2015-11-10 | United Microelectronics Corp. | Semiconductor device having strained fin structure and method of making the same |
US9105660B2 (en) | 2011-08-17 | 2015-08-11 | United Microelectronics Corp. | Fin-FET and method of forming the same |
US8853013B2 (en) | 2011-08-19 | 2014-10-07 | United Microelectronics Corp. | Method for fabricating field effect transistor with fin structure |
US8674433B2 (en) | 2011-08-24 | 2014-03-18 | United Microelectronics Corp. | Semiconductor process |
US8691651B2 (en) | 2011-08-25 | 2014-04-08 | United Microelectronics Corp. | Method of forming non-planar FET |
US8441072B2 (en) | 2011-09-02 | 2013-05-14 | United Microelectronics Corp. | Non-planar semiconductor structure and fabrication method thereof |
US8426277B2 (en) | 2011-09-23 | 2013-04-23 | United Microelectronics Corp. | Semiconductor process |
US8497198B2 (en) | 2011-09-23 | 2013-07-30 | United Microelectronics Corp. | Semiconductor process |
US8722501B2 (en) | 2011-10-18 | 2014-05-13 | United Microelectronics Corp. | Method for manufacturing multi-gate transistor device |
US8575708B2 (en) | 2011-10-26 | 2013-11-05 | United Microelectronics Corp. | Structure of field effect transistor with fin structure |
US8871575B2 (en) | 2011-10-31 | 2014-10-28 | United Microelectronics Corp. | Method of fabricating field effect transistor with fin structure |
US8278184B1 (en) | 2011-11-02 | 2012-10-02 | United Microelectronics Corp. | Fabrication method of a non-planar transistor |
US8426283B1 (en) | 2011-11-10 | 2013-04-23 | United Microelectronics Corp. | Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate |
US8440511B1 (en) | 2011-11-16 | 2013-05-14 | United Microelectronics Corp. | Method for manufacturing multi-gate transistor device |
US8604548B2 (en) | 2011-11-23 | 2013-12-10 | United Microelectronics Corp. | Semiconductor device having ESD device |
US8803247B2 (en) | 2011-12-15 | 2014-08-12 | United Microelectronics Corporation | Fin-type field effect transistor |
US9087687B2 (en) * | 2011-12-23 | 2015-07-21 | International Business Machines Corporation | Thin heterostructure channel device |
US8759184B2 (en) | 2012-01-09 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and the methods for forming the same |
US8609499B2 (en) * | 2012-01-09 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and the methods for forming the same |
US8698199B2 (en) | 2012-01-11 | 2014-04-15 | United Microelectronics Corp. | FinFET structure |
US9698229B2 (en) | 2012-01-17 | 2017-07-04 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US8946031B2 (en) | 2012-01-18 | 2015-02-03 | United Microelectronics Corp. | Method for fabricating MOS device |
US8664060B2 (en) | 2012-02-07 | 2014-03-04 | United Microelectronics Corp. | Semiconductor structure and method of fabricating the same |
US8822284B2 (en) | 2012-02-09 | 2014-09-02 | United Microelectronics Corp. | Method for fabricating FinFETs and semiconductor structure fabricated using the method |
US9159809B2 (en) | 2012-02-29 | 2015-10-13 | United Microelectronics Corp. | Multi-gate transistor device |
US9006107B2 (en) | 2012-03-11 | 2015-04-14 | United Microelectronics Corp. | Patterned structure of semiconductor device and fabricating method thereof |
US9159626B2 (en) | 2012-03-13 | 2015-10-13 | United Microelectronics Corp. | FinFET and fabricating method thereof |
US8946078B2 (en) | 2012-03-22 | 2015-02-03 | United Microelectronics Corp. | Method of forming trench in semiconductor substrate |
US9559189B2 (en) | 2012-04-16 | 2017-01-31 | United Microelectronics Corp. | Non-planar FET |
US9142649B2 (en) | 2012-04-23 | 2015-09-22 | United Microelectronics Corp. | Semiconductor structure with metal gate and method of fabricating the same |
US8766319B2 (en) | 2012-04-26 | 2014-07-01 | United Microelectronics Corp. | Semiconductor device with ultra thin silicide layer |
US8709910B2 (en) | 2012-04-30 | 2014-04-29 | United Microelectronics Corp. | Semiconductor process |
US8691652B2 (en) | 2012-05-03 | 2014-04-08 | United Microelectronics Corp. | Semiconductor process |
US8877623B2 (en) | 2012-05-14 | 2014-11-04 | United Microelectronics Corp. | Method of forming semiconductor device |
US8470714B1 (en) | 2012-05-22 | 2013-06-25 | United Microelectronics Corp. | Method of forming fin structures in integrated circuits |
US9012975B2 (en) | 2012-06-14 | 2015-04-21 | United Microelectronics Corp. | Field effect transistor and manufacturing method thereof |
US8796695B2 (en) | 2012-06-22 | 2014-08-05 | United Microelectronics Corp. | Multi-gate field-effect transistor and process thereof |
US9142400B1 (en) | 2012-07-17 | 2015-09-22 | Stc.Unm | Method of making a heteroepitaxial layer on a seed area |
US8872280B2 (en) | 2012-07-31 | 2014-10-28 | United Microelectronics Corp. | Non-planar FET and manufacturing method thereof |
US9318567B2 (en) | 2012-09-05 | 2016-04-19 | United Microelectronics Corp. | Fabrication method for semiconductor devices |
US9159831B2 (en) | 2012-10-29 | 2015-10-13 | United Microelectronics Corp. | Multigate field effect transistor and process thereof |
CN103839814B (en) * | 2012-11-21 | 2016-12-21 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
US9536792B2 (en) | 2013-01-10 | 2017-01-03 | United Microelectronics Corp. | Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof |
US9076870B2 (en) | 2013-02-21 | 2015-07-07 | United Microelectronics Corp. | Method for forming fin-shaped structure |
US8841197B1 (en) | 2013-03-06 | 2014-09-23 | United Microelectronics Corp. | Method for forming fin-shaped structures |
US9196500B2 (en) | 2013-04-09 | 2015-11-24 | United Microelectronics Corp. | Method for manufacturing semiconductor structures |
US9711368B2 (en) | 2013-04-15 | 2017-07-18 | United Microelectronics Corp. | Sidewall image transfer process |
US8853015B1 (en) | 2013-04-16 | 2014-10-07 | United Microelectronics Corp. | Method of forming a FinFET structure |
US8709901B1 (en) | 2013-04-17 | 2014-04-29 | United Microelectronics Corp. | Method of forming an isolation structure |
US9147747B2 (en) | 2013-05-02 | 2015-09-29 | United Microelectronics Corp. | Semiconductor structure with hard mask disposed on the gate structure |
US9000483B2 (en) | 2013-05-16 | 2015-04-07 | United Microelectronics Corp. | Semiconductor device with fin structure and fabrication method thereof |
US9263287B2 (en) | 2013-05-27 | 2016-02-16 | United Microelectronics Corp. | Method of forming fin-shaped structure |
US8802521B1 (en) | 2013-06-04 | 2014-08-12 | United Microelectronics Corp. | Semiconductor fin-shaped structure and manufacturing process thereof |
US9006804B2 (en) | 2013-06-06 | 2015-04-14 | United Microelectronics Corp. | Semiconductor device and fabrication method thereof |
US9070710B2 (en) | 2013-06-07 | 2015-06-30 | United Microelectronics Corp. | Semiconductor process |
US8993384B2 (en) | 2013-06-09 | 2015-03-31 | United Microelectronics Corp. | Semiconductor device and fabrication method thereof |
US9401429B2 (en) | 2013-06-13 | 2016-07-26 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US9263282B2 (en) | 2013-06-13 | 2016-02-16 | United Microelectronics Corporation | Method of fabricating semiconductor patterns |
US9048246B2 (en) | 2013-06-18 | 2015-06-02 | United Microelectronics Corp. | Die seal ring and method of forming the same |
US9123810B2 (en) | 2013-06-18 | 2015-09-01 | United Microelectronics Corp. | Semiconductor integrated device including FinFET device and protecting structure |
US9190291B2 (en) | 2013-07-03 | 2015-11-17 | United Microelectronics Corp. | Fin-shaped structure forming process |
US9105685B2 (en) | 2013-07-12 | 2015-08-11 | United Microelectronics Corp. | Method of forming shallow trench isolation structure |
US9093565B2 (en) | 2013-07-15 | 2015-07-28 | United Microelectronics Corp. | Fin diode structure |
US9019672B2 (en) | 2013-07-17 | 2015-04-28 | United Microelectronics Corporation | Chip with electrostatic discharge protection function |
US8981487B2 (en) | 2013-07-31 | 2015-03-17 | United Microelectronics Corp. | Fin-shaped field-effect transistor (FinFET) |
US9006805B2 (en) | 2013-08-07 | 2015-04-14 | United Microelectronics Corp. | Semiconductor device |
US9105582B2 (en) | 2013-08-15 | 2015-08-11 | United Microelectronics Corporation | Spatial semiconductor structure and method of fabricating the same |
US9385048B2 (en) | 2013-09-05 | 2016-07-05 | United Microelectronics Corp. | Method of forming Fin-FET |
US9373719B2 (en) | 2013-09-16 | 2016-06-21 | United Microelectronics Corp. | Semiconductor device |
US9934981B2 (en) * | 2013-09-26 | 2018-04-03 | Varian Semiconductor Equipment Associates, Inc. | Techniques for processing substrates using directional reactive ion etching |
US9018066B2 (en) | 2013-09-30 | 2015-04-28 | United Microelectronics Corp. | Method of fabricating semiconductor device structure |
US9166024B2 (en) | 2013-09-30 | 2015-10-20 | United Microelectronics Corp. | FinFET structure with cavities and semiconductor compound portions extending laterally over sidewall spacers |
US9306032B2 (en) | 2013-10-25 | 2016-04-05 | United Microelectronics Corp. | Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric |
US8980701B1 (en) | 2013-11-05 | 2015-03-17 | United Microelectronics Corp. | Method of forming semiconductor device |
US9299843B2 (en) | 2013-11-13 | 2016-03-29 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
US8951884B1 (en) | 2013-11-14 | 2015-02-10 | United Microelectronics Corp. | Method for forming a FinFET structure |
CN103681356A (en) * | 2013-12-27 | 2014-03-26 | 上海集成电路研发中心有限公司 | Method for manufacturing FinFET by using carbon nano tube as mask |
US10854735B2 (en) * | 2014-09-03 | 2020-12-01 | Taiwan Semiconductor Manufacturing Company Limited | Method of forming transistor |
US9391074B1 (en) | 2015-04-21 | 2016-07-12 | International Business Machines Corporation | Structure for FinFET fins |
US10008384B2 (en) | 2015-06-25 | 2018-06-26 | Varian Semiconductor Equipment Associates, Inc. | Techniques to engineer nanoscale patterned features using ions |
US9935102B1 (en) | 2016-10-05 | 2018-04-03 | International Business Machines Corporation | Method and structure for improving vertical transistor |
US10096524B1 (en) | 2017-10-18 | 2018-10-09 | International Business Machines Corporation | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors |
US11545575B2 (en) | 2020-07-02 | 2023-01-03 | Globalfoundries U.S. Inc. | IC structure with fin having subfin extents with different lateral dimensions |
US11211453B1 (en) | 2020-07-23 | 2021-12-28 | Globalfoundries U.S. Inc. | FinFET with shorter fin height in drain region than source region and related method |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5757038A (en) * | 1995-11-06 | 1998-05-26 | International Business Machines Corporation | Self-aligned dual gate MOSFET with an ultranarrow channel |
US6300182B1 (en) * | 2000-12-11 | 2001-10-09 | Advanced Micro Devices, Inc. | Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage |
EP1202335A2 (en) * | 2000-10-18 | 2002-05-02 | International Business Machines Corporation | Method of fabricating semiconductor side wall fin |
US20020130354A1 (en) * | 2001-03-13 | 2002-09-19 | National Inst. Of Advanced Ind. Science And Tech. | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same |
US6458662B1 (en) * | 2001-04-04 | 2002-10-01 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed |
US20020140039A1 (en) * | 2000-11-13 | 2002-10-03 | International Business Machines Corporation | Double gate trench transistor |
US6475869B1 (en) * | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
JP3543117B2 (en) * | 2001-03-13 | 2004-07-14 | 独立行政法人産業技術総合研究所 | Double gate field effect transistor |
JP2002289871A (en) * | 2001-03-28 | 2002-10-04 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
KR100431489B1 (en) * | 2001-09-04 | 2004-05-12 | 한국과학기술원 | Flash memory element and manufacturing method |
US6657259B2 (en) | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US6583469B1 (en) * | 2002-01-28 | 2003-06-24 | International Business Machines Corporation | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same |
US6657252B2 (en) | 2002-03-19 | 2003-12-02 | International Business Machines Corporation | FinFET CMOS with NVRAM capability |
US6750487B2 (en) * | 2002-04-11 | 2004-06-15 | International Business Machines Corporation | Dual double gate transistor |
US6642090B1 (en) | 2002-06-03 | 2003-11-04 | International Business Machines Corporation | Fin FET devices from bulk semiconductor and method for forming |
US6770516B2 (en) * | 2002-09-05 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate |
US6706571B1 (en) | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
US6709982B1 (en) | 2002-11-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Double spacer FinFET formation |
US6645797B1 (en) | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
-
2003
- 2003-01-23 US US10/348,910 patent/US6762483B1/en not_active Expired - Lifetime
-
2004
- 2004-01-15 KR KR1020057013667A patent/KR101035421B1/en not_active IP Right Cessation
- 2004-01-15 CN CN2004800026970A patent/CN1759488B/en not_active Expired - Lifetime
- 2004-01-15 EP EP04702507A patent/EP1588422A1/en not_active Ceased
- 2004-01-15 JP JP2006502826A patent/JP2006516820A/en active Pending
- 2004-01-15 WO PCT/US2004/000963 patent/WO2004068589A1/en active Search and Examination
- 2004-01-20 TW TW093101517A patent/TW200418180A/en unknown
- 2004-04-23 US US10/830,006 patent/US6921963B2/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5757038A (en) * | 1995-11-06 | 1998-05-26 | International Business Machines Corporation | Self-aligned dual gate MOSFET with an ultranarrow channel |
EP1202335A2 (en) * | 2000-10-18 | 2002-05-02 | International Business Machines Corporation | Method of fabricating semiconductor side wall fin |
US20020140039A1 (en) * | 2000-11-13 | 2002-10-03 | International Business Machines Corporation | Double gate trench transistor |
US6300182B1 (en) * | 2000-12-11 | 2001-10-09 | Advanced Micro Devices, Inc. | Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage |
US6475869B1 (en) * | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
US20020130354A1 (en) * | 2001-03-13 | 2002-09-19 | National Inst. Of Advanced Ind. Science And Tech. | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same |
US6458662B1 (en) * | 2001-04-04 | 2002-10-01 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed |
Non-Patent Citations (1)
Title |
---|
CHOI Y-K ET AL: "SUB-20NM CMOS FINFET TECHNOLOGIES", INTERNATIONAL ELECTRON DEVICES MEETING 2001. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC. 2 - 5, 2001, NEW YORK, NY: IEEE, US, 2 December 2001 (2001-12-02), pages 421 - 424, XP001075562, ISBN: 0-7803-7050-3 * |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1643560A4 (en) * | 2003-05-30 | 2007-04-11 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing same |
EP1643560A1 (en) * | 2003-05-30 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing same |
US7473967B2 (en) | 2003-05-30 | 2009-01-06 | Panasonic Corporation | Strained channel finFET device |
WO2005048339A1 (en) * | 2003-11-04 | 2005-05-26 | Advanced Micro Devices, Inc. | Self aligned damascene gate |
GB2424517A (en) * | 2003-11-04 | 2006-09-27 | Advanced Micro Devices Inc | Self aligned damascene gate |
GB2424517B (en) * | 2003-11-04 | 2007-07-11 | Advanced Micro Devices Inc | Self aligned damascene gate |
US6967175B1 (en) | 2003-12-04 | 2005-11-22 | Advanced Micro Devices, Inc. | Damascene gate semiconductor processing with local thinning of channel region |
GB2426124A (en) * | 2004-01-12 | 2006-11-15 | Advanced Micro Devices Inc | Narrow-body damascene tri-gate finfet having thinned body |
US7186599B2 (en) | 2004-01-12 | 2007-03-06 | Advanced Micro Devices, Inc. | Narrow-body damascene tri-gate FinFET |
WO2005071727A1 (en) * | 2004-01-12 | 2005-08-04 | Advanced Micro Devices, Inc. | Narrow-body damascene tri-gate finfet having thinned body |
GB2426124B (en) * | 2004-01-12 | 2007-12-12 | Advanced Micro Devices Inc | Narrow-body damascene tri-gate finfet having thinned body |
JP2006080529A (en) * | 2004-09-10 | 2006-03-23 | Samsung Electronics Co Ltd | Semiconductor device having joining region extended by seg film and manufacturing method therefor |
US7692246B2 (en) | 2006-01-12 | 2010-04-06 | Infineon Technologies Ag | Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement |
JP2008219002A (en) * | 2007-02-28 | 2008-09-18 | Internatl Business Mach Corp <Ibm> | FinFET WITH OVERLAP SENSITIVITY BETWEEN GATE AND FIN REDUCED |
WO2009036273A3 (en) * | 2007-09-12 | 2009-05-22 | Univ Arizona State | Horizontally depleted metal semiconductor field effect transistor |
US8441048B2 (en) | 2007-09-12 | 2013-05-14 | Arizona Board Of Regents For And On Behalf Of Arizona State University | Horizontally depleted metal semiconductor field effect transistor |
Also Published As
Publication number | Publication date |
---|---|
US6762483B1 (en) | 2004-07-13 |
KR20050096156A (en) | 2005-10-05 |
JP2006516820A (en) | 2006-07-06 |
EP1588422A1 (en) | 2005-10-26 |
TW200418180A (en) | 2004-09-16 |
CN1759488A (en) | 2006-04-12 |
CN1759488B (en) | 2010-08-18 |
US6921963B2 (en) | 2005-07-26 |
KR101035421B1 (en) | 2011-05-20 |
US20040197975A1 (en) | 2004-10-07 |
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