WO2004001798A3 - A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide - Google Patents

A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide Download PDF

Info

Publication number
WO2004001798A3
WO2004001798A3 PCT/US2003/017824 US0317824W WO2004001798A3 WO 2004001798 A3 WO2004001798 A3 WO 2004001798A3 US 0317824 W US0317824 W US 0317824W WO 2004001798 A3 WO2004001798 A3 WO 2004001798A3
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
making
same
strained
oxide layer
Prior art date
Application number
PCT/US2003/017824
Other languages
French (fr)
Other versions
WO2004001798A2 (en
Inventor
Witold P Maszara
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to EP03734436A priority Critical patent/EP1516362A2/en
Priority to AU2003238916A priority patent/AU2003238916A1/en
Priority to KR1020047021192A priority patent/KR100996725B1/en
Priority to JP2004515743A priority patent/JP4452883B2/en
Publication of WO2004001798A2 publication Critical patent/WO2004001798A2/en
Publication of WO2004001798A3 publication Critical patent/WO2004001798A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281Lateral isolation by selective oxidation of silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/78654Monocrystalline silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

A silicon-on-insulator (SOI) device with a strained silicon film (14) has a substrate (10), and a buried oxide layer (12) on the substrate (10). Silicon islands (18) are formed on the buried oxide layer (12), the silicon islands (18) being separated from each other by gaps (16). The buried oxide layer (12) has recesses (22) directly under the gaps (16). A material (24) fills the recesses and the gaps (16), this material (24) being different from the material forming the buried oxide layer (12). The material (24) induces a net amount of strain in the silicon islands (18), thereby modifying the electrical properties of carriers in the silicon film (14) and improving device performance.
PCT/US2003/017824 2002-06-25 2003-06-04 A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide WO2004001798A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP03734436A EP1516362A2 (en) 2002-06-25 2003-06-04 A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
AU2003238916A AU2003238916A1 (en) 2002-06-25 2003-06-04 A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
KR1020047021192A KR100996725B1 (en) 2002-06-25 2003-06-04 A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
JP2004515743A JP4452883B2 (en) 2002-06-25 2003-06-04 Silicon-on-insulator device having strained device film partially substituted with insulating oxide and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/178,542 2002-06-25
US10/178,542 US6680240B1 (en) 2002-06-25 2002-06-25 Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide

Publications (2)

Publication Number Publication Date
WO2004001798A2 WO2004001798A2 (en) 2003-12-31
WO2004001798A3 true WO2004001798A3 (en) 2004-07-29

Family

ID=29999123

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/017824 WO2004001798A2 (en) 2002-06-25 2003-06-04 A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide

Country Status (8)

Country Link
US (1) US6680240B1 (en)
EP (1) EP1516362A2 (en)
JP (1) JP4452883B2 (en)
KR (1) KR100996725B1 (en)
CN (1) CN1333454C (en)
AU (1) AU2003238916A1 (en)
TW (1) TWI289895B (en)
WO (1) WO2004001798A2 (en)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
AU2003222003A1 (en) * 2002-03-14 2003-09-29 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6946373B2 (en) * 2002-11-20 2005-09-20 International Business Machines Corporation Relaxed, low-defect SGOI for strained Si CMOS applications
FR2847715B1 (en) * 2002-11-25 2005-03-11 Commissariat Energie Atomique INTEGRATED CIRCUIT COMPRISING SERIES CONNECTED SUBASSEMBLIES
US6717216B1 (en) * 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US7157774B2 (en) * 2003-01-31 2007-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Strained silicon-on-insulator transistors with mesa isolation
US6870179B2 (en) * 2003-03-31 2005-03-22 Intel Corporation Increasing stress-enhanced drive current in a MOS transistor
US7081395B2 (en) * 2003-05-23 2006-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US20050186722A1 (en) * 2004-02-25 2005-08-25 Kuan-Lun Cheng Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050266632A1 (en) * 2004-05-26 2005-12-01 Yun-Hsiu Chen Integrated circuit with strained and non-strained transistors, and method of forming thereof
US7579280B2 (en) * 2004-06-01 2009-08-25 Intel Corporation Method of patterning a film
US7042009B2 (en) * 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7135372B2 (en) * 2004-09-09 2006-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon device manufacturing method
US7071064B2 (en) * 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) * 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
JP4603845B2 (en) * 2004-10-12 2010-12-22 Okiセミコンダクタ株式会社 Manufacturing method of semiconductor device
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7306997B2 (en) * 2004-11-10 2007-12-11 Advanced Micro Devices, Inc. Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) * 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7563701B2 (en) * 2005-03-31 2009-07-21 Intel Corporation Self-aligned contacts for transistors
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) * 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090408A1 (en) * 2005-09-29 2007-04-26 Amlan Majumdar Narrow-body multiple-gate FET with dominant body transistor for high performance
US7759739B2 (en) * 2005-10-27 2010-07-20 International Business Machines Corporation Transistor with dielectric stressor elements
GB2445511B (en) * 2005-10-31 2009-04-08 Advanced Micro Devices Inc An embedded strain layer in thin soi transistors and a method of forming the same
DE102005052055B3 (en) 2005-10-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Transistor and semiconductor components and production process for thin film silicon on insulator transistor has embedded deformed layer
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7396711B2 (en) * 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US7449373B2 (en) * 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7670928B2 (en) * 2006-06-14 2010-03-02 Intel Corporation Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
US7544594B2 (en) * 2006-06-28 2009-06-09 Intel Corporation Method of forming a transistor having gate protection and transistor formed according to the method
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
KR100835413B1 (en) * 2006-12-05 2008-06-04 동부일렉트로닉스 주식회사 Method for forming a small via hole of the semiconductor device
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US8558278B2 (en) * 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
KR101052868B1 (en) * 2008-02-29 2011-07-29 주식회사 하이닉스반도체 SOI element and its manufacturing method
US7943961B2 (en) * 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20100019322A1 (en) * 2008-07-23 2010-01-28 International Business Machines Corporation Semiconductor device and method of manufacturing
US7808051B2 (en) * 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
CN102024706B (en) * 2009-09-22 2012-06-20 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
US8258031B2 (en) * 2010-06-15 2012-09-04 International Business Machines Corporation Fabrication of a vertical heterojunction tunnel-FET
US9406798B2 (en) * 2010-08-27 2016-08-02 Acorn Technologies, Inc. Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
JP6005364B2 (en) * 2012-02-06 2016-10-12 ラピスセミコンダクタ株式会社 Semiconductor device manufacturing method and semiconductor device
US9515181B2 (en) 2014-08-06 2016-12-06 Qualcomm Incorporated Semiconductor device with self-aligned back side features
JP6559745B2 (en) 2017-08-23 2019-08-14 株式会社東芝 Semiconductor device inspection apparatus, semiconductor device inspection method, program thereof, semiconductor device and manufacturing method thereof
JP2018032877A (en) * 2017-11-29 2018-03-01 ラピスセミコンダクタ株式会社 Semiconductor device
JP2019125747A (en) 2018-01-18 2019-07-25 株式会社東芝 Semiconductor device and method for manufacturing the same
KR102396978B1 (en) * 2018-11-16 2022-05-11 삼성전자주식회사 Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2327146A (en) * 1997-07-10 1999-01-13 Ericsson Telefon Ab L M Thermal insulation of integrated circuit components
DE10115489A1 (en) * 2000-09-01 2002-03-28 Mitsubishi Electric Corp Semiconductor device e.g. MOSFET has gate insulating film consisting of deuterium atom content silicon nitride film and silicon oxide film
DE10144201A1 (en) * 2000-09-12 2002-04-25 Zarlink Semiconductor Ltd A semiconductor device
US20020113288A1 (en) * 1999-07-28 2002-08-22 Lawrence A. Clevenger Method and structure for providing improved thermal conduction for silicon semiconductor devices

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4604162A (en) * 1983-06-13 1986-08-05 Ncr Corporation Formation and planarization of silicon-on-insulator structures
US5270265A (en) * 1992-09-01 1993-12-14 Harris Corporation Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5811283A (en) * 1996-08-13 1998-09-22 United Microelectronics Corporation Silicon on insulator (SOI) dram cell structure and process
US6211039B1 (en) 1996-11-12 2001-04-03 Micron Technology, Inc. Silicon-on-insulator islands and method for their formation
US6045625A (en) * 1996-12-06 2000-04-04 Texas Instruments Incorporated Buried oxide with a thermal expansion matching layer for SOI
JP3676910B2 (en) * 1997-07-30 2005-07-27 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor device and method for forming semiconductor island
US6054343A (en) * 1998-01-26 2000-04-25 Texas Instruments Incorporated Nitride trench fill process for increasing shallow trench isolation (STI) robustness
JP2000294623A (en) * 1999-04-02 2000-10-20 Fuji Electric Co Ltd Manufacture of dielectric separating substrate
JP2000332099A (en) * 1999-05-21 2000-11-30 Matsushita Electronics Industry Corp Semiconductor device and manufacture thereof
US6245600B1 (en) * 1999-07-01 2001-06-12 International Business Machines Corporation Method and structure for SOI wafers to avoid electrostatic discharge
US6426252B1 (en) * 1999-10-25 2002-07-30 International Business Machines Corporation Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap
US20020046985A1 (en) * 2000-03-24 2002-04-25 Daneman Michael J. Process for creating an electrically isolated electrode on a sidewall of a cavity in a base
US6403482B1 (en) * 2000-06-28 2002-06-11 International Business Machines Corporation Self-aligned junction isolation
TW501227B (en) * 2000-08-11 2002-09-01 Samsung Electronics Co Ltd SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same
DE10040464A1 (en) * 2000-08-18 2002-02-28 Infineon Technologies Ag Trench capacitor and process for its manufacture
DE10054109C2 (en) * 2000-10-31 2003-07-10 Advanced Micro Devices Inc Method of forming a substrate contact in a field effect transistor formed over a buried insulating layer
US6506620B1 (en) * 2000-11-27 2003-01-14 Microscan Systems Incorporated Process for manufacturing micromechanical and microoptomechanical structures with backside metalization
US6524929B1 (en) * 2001-02-26 2003-02-25 Advanced Micro Devices, Inc. Method for shallow trench isolation using passivation material for trench bottom liner

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2327146A (en) * 1997-07-10 1999-01-13 Ericsson Telefon Ab L M Thermal insulation of integrated circuit components
US20020113288A1 (en) * 1999-07-28 2002-08-22 Lawrence A. Clevenger Method and structure for providing improved thermal conduction for silicon semiconductor devices
DE10115489A1 (en) * 2000-09-01 2002-03-28 Mitsubishi Electric Corp Semiconductor device e.g. MOSFET has gate insulating film consisting of deuterium atom content silicon nitride film and silicon oxide film
DE10144201A1 (en) * 2000-09-12 2002-04-25 Zarlink Semiconductor Ltd A semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1516362A2 *

Also Published As

Publication number Publication date
US20040018668A1 (en) 2004-01-29
TWI289895B (en) 2007-11-11
US6680240B1 (en) 2004-01-20
KR100996725B1 (en) 2010-11-25
JP4452883B2 (en) 2010-04-21
AU2003238916A1 (en) 2004-01-06
AU2003238916A8 (en) 2004-01-06
JP2005531144A (en) 2005-10-13
EP1516362A2 (en) 2005-03-23
TW200400564A (en) 2004-01-01
CN1333454C (en) 2007-08-22
WO2004001798A2 (en) 2003-12-31
CN1659696A (en) 2005-08-24
KR20050013248A (en) 2005-02-03

Similar Documents

Publication Publication Date Title
WO2004001798A3 (en) A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
EP1825509B1 (en) Method for fabricating dual stressed SOI substrates
WO2005050711A3 (en) A method for fabricating semiconductor devices using strained silicon bearing material
TW200503176A (en) High-performance CMOS SOI devices on hybrid crystal-oriented substrates
CN100388415C (en) Semiconductor materials and method of forming semiconductor materials
MY134036A (en) Method of forming strained silicon on insulator and structures formed thereby
WO2003069658A3 (en) Strained si based layer made by uhv-cvd, and devices therein
IL178387A (en) Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby
WO2005057612A3 (en) SILICON DEVICE ON Si:C-OI and SGOI AND METHOD OF MANUFACTURE
EP1583148A4 (en) Semiconductor device and its fabricating method
WO2005055290A3 (en) Method of fabricating a strained semiconductor-on-insulator substrate
WO2006007394A3 (en) Strained tri-channel layer for semiconductor-based electronic devices
JP2008536334A5 (en)
WO2004090201A3 (en) Method for the production of monocrystalline crystals
WO2004006327A3 (en) Transfer of a thin layer from a wafer comprising a buffer layer
WO2002013258A3 (en) Backside contact for integrated circuit and method of forming same
TW200640008A (en) Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices
AU2002368388A1 (en) Strained finfet cmos device structures
WO2006034189A3 (en) High-mobility bulk silicon pfet
EP1213748A3 (en) Semiconductor substrate and method for fabricating the same
EP1039513A3 (en) Method of producing a SOI wafer
EP0955681A3 (en) Optical semiconductor device and method of fabricating the same
TW200636822A (en) Structure and method for manufacturing strained silicon directly-on insulator substrate with hybrid crystalling orientation and different stress levels
WO2006017640B1 (en) Method of forming strained silicon materials with improved thermal conductivity
TW200631078A (en) A method of making a semiconductor structure for high power semiconductor devices

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003734436

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2003813263X

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2004515743

Country of ref document: JP

Ref document number: 1020047021192

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020047021192

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2003734436

Country of ref document: EP