WO2003094239A1 - Semiconductor device having strained silicon and silicon germanium alloy layers - Google Patents

Semiconductor device having strained silicon and silicon germanium alloy layers Download PDF

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Publication number
WO2003094239A1
WO2003094239A1 PCT/GB2003/001825 GB0301825W WO03094239A1 WO 2003094239 A1 WO2003094239 A1 WO 2003094239A1 GB 0301825 W GB0301825 W GB 0301825W WO 03094239 A1 WO03094239 A1 WO 03094239A1
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layer
silicon
conduction layer
conduction
substrate
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PCT/GB2003/001825
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French (fr)
Inventor
Anthony Gerard O'neill
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University Of Newcastle Upon Tyne
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Publication of WO2003094239A1 publication Critical patent/WO2003094239A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Definitions

  • the present invention relates to semiconductor devices, and relates particularly, but not exclusively to CMOS devices having strained silicon and silicon germanium alloy layers to provide channels for transistors.
  • NMOS transistors are known in which a silicon layer is grown on a layer of silicon-germanium alloy such that the silicon layer is under tensile strain.
  • the separation of atoms in pure silicon is less than in pure germanium, and when the silicon layer is grown on the silicon-germanium alloy layer, the separation of the silicon atoms therefore increases to follow the atomic arrangement of the underlying silicon-germanium layer.
  • the resulting silicon layer is under tension, and the tensile strain of the silicon layer improves the conductivity of electrons in the strained silicon. This phenomenon can be used to improve the speed of operation of NMOS transistors when the conduction channel is formed in the strained silicon layer.
  • PMOS devices are also known in which a silicon-germanium alloy layer with a higher density of germanium is grown on a silicon- germanium alloy layer having a lower germanium density.
  • the atoms of the silicon-germanium layer of higher germanium density are arranged closer together, as a result of which that silicon-germanium layer is placed under compressive strain.
  • This increases the conductivity of the layer to holes, which improves the speed of operation of PMOS transistors of which the hole conduction channels are formed in the silicon- germanium layer.
  • CMOS type devices which are the commonest type of microelectronic device, it is necessary to have both NMOS and PMOS transistors on the same device.
  • the problem arises that the performance of one type of transistor must generally be compromised to maximise the performance of the other type.
  • EP0683522 discloses a CMOS device incorporating NMOS transistors having an n-channel under tensile strain, and PMOS transistors having a p-channel under compressive strain.
  • the device of EP0683522 suffers from a number of drawbacks.
  • the object of the device of EP0683522 is specifically to create buried n-channel and p-channel layers and to remove carriers from the gate dielectric interface and to have the p-channel closer to the gate electrode than the n- channel. This unduly degrades the performance (e.g. transconductance) of n-channel transistors, which are crucial to high performance in CMOS circuits . Better performance is obtained with the n-channel at the gate dielectric interface.
  • the invention specifies a virtual substrate of silicon germanium having a germanium fraction between 0.2 - 0.5, which makes high temperature device processing problematic due to the high degree of strain incorporated within conducting layers .
  • Preferred embodiments of the present invention seek to overcome the above disadvantages of the prior art.
  • a semiconductor device comprising: -
  • first conduction layer formed on a first side of said substrate layer and comprising silicon-germanium alloy having a lattice constant in an unstrained state larger than that of said substrate layer such that said first conduction layer is under compressive strain, wherein said first conduction layer is adapted to have respective source and drain regions of at least one first field effect transistor formed therein;
  • a second conduction layer formed on a side of said first conduction layer remote from said substrate layer and comprising silicon, such that said second conduction layer is under tensile strain, wherein said second conduction layer is adapted to have respective source and drain regions of at least one second field effect transistor formed therein.
  • this provides the advantage of enabling the advantageous features of a surface n-channel device to be combined with the advantages of a buried p-channel device without having to compromise the performance of either type of device.
  • the device may further comprise an electrically insulating layer formed on a side of said second conduction layer remote from said first conduction layer, and respective gate electrodes of at least one said first and second field effect transistor formed on said electrically insulating layer.
  • the substrate layer may be provided on a silicon substrate.
  • the second conduction layer is preferably directly formed on said first conduction layer.
  • said first conduction layer further comprises respective source and drain regions of at least one p-channel field effect transistor.
  • said second conduction layer further comprises respective source and drain regions of at least one n-channel field effect transistor.
  • said substrate layer is silicon- germanium alloy having the formula Si ⁇ _ x Ge x , where x is between 0 and 0.25.
  • the first conduction layer may comprise silicon-germanium alloy having an average germanium density higher than that of said substrate layer.
  • said first conduction layer is formed directly on said substrate layer and comprises silicon- germanium alloy and has a thickness of at least 5 nm.
  • the substrate layer may comprise silicon-carbon alloy.
  • the device may further comprise respective gate regions of a plurality of said first and second field effect transistors arranged on a side of said second conduction layer remote from said first conduction layer, and an electrically insulating layer arranged between each said gate region and the second conduction layer.
  • Figures 1 to 6 are schematic cross-sectional views showing steps in the formation of a semiconductor device embodying the present invention.
  • CMOS complementary metal-oxide- silicon
  • a CMOS (complementary metal-oxide- silicon) heterojunction semiconductor device is formed by growing a virtual substrate 1 of silicon-germanium alloy on a silicon wafer 2, the silicon wafer 2 being in a relaxed state and the silicon-germanium alloy of the virtual substrate 1 having the formula Si ⁇ - x Ge x , where x varies between 0 and 0.25, and is typically 0.15.
  • a first conduction layer 3 of silicon-germanium alloy having the formula Si ⁇ _ y Ge y where y is less than x+0.3 is then grown on the relaxed silicon-germanium substrate 1. Because of the higher average germanium density in layer 3 compared with virtual substrate 1, the separation of atoms in layer 3 is less than in virtual substrate 1, as a result of which layer 3 is under compressive strain. As will be familiar to persons skilled in the art, this significantly increases the conductivity of the layer 3 to holes compared with a relaxed layer (i.e. not under compressive strain) of the same material.
  • a second conduction layer 4 of silicon is then grown on silicon-germanium alloy layer 3. Because the separation of silicon atoms is less than in silicon-germanium, the silicon layer 4 is placed under tensile stress, which significantly increases the conductivity of layer 4 to electrons.
  • the wafer is cleaned, and alignment marks are defined on the wafer for lithography steps.
  • the active area is then defined, and dielectric regions 5 are formed by low temperature processing to avoid diffusion of germanium from layer 3 into layer 4, which would degrade devices formed in silicon layer 4.
  • p-type 6 and n-type 7 wells are formed by a suitable technique such as ion implantation, the wells extending downwards into the virtual substrate 1.
  • the wells are intended to surround source and drain regions of transistors to be formed in the wafer.
  • Gate stacks, each of which comprises a gate oxide layer 8 and a polysilicon gate electrode 9 are formed by growing a continuous layer of gate oxide 8, depositing a continuous layer of polysilicon 9, and using lithographic techniques and etching to define the date region and then remove unwanted oxide and polysilicon. This arrangement is shown in Figure 3.
  • source 10 and drain 11 regions of an n-channel transistor are formed by ion implantation and annealing, the source and drain regions extending downwards into the virtual substrate 1.
  • source 12 and drain 13 regions of a p-channel transistor are formed.
  • a continuous dielectric layer 14 of BPSG boron phosphorous silica glass is deposited over the top surface of the wafer as shown in Figure 5.
  • contact windows are opened in dielectric layer 14 by lithography and etching, and metal for forming contacts to the gates, sources and drains of the transistors is deposited. The metal is then patterned using lithography and etched to leave source 15, gate 16 and drain 17 contacts respectively.

Abstract

A CMOS (complementary metal-oxide-silicon) heterojunction semiconductor device is formed by growing a virtual substrate (1) of silicon-germanium alloy on a silicon wafer (2), the silicon wafer (2) being in a relaxed state and the silicon-germanium alloy of the virtual substrate (1) having the formula Si1-xGex, where x varies between 0 and 0.25, and is typically 0.15. A first conduction layer (3) of silicon-germanium alloy having the formula Si1-yGey, where y is less than x+0.3 is then grown on the relaxed silicon-germanium substrate (1). Because of the higher average germanium density in first conduction layer (3) compared with virtual substrate (1), the separation of atoms in layer (3) is less than in virtual substrate (1), as a result of which layer (3) is under compressive strain. This significantly increases the conductivity of the layer (3) to holes compared with a relaxed layer (i.e. not under compressive strain) of the same material. A second conduction layer (4) of silicon is then grown on silicon-germanium alloy layer (3). Because the separation of silicon atoms is less than in silicon-germanium, the silicon layer (4) is placed under tensile stress, which significantly increases the conductivity of layer (4) to electrons.

Description

SE ICO DUCTOR DEVICE HAVING STRAINED SILICON AND SILICON- GERMANIUM ALLOY LAYERS
The present invention relates to semiconductor devices, and relates particularly, but not exclusively to CMOS devices having strained silicon and silicon germanium alloy layers to provide channels for transistors.
NMOS transistors are known in which a silicon layer is grown on a layer of silicon-germanium alloy such that the silicon layer is under tensile strain. The separation of atoms in pure silicon is less than in pure germanium, and when the silicon layer is grown on the silicon-germanium alloy layer, the separation of the silicon atoms therefore increases to follow the atomic arrangement of the underlying silicon-germanium layer. The resulting silicon layer is under tension, and the tensile strain of the silicon layer improves the conductivity of electrons in the strained silicon. This phenomenon can be used to improve the speed of operation of NMOS transistors when the conduction channel is formed in the strained silicon layer.
PMOS devices are also known in which a silicon-germanium alloy layer with a higher density of germanium is grown on a silicon- germanium alloy layer having a lower germanium density. In a manner similar to the formation of a strained silicon layer, the atoms of the silicon-germanium layer of higher germanium density are arranged closer together, as a result of which that silicon-germanium layer is placed under compressive strain. This increases the conductivity of the layer to holes, which improves the speed of operation of PMOS transistors of which the hole conduction channels are formed in the silicon- germanium layer. In CMOS type devices, which are the commonest type of microelectronic device, it is necessary to have both NMOS and PMOS transistors on the same device. However, when an attempt is made to integrate the NMOS and PMOS transistors of the above type in a single device, the problem arises that the performance of one type of transistor must generally be compromised to maximise the performance of the other type.
EP0683522 discloses a CMOS device incorporating NMOS transistors having an n-channel under tensile strain, and PMOS transistors having a p-channel under compressive strain. However, the device of EP0683522 suffers from a number of drawbacks. The object of the device of EP0683522 is specifically to create buried n-channel and p-channel layers and to remove carriers from the gate dielectric interface and to have the p-channel closer to the gate electrode than the n- channel. This unduly degrades the performance (e.g. transconductance) of n-channel transistors, which are crucial to high performance in CMOS circuits . Better performance is obtained with the n-channel at the gate dielectric interface. Moreover, the invention specifies a virtual substrate of silicon germanium having a germanium fraction between 0.2 - 0.5, which makes high temperature device processing problematic due to the high degree of strain incorporated within conducting layers .
Preferred embodiments of the present invention seek to overcome the above disadvantages of the prior art.
According to the present invention, there is provided a semiconductor device comprising: -
a substrate layer of semiconductor material having a lattice constant larger than that of pure silicon;
a first conduction layer formed on a first side of said substrate layer and comprising silicon-germanium alloy having a lattice constant in an unstrained state larger than that of said substrate layer such that said first conduction layer is under compressive strain, wherein said first conduction layer is adapted to have respective source and drain regions of at least one first field effect transistor formed therein; and
a second conduction layer formed on a side of said first conduction layer remote from said substrate layer and comprising silicon, such that said second conduction layer is under tensile strain, wherein said second conduction layer is adapted to have respective source and drain regions of at least one second field effect transistor formed therein.
By providing a compressed layer for the formation of hole channels and a layer under tensile strain for the formation of electron channels such that the layer under tensile strain is located on a side of the compressed layer remote from the substrate layer, this provides the advantage of enabling the advantageous features of a surface n-channel device to be combined with the advantages of a buried p-channel device without having to compromise the performance of either type of device.
The device may further comprise an electrically insulating layer formed on a side of said second conduction layer remote from said first conduction layer, and respective gate electrodes of at least one said first and second field effect transistor formed on said electrically insulating layer.
The substrate layer may be provided on a silicon substrate.
The second conduction layer is preferably directly formed on said first conduction layer.
This provides the advantage that the compressive strain in the first conduction layer is compensated by the tensile strain in the second conduction layer, as a result of which the strain in each layer can be higher, thus improving the conductivity of each layer to charge carriers of the appropriate polarity for that layer.
In a preferred embodiment, said first conduction layer further comprises respective source and drain regions of at least one p-channel field effect transistor.
In a preferred embodiment, said second conduction layer further comprises respective source and drain regions of at least one n-channel field effect transistor.
In a preferred embodiment, said substrate layer is silicon- germanium alloy having the formula Siι_xGex , where x is between 0 and 0.25.
The first conduction layer may comprise silicon-germanium alloy having an average germanium density higher than that of said substrate layer.
In a preferred embodiment, said first conduction layer is formed directly on said substrate layer and comprises silicon- germanium alloy and has a thickness of at least 5 nm.
The substrate layer may comprise silicon-carbon alloy.
The device may further comprise respective gate regions of a plurality of said first and second field effect transistors arranged on a side of said second conduction layer remote from said first conduction layer, and an electrically insulating layer arranged between each said gate region and the second conduction layer. A preferred embodiment of the invention will now be described, by way of example only and not in any limitative sense, with reference to the accompanying drawings, in which: -
Figures 1 to 6 are schematic cross-sectional views showing steps in the formation of a semiconductor device embodying the present invention.
Referring to Figure 1, a CMOS (complementary metal-oxide- silicon) heterojunction semiconductor device is formed by growing a virtual substrate 1 of silicon-germanium alloy on a silicon wafer 2, the silicon wafer 2 being in a relaxed state and the silicon-germanium alloy of the virtual substrate 1 having the formula Siι-xGex, where x varies between 0 and 0.25, and is typically 0.15.
A first conduction layer 3 of silicon-germanium alloy having the formula Siι_yGey where y is less than x+0.3 is then grown on the relaxed silicon-germanium substrate 1. Because of the higher average germanium density in layer 3 compared with virtual substrate 1, the separation of atoms in layer 3 is less than in virtual substrate 1, as a result of which layer 3 is under compressive strain. As will be familiar to persons skilled in the art, this significantly increases the conductivity of the layer 3 to holes compared with a relaxed layer (i.e. not under compressive strain) of the same material.
A second conduction layer 4 of silicon is then grown on silicon-germanium alloy layer 3. Because the separation of silicon atoms is less than in silicon-germanium, the silicon layer 4 is placed under tensile stress, which significantly increases the conductivity of layer 4 to electrons.
In order to isolate neighbouring devices to be formed in the wafer from each other, the wafer is cleaned, and alignment marks are defined on the wafer for lithography steps. The active area is then defined, and dielectric regions 5 are formed by low temperature processing to avoid diffusion of germanium from layer 3 into layer 4, which would degrade devices formed in silicon layer 4.
Referring now to Figure 2, p-type 6 and n-type 7 wells are formed by a suitable technique such as ion implantation, the wells extending downwards into the virtual substrate 1. The wells are intended to surround source and drain regions of transistors to be formed in the wafer. Gate stacks, each of which comprises a gate oxide layer 8 and a polysilicon gate electrode 9 are formed by growing a continuous layer of gate oxide 8, depositing a continuous layer of polysilicon 9, and using lithographic techniques and etching to define the date region and then remove unwanted oxide and polysilicon. This arrangement is shown in Figure 3.
Referring now to Figure 4, source 10 and drain 11 regions of an n-channel transistor are formed by ion implantation and annealing, the source and drain regions extending downwards into the virtual substrate 1. Similarly, source 12 and drain 13 regions of a p-channel transistor are formed. At the end of this process, a continuous dielectric layer 14 of BPSG (boron phosphorous silica glass) is deposited over the top surface of the wafer as shown in Figure 5.
Finally, referring to Figure 6, contact windows are opened in dielectric layer 14 by lithography and etching, and metal for forming contacts to the gates, sources and drains of the transistors is deposited. The metal is then patterned using lithography and etched to leave source 15, gate 16 and drain 17 contacts respectively. It will be appreciated by persons skilled in the art that the above embodiment has been described by way of example only, and not in any limitative sense, and that various alterations and modifications are possible without departure from the scope of protection as defined by the appended claims. For example, instead of forming the silicon-germanium layer 3 directly on virtual substrate 1, an intermediate layer may be interposed between layer 3 and virtual substrate 1. Similarly, instead of forming tensilely strained silicon layer 4 directly on layer 3, an intermediate layer may be interposed between layers 4 and 3.

Claims

1. A semiconductor device comprising: -
a substrate layer of semiconductor material having a lattice constant larger than that of pure silicon;
a first conduction layer formed on a first side of said substrate layer and comprising silicon-germanium alloy having a lattice constant in an unstrained state larger than that of said substrate layer such that said first conduction layer is under compressive strain, wherein said first conduction layer is adapted to have respective source and drain regions of at least one first field effect transistor formed therein; and
a second conduction layer formed on a side of said first conduction layer remote from said substrate layer and comprising silicon, such that said second conduction layer is under tensile strain, wherein said second conduction layer is adapted to have respective source and drain regions of at least one second field effect transistor formed therein.
2. A device according to claim 1, further comprising an electrically insulating layer formed on a side of said second conduction layer remote from said first conduction layer, and respective gate electrodes of at least one said first and second field effect transistor formed on said electrically insulating layer.
3. A device according to claim 1 or 2, wherein the substrate layer is provided on a silicon substrate.
4. A device according to any one of the preceding claims, wherein the second conduction layer is directly formed on said first conduction layer.
5. A device according to any one of the preceding claims, wherein said first conduction layer further comprises respective source and drain regions of at least one p-channel field effect transistor.
6. A device according to any one of the preceding claims, wherein said second conduction layer further comprises respective source and drain regions of at least one n-channel field effect transistor.
7. A device according to any one of the preceding claims, wherein said substrate layer is silicon-germanium alloy having the formula Siι-xGex , where x is between 0 and 0.25.
8. A device according to any one of the preceding claims, wherein the first conduction layer comprises silicon-germanium alloy having an average germanium density higher than that of said substrate layer.
9. A device according to claim 8, wherein said first conduction layer is formed directly on said substrate layer and comprises silicon-germanium alloy and has a thickness of at least 5 nm.
10. A device according to any one of the preceding claims, wherein the substrate layer comprises silicon-carbon alloy.
11. A device according to any one of the preceding claims, further comprising respective gate regions of a plurality of said first and second field effect transistors arranged on a side of said second conduction layer remote from said first conduction layer, and an electrically insulating layer arranged between each said gate region and the second conduction layer.
12. A semiconductor device substantially as hereinbefore described with reference to the accompanying drawings.
PCT/GB2003/001825 2002-04-29 2003-04-28 Semiconductor device having strained silicon and silicon germanium alloy layers WO2003094239A1 (en)

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WO2006006972A1 (en) * 2004-06-24 2006-01-19 International Business Machines Corporation Improved strained-silicon cmos device and method
US7495266B2 (en) * 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
US7808081B2 (en) 2004-08-31 2010-10-05 International Business Machines Corporation Strained-silicon CMOS device and method

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