WO2002069380A3 - Atomically thin highly resistive barrier layer in a copper via - Google Patents

Atomically thin highly resistive barrier layer in a copper via Download PDF

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Publication number
WO2002069380A3
WO2002069380A3 PCT/US2002/005576 US0205576W WO02069380A3 WO 2002069380 A3 WO2002069380 A3 WO 2002069380A3 US 0205576 W US0205576 W US 0205576W WO 02069380 A3 WO02069380 A3 WO 02069380A3
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WO
WIPO (PCT)
Prior art keywords
copper
via hole
barrier layer
layer
deposited
Prior art date
Application number
PCT/US2002/005576
Other languages
French (fr)
Other versions
WO2002069380A2 (en
Inventor
Fusen Chen
Ling Chen
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to JP2002568407A priority Critical patent/JP2004531053A/en
Publication of WO2002069380A2 publication Critical patent/WO2002069380A2/en
Publication of WO2002069380A3 publication Critical patent/WO2002069380A3/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844Bottomless liners
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/16Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/3407Cathode assembly for sputtering apparatus, e.g. Target
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865Selective removal of parts of the layer
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/26Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
    • Y10T428/263Coating layer not in excess of 5 mils thick or equivalent
    • Y10T428/264Up to 3 mils
    • Y10T428/2651 mil or less

Abstract

A method of forming a copper via and the resultant structure. A thin layer of an insulating barrier material (30), such as aluminum oxide or tantalum nitride, is conformally coated onto the sides and bottom of the via hole, for example, by atomic layer deposition (ALD) to a thickness of less than 5nm, preferably less than 2nm and having an electrical resistivity of more than 500 microohm-cm. A copper seed layer (40) is then deposited under conditions such that copper is deposited on the via sidewalls but not deposited over most of the bottom of via hole. Instead energetic copper ions sputter the barrier material from the via bottom. Copper (50) is electroplated into the via hole lined only on its sidewalls with the barrier. The invention preferably extends also to dual-damascene structures in which the copper seed sputter process sputters the barrier layer from the via bottom but not the trench floor.
PCT/US2002/005576 2001-02-23 2002-02-25 Atomically thin highly resistive barrier layer in a copper via WO2002069380A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002568407A JP2004531053A (en) 2001-02-23 2002-02-25 High resistance barrier atomic thin layers in copper vias

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/792,737 2001-02-23
US09/792,737 US20020117399A1 (en) 2001-02-23 2001-02-23 Atomically thin highly resistive barrier layer in a copper via

Publications (2)

Publication Number Publication Date
WO2002069380A2 WO2002069380A2 (en) 2002-09-06
WO2002069380A3 true WO2002069380A3 (en) 2003-02-06

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US (1) US20020117399A1 (en)
JP (1) JP2004531053A (en)
WO (1) WO2002069380A2 (en)

Families Citing this family (128)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6974766B1 (en) 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
US6156743A (en) * 1999-10-18 2000-12-05 Whitcomb; John E. Method of decreasing fatigue
US6620723B1 (en) 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
US6936538B2 (en) 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US7732327B2 (en) 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US7405158B2 (en) 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US6551929B1 (en) 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US7101795B1 (en) 2000-06-28 2006-09-05 Applied Materials, Inc. Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US6596643B2 (en) * 2001-05-07 2003-07-22 Applied Materials, Inc. CVD TiSiN barrier for copper integration
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US6849545B2 (en) * 2001-06-20 2005-02-01 Applied Materials, Inc. System and method to form a composite film stack utilizing sequential deposition techniques
KR100400252B1 (en) * 2001-06-29 2003-10-01 주식회사 하이닉스반도체 Method for manufacturing Tantalium Oxide capacitor
US7211144B2 (en) 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
TW581822B (en) 2001-07-16 2004-04-01 Applied Materials Inc Formation of composite tungsten films
US20090004850A1 (en) 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US9051641B2 (en) 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US8110489B2 (en) 2001-07-25 2012-02-07 Applied Materials, Inc. Process for forming cobalt-containing materials
TW589684B (en) * 2001-10-10 2004-06-01 Applied Materials Inc Method for depositing refractory metal layers employing sequential deposition techniques
US7780785B2 (en) 2001-10-26 2010-08-24 Applied Materials, Inc. Gas delivery apparatus for atomic layer deposition
US6916398B2 (en) 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
US7081271B2 (en) 2001-12-07 2006-07-25 Applied Materials, Inc. Cyclical deposition of refractory metal silicon nitride
US6809026B2 (en) 2001-12-21 2004-10-26 Applied Materials, Inc. Selective deposition of a barrier layer on a metal film
WO2003065424A2 (en) 2002-01-25 2003-08-07 Applied Materials, Inc. Apparatus for cyclical deposition of thin films
US6998014B2 (en) 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US6911391B2 (en) 2002-01-26 2005-06-28 Applied Materials, Inc. Integration of titanium and titanium nitride layers
US6827978B2 (en) 2002-02-11 2004-12-07 Applied Materials, Inc. Deposition of tungsten films
US6833161B2 (en) 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US6972267B2 (en) 2002-03-04 2005-12-06 Applied Materials, Inc. Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US6720027B2 (en) * 2002-04-08 2004-04-13 Applied Materials, Inc. Cyclical deposition of a variable content titanium silicon nitride layer
US7279432B2 (en) * 2002-04-16 2007-10-09 Applied Materials, Inc. System and method for forming an integrated barrier layer
US20040033371A1 (en) * 2002-05-16 2004-02-19 Hacker Nigel P. Deposition of organosilsesquioxane films
US7186385B2 (en) 2002-07-17 2007-03-06 Applied Materials, Inc. Apparatus for providing gas to a processing chamber
DE10240106A1 (en) * 2002-08-30 2004-03-11 Infineon Technologies Ag Forming an electrical connection between structures in a semiconductor substrate
US7005375B2 (en) * 2002-09-30 2006-02-28 Agere Systems Inc. Method to avoid copper contamination of a via or dual damascene structure
US6821563B2 (en) 2002-10-02 2004-11-23 Applied Materials, Inc. Gas distribution system for cyclical layer deposition
WO2004040642A1 (en) * 2002-10-29 2004-05-13 Asm America, Inc. Oxygen bridge structures and methods
US20040152330A1 (en) * 2002-11-04 2004-08-05 Applied Materials, Inc. Tunneling barrier for a copper damascene via
US6869876B2 (en) 2002-11-05 2005-03-22 Air Products And Chemicals, Inc. Process for atomic layer deposition of metal films
US7262133B2 (en) * 2003-01-07 2007-08-28 Applied Materials, Inc. Enhancement of copper line reliability using thin ALD tan film to cap the copper line
KR100538806B1 (en) * 2003-02-21 2005-12-26 주식회사 하이닉스반도체 SEMICONDUCTOR DEVICE WITH EPITAXIAL C49-TiSi2 LAYER AND METHOD FOR FABRICATING THE SAME
US20040175926A1 (en) * 2003-03-07 2004-09-09 Advanced Micro Devices, Inc. Method for manufacturing a semiconductor component having a barrier-lined opening
US6835664B1 (en) * 2003-06-26 2004-12-28 Micron Technology, Inc. Methods of forming trenched isolation regions
US7101785B2 (en) * 2003-07-22 2006-09-05 Infineon Technologies Ag Formation of a contact in a device, and the device including the contact
FR2859822B1 (en) * 2003-09-16 2006-05-05 Commissariat Energie Atomique INTERCONNECTION STRUCTURE WITH LOW DIELECTRIC CONSTANT
US7166528B2 (en) 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US20050109276A1 (en) * 2003-11-25 2005-05-26 Applied Materials, Inc. Thermal chemical vapor deposition of silicon nitride using BTBAS bis(tertiary-butylamino silane) in a single wafer chamber
US20050252449A1 (en) 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US8323754B2 (en) 2004-05-21 2012-12-04 Applied Materials, Inc. Stabilization of high-k dielectric materials
US7211507B2 (en) * 2004-06-02 2007-05-01 International Business Machines Corporation PE-ALD of TaN diffusion barrier region on low-k materials
EP1783832A4 (en) * 2004-07-06 2008-07-09 Tokyo Electron Ltd Interposer and interposer producing method
KR100858075B1 (en) * 2004-07-06 2008-09-11 도쿄엘렉트론가부시키가이샤 Interposer
US7241686B2 (en) * 2004-07-20 2007-07-10 Applied Materials, Inc. Atomic layer deposition of tantalum-containing materials using the tantalum precursor TAIMATA
US20060019032A1 (en) * 2004-07-23 2006-01-26 Yaxin Wang Low thermal budget silicon nitride formation for advance transistor fabrication
US7083425B2 (en) 2004-08-27 2006-08-01 Micron Technology, Inc. Slanted vias for electrical circuits on circuit boards and other substrates
US20060084283A1 (en) * 2004-10-20 2006-04-20 Paranjpe Ajit P Low temperature sin deposition methods
CN100364057C (en) * 2004-11-24 2008-01-23 中芯国际集成电路制造(上海)有限公司 Method and system for metal barrier and crystal seed integration
US7312128B2 (en) * 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
US7560352B2 (en) * 2004-12-01 2009-07-14 Applied Materials, Inc. Selective deposition
US7682940B2 (en) * 2004-12-01 2010-03-23 Applied Materials, Inc. Use of Cl2 and/or HCl during silicon epitaxial film formation
KR100668833B1 (en) * 2004-12-17 2007-01-16 주식회사 하이닉스반도체 Emthod for fabricating capacitor in semiconductor device
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20070271751A1 (en) * 2005-01-27 2007-11-29 Weidman Timothy W Method of forming a reliable electrochemical capacitor
US20060162658A1 (en) * 2005-01-27 2006-07-27 Applied Materials, Inc. Ruthenium layer deposition apparatus and method
US7235492B2 (en) 2005-01-31 2007-06-26 Applied Materials, Inc. Low temperature etchant for treatment of silicon-containing surfaces
US7332428B2 (en) * 2005-02-28 2008-02-19 Infineon Technologies Ag Metal interconnect structure and method
KR100676597B1 (en) * 2005-02-28 2007-01-30 주식회사 하이닉스반도체 Method for fabricating flash memory device
DE102005024914A1 (en) * 2005-05-31 2006-12-07 Advanced Micro Devices, Inc., Sunnyvale Method for forming electrically conductive lines in an integrated circuit
US7648927B2 (en) 2005-06-21 2010-01-19 Applied Materials, Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
US7651955B2 (en) * 2005-06-21 2010-01-26 Applied Materials, Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
US20060286774A1 (en) * 2005-06-21 2006-12-21 Applied Materials. Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
US7262134B2 (en) * 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7704878B2 (en) * 2005-10-03 2010-04-27 Advanced Micro Devices, Inc, Contact spacer formation using atomic layer deposition
TWI332532B (en) 2005-11-04 2010-11-01 Applied Materials Inc Apparatus and process for plasma-enhanced atomic layer deposition
US7674337B2 (en) * 2006-04-07 2010-03-09 Applied Materials, Inc. Gas manifolds for use during epitaxial film formation
US7798096B2 (en) 2006-05-05 2010-09-21 Applied Materials, Inc. Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool
US7501355B2 (en) * 2006-06-29 2009-03-10 Applied Materials, Inc. Decreasing the etch rate of silicon nitride by carbon addition
CN101496153A (en) 2006-07-31 2009-07-29 应用材料股份有限公司 Methods of forming carbon-containing silicon epitaxial layers
JP5175285B2 (en) * 2006-07-31 2013-04-03 アプライド マテリアルズ インコーポレイテッド Method for controlling morphology during epitaxial layer formation
DE102006056626A1 (en) * 2006-11-30 2008-06-05 Advanced Micro Devices, Inc., Sunnyvale Conductive barrier layer producing method for manufacturing integrated circuit, involves depositing layer on exposed surfaces by self-restricted deposition technique, and providing surface with characteristics at reduced deposition rate
US20080145536A1 (en) * 2006-12-13 2008-06-19 Applied Materials, Inc. METHOD AND APPARATUS FOR LOW TEMPERATURE AND LOW K SiBN DEPOSITION
KR100790452B1 (en) * 2006-12-28 2008-01-03 주식회사 하이닉스반도체 Method for forming multi layer metal wiring of semiconductor device using damascene process
DE102007004860B4 (en) * 2007-01-31 2008-11-06 Advanced Micro Devices, Inc., Sunnyvale A method of making a copper-based metallization layer having a conductive overcoat by an improved integration scheme
US8202798B2 (en) 2007-09-20 2012-06-19 Freescale Semiconductor, Inc. Improvements for reducing electromigration effect in an integrated circuit
US7678298B2 (en) 2007-09-25 2010-03-16 Applied Materials, Inc. Tantalum carbide nitride materials by vapor deposition processes
US7824743B2 (en) 2007-09-28 2010-11-02 Applied Materials, Inc. Deposition processes for titanium nitride barrier and aluminum
US7659158B2 (en) 2008-03-31 2010-02-09 Applied Materials, Inc. Atomic layer deposition processes for non-volatile memory devices
KR20090116168A (en) * 2008-05-06 2009-11-11 삼성전자주식회사 Metal line substrate, thin film transistor substrate, and method of forming metal line
US20100062149A1 (en) 2008-09-08 2010-03-11 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
US8491967B2 (en) 2008-09-08 2013-07-23 Applied Materials, Inc. In-situ chamber treatment and deposition process
US8146896B2 (en) 2008-10-31 2012-04-03 Applied Materials, Inc. Chemical precursor ampoule for vapor deposition processes
EP2415086B1 (en) * 2009-04-03 2019-02-27 OSRAM Opto Semiconductors GmbH Method for producing an optoelectronic component, optoelectronic component, and component arrangement having a plurality of optoelectronic components
US20100267230A1 (en) * 2009-04-16 2010-10-21 Anand Chandrashekar Method for forming tungsten contacts and interconnects with small critical dimensions
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8709948B2 (en) * 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
US20120273949A1 (en) * 2011-04-27 2012-11-01 Globalfoundries Singapore Pte. Ltd. Method of forming oxide encapsulated conductive features
CN113862634A (en) 2012-03-27 2021-12-31 诺发系统公司 Tungsten feature fill
US20140046475A1 (en) * 2012-08-09 2014-02-13 Applied Materials, Inc. Method and apparatus deposition process synchronization
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
CN102832199A (en) * 2012-09-25 2012-12-19 复旦大学 Mixed-media copper-diffusion-resistant blocking layer for copper interconnection and fabrication method of blocking layer
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9472415B2 (en) * 2014-04-30 2016-10-18 International Business Machines Corporation Directional chemical oxide etch technique
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US10312181B2 (en) 2016-05-27 2019-06-04 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US10396012B2 (en) * 2016-05-27 2019-08-27 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
CN107369706A (en) * 2017-07-17 2017-11-21 华南理工大学 One kind display electronic device copper alloy electrode and preparation method thereof
US11348795B2 (en) 2017-08-14 2022-05-31 Lam Research Corporation Metal fill process for three-dimensional vertical NAND wordline
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
US11033930B2 (en) 2018-01-08 2021-06-15 Applied Materials, Inc. Methods and apparatus for cryogenic gas stream assisted SAM-based selective deposition
SG11202008268RA (en) 2018-03-19 2020-10-29 Applied Materials Inc Methods for depositing coatings on aerospace components
EP3784815A4 (en) 2018-04-27 2021-11-03 Applied Materials, Inc. Protection of components from corrosion
CN112262457A (en) 2018-05-03 2021-01-22 朗姆研究公司 Methods of depositing tungsten and other metals in 3D NAND structures
US11009339B2 (en) 2018-08-23 2021-05-18 Applied Materials, Inc. Measurement of thickness of thermal barrier coatings using 3D imaging and surface subtraction methods for objects with complex geometries
US10636705B1 (en) 2018-11-29 2020-04-28 Applied Materials, Inc. High pressure annealing of metal gate structures
WO2020219332A1 (en) 2019-04-26 2020-10-29 Applied Materials, Inc. Methods of protecting aerospace components against corrosion and oxidation
US11794382B2 (en) 2019-05-16 2023-10-24 Applied Materials, Inc. Methods for depositing anti-coking protective coatings on aerospace components
US11697879B2 (en) 2019-06-14 2023-07-11 Applied Materials, Inc. Methods for depositing sacrificial coatings on aerospace components
US11466364B2 (en) 2019-09-06 2022-10-11 Applied Materials, Inc. Methods for forming protective coatings containing crystallized aluminum oxide
US11519066B2 (en) 2020-05-21 2022-12-06 Applied Materials, Inc. Nitride protective coatings on aerospace components and methods for making the same
WO2022005696A1 (en) 2020-07-03 2022-01-06 Applied Materials, Inc. Methods for refurbishing aerospace components
US11634830B2 (en) * 2021-08-25 2023-04-25 Applied Materials, Inc. Electrochemical depositions of nanotwin copper materials

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
US6008117A (en) * 1996-03-29 1999-12-28 Texas Instruments Incorporated Method of forming diffusion barriers encapsulating copper
KR20000002928A (en) * 1998-06-24 2000-01-15 윤종용 Metal wiring structure of semiconductor device and production method thereof
US6040243A (en) * 1999-09-20 2000-03-21 Chartered Semiconductor Manufacturing Ltd. Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
TW389991B (en) * 1998-09-04 2000-05-11 United Microelectronics Corp Method for producing copper interconnect
US6077774A (en) * 1996-03-29 2000-06-20 Texas Instruments Incorporated Method of forming ultra-thin and conformal diffusion barriers encapsulating copper

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008117A (en) * 1996-03-29 1999-12-28 Texas Instruments Incorporated Method of forming diffusion barriers encapsulating copper
US6077774A (en) * 1996-03-29 2000-06-20 Texas Instruments Incorporated Method of forming ultra-thin and conformal diffusion barriers encapsulating copper
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
KR20000002928A (en) * 1998-06-24 2000-01-15 윤종용 Metal wiring structure of semiconductor device and production method thereof
US6333260B1 (en) * 1998-06-24 2001-12-25 Samsung Electronics Co., Ltd. Semiconductor device having improved metal line structure and manufacturing method therefor
TW389991B (en) * 1998-09-04 2000-05-11 United Microelectronics Corp Method for producing copper interconnect
US6265313B1 (en) * 1998-09-04 2001-07-24 United Microelectronics Corp. Method of manufacturing copper interconnect
US6040243A (en) * 1999-09-20 2000-03-21 Chartered Semiconductor Manufacturing Ltd. Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
DATABASE WPI Section Ch Week 200065, Derwent World Patents Index; Class L03, AN 2000-670923, XP002215053 *
DATABASE WPI Section Ch Week 200067, Derwent World Patents Index; Class L03, AN 2000-685762, XP002217771 *
RITALA M ET AL: "PERFECTLY CONFORMAL TIN AND AL2O3 FILMS DEPOSITED BY ATOMIC LAYER DEPOSITION", CHEMICAL VAPOR DEPOSITION, VCH PUBLISHERS, WEINHEIM, DE, vol. 5, no. 1, January 1999 (1999-01-01), pages 7 - 9, XP000803200, ISSN: 0948-1907 *
ROSSNAGEL S M ET AL: "Plasma-enhanced atomic layer deposition of Ta and Ti for interconnect diffusion barriers", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 18, no. 4, 2000, pages 2016 - 2020, XP002215505, ISSN: 0734-211X *

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