WO2002029887A3 - One-step etch processes for dual damascene metallization - Google Patents

One-step etch processes for dual damascene metallization Download PDF

Info

Publication number
WO2002029887A3
WO2002029887A3 PCT/US2001/026998 US0126998W WO0229887A3 WO 2002029887 A3 WO2002029887 A3 WO 2002029887A3 US 0126998 W US0126998 W US 0126998W WO 0229887 A3 WO0229887 A3 WO 0229887A3
Authority
WO
WIPO (PCT)
Prior art keywords
resist layer
dual damascene
dielectric layer
etch processes
layer
Prior art date
Application number
PCT/US2001/026998
Other languages
French (fr)
Other versions
WO2002029887A2 (en
Inventor
Zhijian Lu
Xian J Ning
Xiaoming Yin
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Publication of WO2002029887A2 publication Critical patent/WO2002029887A2/en
Publication of WO2002029887A3 publication Critical patent/WO2002029887A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch

Abstract

A method for forming a dual damascene structure, employs the steps of forming a dielectric layer (14), patterning a first resist layer (16) on the dielectric layer to form a via pattern (26) and patterning a second resist layer (28) to form a line pattern (38) in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern. The first resist layer, the second resist layer and the dielectric layer are etched such that the dielectric layer has a via (40) formed therein which gets deeper during the etching process. The dielectric layer has a trench (42) formed therein in communication with the via which gets deeper after the exposed portions of the first resist layer are consumed by the etching process.
PCT/US2001/026998 2000-09-29 2001-08-30 One-step etch processes for dual damascene metallization WO2002029887A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67582700A 2000-09-29 2000-09-29
US09/675,827 2000-09-29

Publications (2)

Publication Number Publication Date
WO2002029887A2 WO2002029887A2 (en) 2002-04-11
WO2002029887A3 true WO2002029887A3 (en) 2003-02-06

Family

ID=24712121

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/026998 WO2002029887A2 (en) 2000-09-29 2001-08-30 One-step etch processes for dual damascene metallization

Country Status (1)

Country Link
WO (1) WO2002029887A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10233209A1 (en) * 2002-07-22 2004-02-05 Infineon Technologies Ag Irradiating resist during the production of integrated switching arrangement comprises forming radiation-sensitive resist layer arrangement after producing layer to be structured and irradiating the resist layer arrangement

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US5369061A (en) * 1992-06-16 1994-11-29 Sony Corporation Method of producing semiconductor device using a hydrogen-enriched layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US5369061A (en) * 1992-06-16 1994-11-29 Sony Corporation Method of producing semiconductor device using a hydrogen-enriched layer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"METHOD TO CONTROL DEPTH OF ETCHING", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 35, no. 3, 1 August 1992 (1992-08-01), pages 29 - 30, XP000326155, ISSN: 0018-8689 *
"METHOD TO INCORPORATE THREE SETS OF PATTERN INFORMATION IN TWO PHOTO-MASKING STEPS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 32, no. 8A, January 1990 (1990-01-01), pages 218 - 219, XP000082778, ISSN: 0018-8689 *

Also Published As

Publication number Publication date
WO2002029887A2 (en) 2002-04-11

Similar Documents

Publication Publication Date Title
WO2004061916A3 (en) Method of forming a low-k dual damascene interconnect structure
MY117201A (en) Process for self-alignment of sub-critical contacts to wiring
WO2005060548A3 (en) Method of preventing damage to porous low-k materials during resist stripping
TW200633000A (en) Method for forming dual damascene structure with tapered via portion and improved performance
TW368741B (en) Manufacturing method for dual damascene
SG125881A1 (en) Define via in dual damascene process
TW200606998A (en) Method of making dual damascene with via etch through
WO2001015219A3 (en) Method for producing an integrated circuit having at least one metalicized surface
WO2002029887A3 (en) One-step etch processes for dual damascene metallization
TW348276B (en) Method of forming a tungsten plug in a semiconductor device
KR20000004334A (en) Method of forming metal wire in semiconductor device
TW428299B (en) Metal plug forming method
TW337608B (en) Process for producing unlanded via
KR100268935B1 (en) Method for forming plug of semiconductor device
KR100390941B1 (en) Method of forming a dual damascene pattern in a semiconductor device
TW429572B (en) Manufacturing method of dual damascene structure
KR100462758B1 (en) Photo process for copper dual damascene
KR100317327B1 (en) Method for Manufacturing of Semiconductor Device
KR100425935B1 (en) Method for forming a contact hole in a semiconductor device
TW368732B (en) Manufacturing method for integrated circuit dual damascene
KR100231482B1 (en) Method of forming contact hole of semiconductor device
KR20050034029A (en) Method for forming metal line of semiconductor device
KR20020002678A (en) Method for forming metal line
KR930011116A (en) Manufacturing Method of Semiconductor Device
WO1999054929A3 (en) A method for manufacturing an electronic device comprising an organic-containing material

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP