WO2002029887A2

WO2002029887A2 - One-step etch processes for dual damascene metallization

Info

Publication number: WO2002029887A2
Application number: PCT/US2001/026998
Authority: WO
Inventors: Zhijian Lu; Xian J. Ning; Xiaoming Yin
Original assignee: Infineon Technologies North America Corp.
Priority date: 2000-09-29
Filing date: 2001-08-30
Publication date: 2002-04-11
Also published as: WO2002029887A3

Abstract

A method for forming a dual damascene structure, employs the steps of forming a dielectric layer (14), patterning a first resist layer (16) on the dielectric layer to form a via pattern (26) and patterning a second resist layer (28) to form a line pattern (38) in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern. The first resist layer, the second resist layer and the dielectric layer are etched such that the dielectric layer has a via (40) formed therein which gets deeper during the etching process. The dielectric layer has a trench (42) formed therein in communication with the via which gets deeper after the exposed portions of the first resist layer are consumed by the etching process.

Description

ONE-STEP ETCH PROCESSES FOR DUAL DAMASCENE METALLIZATION

BACKGROUND

1. Technical Field

This disclosure relates to semiconductor fabrication, and more particularly, to a method for forming dual damascene structures for semiconductor chip metallization processes.

2. Description of the Related Art

Metallization processes for semiconductor fabrication

include forming trenches and/or contact vias in a dielectric layer and then filling the trench or contact hole with metal. These processes are commonly referred to as damascene or dual damascene processes . Dual Damascene (DD) processes are extensively used for back end of the line (BEOL)

metallizations. Dual damascene processes typically include forming contacts and metal lines (line spaces) in a single filling process. Current dual damascene processes typically involve first patterning contact holes, and then etching vias in a dielectric layer. Then, metal line trenches are patterned, and etched to form trenches in communication with the vias. Metal is then deposited in the trenches and vias simultaneously. A chemical-mechanical polishing (CMP) step typically follows to remove any metal from a top surface of the device being fabricated.

One of the drawbacks associated with the conventional approach includes fence generation. Since two or more etching steps are employed, masking materials may not be completely removed forming "fences", which degrade performance. Another drawback of the conventional approach includes non-self alignment of vias and line trenches. This often occurs as a result of two or more patterning steps being employed.

Therefore, a need exists for a dual damascene process which reduces fence formation, provides via/trench self- alignment and reduces the number of etching steps needed to form the structure .

SUMMARY OF THE INVENTION

A method for forming a dual damascene structure, employs the steps of forming a dielectric layer, patterning a first resist layer on the dielectric layer to form a via pattern and patterning a second resist layer to form a line pattern in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern. The first resist layer, the second resist layer and the dielectric layer are etched such that the dielectric layer has a via formed therein which gets deeper during the etching process . The dielectric layer has a trench formed therein in communication with the via which gets deeper after the exposed portions of the first resist layer are consumed by ^"the etching process.

Another method for forming a dual damascene structure, in accordance with the present invention, includes the steps of forming a dielectric layer on a target layer, forming a first resist layer having a first thickness on the dielectric layer, patterning the first resist layer on the dielectric layer to form a via pattern, forming a second resist layer having a second thickness on the first resist layer, patterning the second resist layer to form a line pattern in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern and etching the first resist layer, the second resist layer and the dielectric layer such that the dielectric layer has a via formed therein which gets deeper during the etching process and the dielectric layer has a trench formed therein in communication with the via which gets deeper after the first thickness of the first resist layer is consumed in the exposed portions by the etching process.

Another method for forming a dual damascene structure, includes the steps of forming a dielectric layer on a target layer, forming a negative-tone resist layer having a first thickness on the dielectric layer, the negative tone resist including a cross-linking chemistry, patterning the negative- tone resist layer on the dielectric layer to form a via pattern, the cross-linking chemistry for preventing intermixing with a positive-tone resist, forming the positive- tone resist layer having a second thickness on the negative- tone resist layer, patterning the positive-tone resist layer to form a line pattern in communication with the via pattern formed on the negative-tone resist layer wherein the negative- tone resist layer includes exposed portions adjacent to the via pattern and etching the negative-tone resist layer, the positive-tone resist layer and the dielectric layer such that the dielectric layer has a via formed therein which gets deeper during the etching process and the dielectric layer has a trench formed therein in communication with the via which gets deeper after the first thickness of the negative-tone resist layer is consumed in the exposed portions by the , etching process.

In alternate methods, the first resist layer may include a cross-linking chemistry to prevent a mixing reaction with the second resist layer. The step of patterning the first resist layer may include the step of patterning a negative- tone resist. The step of patterning the second resist layer may include the step of patterning a positive-tone resist. The step of patterning the second resist layer may include the step of patterning a negative-tone resist. The step of etching preferably includes etching the trench and the via in a single etch step. The step of patterning the first resist layer may includes forming the first resist layer having a first thickness, and the step of patterning the second resist layer may include the step of forming the second resist layer having a second thickness greater than the first thickness. The step of exposing a portion of the target layer through the via may be included, and the method may include the step of filling the via and the trench with a conductive material to make an electrical connection to the target layer. These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings .

BRIEF DESCRIPTION OF DRAWINGS

This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a semiconductor device having a dielectric layer formed on a target layer and a first resist layer formed on the dielectric layer in accordance with the present invention;

FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 showing the exposure of the first resist layer in accordance with the present invention;

FIG. 3 is a cross- sectional view of the semiconductor device of FIG. 2 showing the development of the first resist layer in accordance with the present invention;

FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3 showing a second resist layer formed in accordance with the present invention;

FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4 showing the exposure of the second resist layer in accordance with the present invention; FIG. 6 is a cross-sectional view of the semiconductor device of FIG. 5 showing the development of the second resist layer in accordance with the present invention;

FIG. 7 is a cross-sectional view of the semiconductor device of FIG'. 6 showing an etching step which forms a via in the dielectric layer in accordance with the present invention;

FIG. 8 is a cross- sectional view of the semiconductor device of FIG. 7, later in the same etching process, showing the progression of the etching which consumes a portion of the first resist layer and forms a trench thereafter in the dielectric layer in accordance with the present invention;

FIG. 9 is a cross-sectional view of the semiconductor device of FIG. 8 showing a completed dual damascene structure formed in the dielectric layer in accordance with the present invention; and

FIG. 10 is a cross-sectional view of the semiconductor device of FIG. 9 showing the dual damascene structure filled with a conductive material and polished to planarize the top surface in accordance with the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention includes methods for forming dual damascene structures for semiconductor devices. The present invention employs positive and negative resist layers to create a structure which is etched to simultaneously form via and lines in a single etching step. The present invention is described in terms of a dual damascene structure; however the present invention is broader and may be extended to other structures to reduce the. number of etching steps, reduce fence formation and provide self-alignment between etched features. The present invention may be employed in semiconductor memory devices, such as dynamic -random access memories (DRAM) , processors, application specific integrated circuits (ASICs) or any other integrated circuit device.

Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, and initially to FIG. 1, a partial cross-sectional view of a semiconductor device 10 is shown. Device 10 includes a target layer 12. Target layer 12 may include a conductive line, a contact, a semiconductor substrate or any other conductive or semiconductive structure 13 to which electrical contact is to be made. In one embodiment, target layer 12 includes a metal line (13), which may include, for example, polysilicon, copper, tungsten, aluminum or any other suitable conductive material. In other embodiments, target layer 12 may include a doped diffusion region (13) of a semiconductor substrate or gate electrode (13) of a transistor.

A dielectric layer 14 is deposited over target layer 12 by known methods . Dielectric layer 14 preferably includes an oxide, such as silicon dioxide, although other dielectric materials may also be employed. An optional anti-reflection coating (ARC) 15 may be formed on dielectric layer 14 to improve imaging resolution during exposure steps of resist layers, described below. ARC layer 15 may include SiN, SiON,

or any other suitable material .

A first resist layer 16 is then formed over dielectric layer 14 or ARC layer 15. Resist layer 16 may include a photoresist material and may be spun onto dielectric layer 16 by known processes to coat the surface of dielectric layer. Resist layer 16 may include a negative-tone resist or a positive-tone resist. However, for simplicity, the present invention will be illustratively described with resist layer 16 as a negative-tone resist. In preferred embodiments, resist layer 16 includes crosslinking chemistry. By employing cross-linking chemistry resists, such as, for example, UVN30 available from Shipley, Inc., or CGR available from IBM, Inc., there will be no intermixing concerns when coating these resists with other photoresist layers. After coating resist layer 16, a post application bake process (PAB) may be performed.

Referring to FIG. 2, resist layer 16 is patterned to form a contact hole mask or a trench mask. Patterning of resist layer 16 includes exposing portions 20 of resist layer 16 with

light 24 and blocking other portions 22 of resist layer 16 from light by employing a photomask 18. Light 24 may include

ultraviolet (UV) light, such as for example, deep ultraviolet (DUV) or middle ultra violet light (MUV) when UV resists are employed for resist layer 16. It is to be understood that if a positive-tone resist is employed for resist layer 16, photomask 18 would block the light in portions 20 and permit light to expose portion 22.

Referring to FIG. 3, resist layer 16 is developed to open

up a contact hole/line spacing pattern 26. Pattern 26 may include a hole, such as a via or contact hole or extend into

and/or out of the plane of the page to form a line or trench. Development of resist layer 16 exposes a portion of dielectric layer 14.

Referring to FIG. 4, a second resist layer 28 is coated

onto resist layer 16 and the exposed portion of dielectric layer 14. If resist layer 16 includes a negative-tone resist then resist layer 28 preferably includes a positive-tone resist. If resist layer 16 includes a positive-tone resist, the resist layer 28 preferably includes a negative-tone resist. However, if resist layer 16 is substantially non- reactant with resist layer 28 (for example, layer 16 is significantly cross-linked) then the same tone resist may be employed for both resist layers 16 and 28. An optional ARC layer (not shown) may be deposited prior to the coating of resist layer 28. This resist layer may be employed to provide a barrier to prevent cross-linking between resist layer 16 and

resist layer 28. This ARC layer may include SiN, SiON, or any other suitable material . In a preferred embodiment ARC layer

15 is employed for resist layer 28 exposure as well (e.g., both resist layer 16 and 28 employ ARC 15) . Resist layer 28 may also include cross- linking chemistry to prevent

interaction with resist layer 16, as described above. Resist layer 28 is then post application baked (PAB) , by a known

baking process .

Referring to FIG. 5, resist layer 28 is exposed to light 24 in portion 30, and light 24 is blocked by a photomask 32 in

portions 34. Resist layer 28 may include a positive-tone resist (or a negative-tone resist) . In this example, resist layer 28 is a positive-tone resist. Portion 30 is exposed to light to render resist of layer 28 removable in a development process, as shown in FIG. 6. Advantageously, resist layer 28 is exposed in hole 26 as well in portion 30 directly over hole 26. In this way, self-alignment between hole 26 and a line pattern 38 (FIG. 6) is automatically achieved in accordance with the present invention. Resist layer 28 is then post exposure baked (PEB) , by a known baking process.

Referring to FIG. 6, resist layer 28 is developed to open up line spacing pattern 38. Pattern 38 may include a hole or

via, but preferably includes a trench extending into and/or out of the plane of the page to form a line. Development of resist layer 28 exposes the same portion of dielectric layer 14 as exposed earlier by the resist layer 16 development

process .

Referring to FIG. 7, an etching process is performed on the structure of FIG. 6. The etching process preferably includes an anisotropic etch, such as for example, a reactive ion etch (RIE) or a plasma etch. Etchants 39 begin to etch a

contact hole or trench 40 into dielectric layer 14. During

the etching of hole 40, unprotected portions of resist layer 16 are consumed exposing a larger portion of dielectric layer 14 in accordance with the pattern of resist layer 28. FIG. 7 shows resist layer 16 consumed in accordance with the pattern of resist layer 28. Etching is continued to form trench 42 in dielectric layer 14 as shown in FIG. 8. Advantageously, only a single etch process is employed to form both hole 40 and trench 42 in a dual damascene structure 44 or similar structure .

During the etching process, resist layers 16 and 28 are consumed. Thicknesses of resist layer 16 and resist layer 28 should be chosen such that sufficient thicknesses are available to form dual damascene structure 44 in a single etch process. Thicknesses of resist layers 16 and 28 may be chosen in accordance with different criteria. For example, etch

selectivity, depth of hole 40, depth of line 42, dielectric layer material and thickness are all considerations for

determining resist layer thicknesses. In one preferred embodiment, the thickness of layer 28 is greater than the thickness of layer 28.

In one illustrative embodiment, resist layer 16 includes UVN30 material available commercially from Shipley, Inc. and is formed with a thickness of between about 100 nm and about

1000 nm. In this example, resist layer 28 includes DUV resist

M20G material available commercially from JSR and is formed

with a thickness of between about 100 nm and about 1000 nm. The thickness of dielectric layer 14 may be between about 50 nm and 3000 nm. A selectivity of 1:1 between the resist material of resist layers 16 and 28 and dielectric layer 14 is achieved by an oxygen ion reactive ion etch. The selectivity

may be adjusted along with the resist layer thickness depending on the application and the specific results desired. It is to be understood that other selectivities, materials and thickness other than those described may be employed in accordance with the present invention. The above parameters may be employed in the illustrative embodiment to achieve the structure of FIG. 8 where, hole 40 reaches target layer 12 below dielectric layer 14.

Referring to FIG. 9, remaining portions of resist layer 16 and resist layer 28 are stripped from dielectric layer 14. This may be performed by a CMP step or by wet process. A cleaning process may be employed for example a water rinse, to clean surfaces of dielectric layer 14 and surface in hole 40 and trench 42.

Referring to FIG. 10, conductor deposition is formed to fill trench 42 and hole or via 40. A conductive material 46

may include doped polysilicon, copper, tungsten, aluminum or any other suitable conductive material. A diffusion barrier

layer (not shown) may be deposited before the deposition of

conductive material 46 to line hole 40 and trench 42. The

diffusion barrier may include, for example, Ta, TaN or other

suitable materials. A CMP process is then employed to remove access material 46 from a top surface of device 10. Electrical contact is preferably made between region 13 and material 46. Processing then continues as is known in the art.

The present invention may also employ a process where the trenches are formed after contact hole or vias. Other variations include but are not limited to more complex patterns etched into a conductive or dielectric layer using multiple resist layers.

Having described preferred embodiments for one-step etch processes for dual damascene metallization (which are intended to be illustrative and not limiting) , it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope and spirit of the invention as outlined by the appended claims. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims

WHAT IS CLAIMED IS;

1. A method for forming a dual damascene structure, comprising the steps of: forming a dielectric layer; patterning a first resist layer on the dielectric layer to form a via pattern; patterning a second resist layer to form a line pattern in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern; and etching the first resist layer, the second resist layer and the dielectric layer such that the dielectric layer has a via formed therein which gets deeper during the etching process and the dielectric layer has a trench formed therein in communication with the via which gets deeper after the exposed portions of the first resist layer are consumed by the etching process.

2. The method as recited in claim 1, wherein the first resist layer includes a cross-linking chemistry to prevent a mixing reaction with the second resist layer.

3. The method as recited in claim 1, wherein the step of patterning the first resist layer includes the step of patterning a negative-tone resist.

4. The method as recited in claim 3, wherein the step of patterning the second resist layer includes the step of patterning a positive-tone resist.

5. The method as recited in claim 3, wherein the step of patterning the second resist layer includes the step of patterning a negative-tone resist.

6. The method as recited in claim 1, wherein the ' step of etching includes etching the trench and the via in a single etch step.

7. The method as recited in claim 1, wherein the step of patterning the first resist layer includes forming the first resist layer having a first thickness and the step of patterning the second resist layer includes the step of forming the second resist layer having a second thickness greater than the first thickness.

8. A method for forming a dual damascene structure, comprising the steps of: forming a dielectric layer on a target layer; forming a first resist layer having a first thickness on the dielectric layer; patterning the first resist layer on the dielectric layer to form a via pattern; forming a second resist layer having a second thickness on the first resist layer; patterning the second resist layer to form a line pattern in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern; and etching the first resist layer, the second resist layer and the dielectric layer such that the dielectric layer has a via formed therein which gets deeper during the etching process and the dielectric layer has a trench formed therein in communication with the via which gets deeper after the first thickness of the first resist layer is consumed in the exposed portions by the etching process.

9. The method as recited in claim 8, wherein the first resist layer includes a cross-linking chemistry to prevent a mixing reaction with the second resist layer.

10. The method as recited in claim 8, wherein the step of patterning the first resist layer includes the step of patterning a negative-tone resist.

11. The method as recited in claim 10, wherein the step of patterning the second resist layer includes the step of patterning a positive-tone resist.

12. The method as recited in claim 10, wherein the step of patterning the second resist layer includes the step of patterning a negative-tone resist.

13. The method as recited in claim 8, wherein the step of etching includes etching the trench and the via in a single etch step.

14. The method as recited in claim 8, further comprising the step of exposing a portion of the target layer through the via.

15. The method as recited in claim 8, further comprising the step of filling the via and the trench with a conductive material to make an electrical connection to the target layer.

16. A method for forming a dual damascene structure, comprising the steps of: forming a dielectric layer on a target layer; forming a negative-tone resist layer having a first thickness on the dielectric layer, the negative tone resist including a cross-linking chemistry; patterning the negative-tone resist layer on the dielectric layer to form a via pattern, the cross-linking chemistry for preventing intermixing with a positive-tone resist; forming the positive-tone resist layer having a second thickness on the negative-tone resist layer; patterning the. positive-tone resist layer to form a line pattern in communication with the via pattern formed on the negative-tone resist layer wherein the negative-tone resist layer includes exposed portions adjacent to the via pattern; and etching the negative-tone resist layer, the positive-tone resist layer and the dielectric layer such that the dielectric layer has a via formed therein which gets deeper during the etching process and the dielectric layer has a trench formed therein in communication with the via which gets deeper after the first thickness of the negative-tone resist layer is consumed in the exposed portions by the etching process .

17. The method as recited in claim 16, wherein the step of etching includes etching the trench and the via in a single etch step.

18. The method as recited in claim 16, further comprising the step of exposing a portion of the target layer through the via.

19. The method as recited in claim 16, further comprising the step of filling the via and the trench with a conductive material to make an electrical connection to the target layer.