WO2002009186A3 - Field effect transistor - Google Patents

Field effect transistor Download PDF

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Publication number
WO2002009186A3
WO2002009186A3 PCT/US2001/022677 US0122677W WO0209186A3 WO 2002009186 A3 WO2002009186 A3 WO 2002009186A3 US 0122677 W US0122677 W US 0122677W WO 0209186 A3 WO0209186 A3 WO 0209186A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
accommodating buffer
buffer layer
silicon
amorphous interface
Prior art date
Application number
PCT/US2001/022677
Other languages
French (fr)
Other versions
WO2002009186A2 (en
Inventor
Kurt Eisenbeiser
James E Prendergast
Jamal Ramdani
William Jay Ms
Ravindranath Droopad
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2001275983A priority Critical patent/AU2001275983A1/en
Publication of WO2002009186A2 publication Critical patent/WO2002009186A2/en
Publication of WO2002009186A3 publication Critical patent/WO2002009186A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material

Abstract

High quality epitaxial layers of compound semiconductor materials (26) can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (24) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
PCT/US2001/022677 2000-07-24 2001-07-19 Field effect transistor WO2002009186A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001275983A AU2001275983A1 (en) 2000-07-24 2001-07-19 Field effect transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62510000A 2000-07-24 2000-07-24
US09/625,100 2000-07-24

Publications (2)

Publication Number Publication Date
WO2002009186A2 WO2002009186A2 (en) 2002-01-31
WO2002009186A3 true WO2002009186A3 (en) 2002-05-02

Family

ID=24504585

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/022677 WO2002009186A2 (en) 2000-07-24 2001-07-19 Field effect transistor

Country Status (2)

Country Link
TW (1) TW513810B (en)
WO (1) WO2002009186A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100701555B1 (en) * 2002-05-22 2007-03-30 마사시 카와사키 Semiconductor device and display comprising same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225031A (en) * 1991-04-10 1993-07-06 Martin Marietta Energy Systems, Inc. Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process
US5479033A (en) * 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
US5482003A (en) * 1991-04-10 1996-01-09 Martin Marietta Energy Systems, Inc. Process for depositing epitaxial alkaline earth oxide onto a substrate and structures prepared with the process
US5937274A (en) * 1995-01-31 1999-08-10 Hitachi, Ltd. Fabrication method for AlGaIn NPAsSb based devices
EP1109212A2 (en) * 1999-12-17 2001-06-20 Motorola, Inc. Semiconductor structure having a crystalline alkaline earth metal silicon nitride/oxide interface with silicon

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225031A (en) * 1991-04-10 1993-07-06 Martin Marietta Energy Systems, Inc. Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process
US5482003A (en) * 1991-04-10 1996-01-09 Martin Marietta Energy Systems, Inc. Process for depositing epitaxial alkaline earth oxide onto a substrate and structures prepared with the process
US5479033A (en) * 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
US5937274A (en) * 1995-01-31 1999-08-10 Hitachi, Ltd. Fabrication method for AlGaIn NPAsSb based devices
EP1109212A2 (en) * 1999-12-17 2001-06-20 Motorola, Inc. Semiconductor structure having a crystalline alkaline earth metal silicon nitride/oxide interface with silicon

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CHEN K J ET AL: "A novel ultrafast functional device: resonant tunneling high electron mobility transistor", ELECTRON DEVICES MEETING, 1996., IEEE HONG KONG HONG KONG 29 JUNE 1996, NEW YORK, NY, USA,IEEE, US, 1996, pages 60 - 63, XP010210167, ISBN: 0-7803-3091-9 *

Also Published As

Publication number Publication date
TW513810B (en) 2002-12-11
WO2002009186A2 (en) 2002-01-31

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