WO2001066832A3 - Graded thin films - Google Patents

Graded thin films Download PDF

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Publication number
WO2001066832A3
WO2001066832A3 PCT/US2001/006746 US0106746W WO0166832A3 WO 2001066832 A3 WO2001066832 A3 WO 2001066832A3 US 0106746 W US0106746 W US 0106746W WO 0166832 A3 WO0166832 A3 WO 0166832A3
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WO
WIPO (PCT)
Prior art keywords
varied
graded
aluminum oxide
gate dielectric
copper
Prior art date
Application number
PCT/US2001/006746
Other languages
French (fr)
Other versions
WO2001066832A2 (en
Inventor
Christiaan J Werkhoven
Ivo Raaijmakers
Suvi P Haukka
Original Assignee
Asm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asm Inc filed Critical Asm Inc
Priority to JP2001565432A priority Critical patent/JP5016767B2/en
Priority to AU2001245388A priority patent/AU2001245388A1/en
Priority to DE60125338T priority patent/DE60125338T2/en
Priority to EP01918295A priority patent/EP1266054B1/en
Publication of WO2001066832A2 publication Critical patent/WO2001066832A2/en
Publication of WO2001066832A3 publication Critical patent/WO2001066832A3/en

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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • C23C16/45529Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making a layer stack of alternating different compositions or gradient compositions
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Abstract

Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.
PCT/US2001/006746 2000-03-07 2001-03-02 Graded thin films WO2001066832A2 (en)

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JP2001565432A JP5016767B2 (en) 2000-03-07 2001-03-02 Method for forming gradient thin film
AU2001245388A AU2001245388A1 (en) 2000-03-07 2001-03-02 Graded thin films
DE60125338T DE60125338T2 (en) 2000-03-07 2001-03-02 GRADED THIN LAYERS
EP01918295A EP1266054B1 (en) 2000-03-07 2001-03-02 Graded thin films

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US60/187,423 2000-03-07

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WO2001066832A3 true WO2001066832A3 (en) 2002-02-14

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Cited By (14)

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US7687383B2 (en) 2005-02-04 2010-03-30 Asm America, Inc. Methods of depositing electrically active doped crystalline Si-containing films
US7759199B2 (en) 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
US7863163B2 (en) 2005-12-22 2011-01-04 Asm America, Inc. Epitaxial deposition of doped semiconductor materials
US8278176B2 (en) 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
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US6933225B2 (en) 2005-08-23
US20030129826A1 (en) 2003-07-10
WO2001066832A2 (en) 2001-09-13
AU2001245388A1 (en) 2001-09-17
US20010041250A1 (en) 2001-11-15
KR100803770B1 (en) 2008-02-15
EP1266054A2 (en) 2002-12-18
US6534395B2 (en) 2003-03-18
TW490739B (en) 2002-06-11
JP2003526218A (en) 2003-09-02
US20030032281A1 (en) 2003-02-13
DE60125338T2 (en) 2007-07-05
EP1266054B1 (en) 2006-12-20
JP5016767B2 (en) 2012-09-05
US6703708B2 (en) 2004-03-09
DE60125338D1 (en) 2007-02-01

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