WO2000038237A1 - A method of manufacturing a semiconductor device - Google Patents
A method of manufacturing a semiconductor device Download PDFInfo
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- WO2000038237A1 WO2000038237A1 PCT/EP1999/009356 EP9909356W WO0038237A1 WO 2000038237 A1 WO2000038237 A1 WO 2000038237A1 EP 9909356 W EP9909356 W EP 9909356W WO 0038237 A1 WO0038237 A1 WO 0038237A1
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- WIPO (PCT)
- Prior art keywords
- layer
- gate
- memory element
- active region
- dielectric
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000007667 floating Methods 0.000 claims abstract description 51
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 230000005669 field effect Effects 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 47
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 5
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 5
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 129
- 230000008569 process Effects 0.000 description 16
- 238000002513 implantation Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 239000000203 mixture Substances 0.000 description 6
- 238000005457 optimization Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000001627 detrimental effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000001117 sulphuric acid Substances 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device.
- the invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a field-effect transistor having a gate insulated from the semiconductor body by a gate dielectric, and with a nonvolatile memory element having a floating gate and a control gate, the floating gate being insulated from the semiconductor body by a floating gate dielectric and from the control gate by an inter-gate dielectric, by which method a first and a second active region of a first conductivity type adjoining the surface are defined in the semiconductor body for the transistor and the memory element, respectively, and the surface is coated with a first insulating layer providing the floating gate dielectric of the memory element, on which first insulating layer a silicon-containing layer is applied providing the floating gate of the memory element, after which source and drain zones of a second conductivity type of the memory element are provided in the semiconductor body and a second insulating layer is applied at the second active region so as to provide the inter-gate dielectric of the memory element, on which second insulating layer a conductive layer
- a method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph is known from US-A-5, 340,764.
- a first series of steps is performed to manufacture the non-volatile memory element consisting of two stacked layers of polycrystalline silicon (called poly hereinafter for short), which are mutually separated by an inter-gate dielectric and insulated from the semiconductor body by a floating gate oxide.
- a second series of steps is performed to manufacture the field-effect transistor.
- a relatively thin gate oxide layer is applied, which is covered by a further poly layer providing the gate of the field- effect transistor.
- the field-effect transistor is provided with a source and a drain zone by means of a self-aligned implantation using the gate together with adjacent oxide field insulating regions as a mask.
- a self-aligned implantation consists of an actual implantation of atoms into the semiconductor body followed by an anneal or so-called d ⁇ ve-in step, which is often carried out at a temperature as high as 1000 °C in order to activate the as-implanted atoms and to repair implantation damage caused to the lattice of the semiconductor body.
- a disadvantage of the known method is that the control gate and the inter-gate dielect ⁇ c of the memory element as well as the gate and the gate dielect ⁇ c of the transistor are applied p ⁇ or to the self-aligned implantation of the source and the dram zone of the transistor, and, hence, are subjected to the high-temperature anneal following the actual implantation. Consequently, se ⁇ ous constraints are imposed on the choice of process compatible mate ⁇ als for the gate and the control gate as well as for the gate dielect ⁇ c and the inter-gate dielect ⁇ c.
- a further disadvantage of the known method is that it possesses a rather complex sequential character so as to achieve a separate device optimization for the non-volatile memory element and the field-effect transistor.
- this object is achieved in that, together with the formation of the floating gate and the floating gate dielect ⁇ c of the memory element, the first active region is provided with a sac ⁇ ficial gate and a sac ⁇ ficial gate dielect ⁇ c of the transistor, respectively, after which source and drain zones of the second conductivity type of the transistor are provided together with the source and drain zones of the memory element and a dielect ⁇ c layer is applied which is removed over at least part of its thickness by means of a matenal removing treatment until the silicon-containing layer at the first and the second active region is exposed, after which the silicon-containing layer and the first insulating layer at the first active region are removed, thereby forming a recess in the dielect ⁇ c layer, in which recess a third insulating layer is applied providing the gate dielect ⁇ c of the transistor at the first active region, after which the conductive layer is applied, thereby filling the recess at the first active region, which conductive layer is shaped into the gate of the transistor at the first active region and into the control gate of
- the above measures in accordance with the invention prevent the gate and the gate dielectric of the transistor as well as the control gate and the inter-gate dielectric of the memory element, once formed, from being exposed to the high temperatures, often as high as 1000 °C, of the drive-in step carried out after the actual source/drain implantation.
- This substantially increases the flexibility in the use of process compatible materials for the gate and control gate and for the gate dielectric and inter-gate dielectric into conventional CMOS technology.
- the method in accordance with the invention allows a separate optimization of logic device characteristics and non-volatile device characteristics in conventional CMOS technology while using as many common process steps as possible, thereby reducing the complexity of the process.
- the above advantages are achieved by initially providing the field-effect transistor with a sacrificial gate and a sacrificial gate dielectric while at the same time providing the memory element with a floating gate and a floating gate dielectric, and by replacing in a later stage of the process, with the high-temperature anneal associated with the self-aligned implantation of the source and drain zones having been being carried out already, the sacrificial gate and the sacrificial gate dielectric with an actual gate and an actual gate dielectric while at the same time providing the memory element with a control gate and an inter gate dielectric.
- the replacement of the sacrificial gate by the actual gate shows a similarity to the replacement gate process described in an article entitled "Sub-lOOnm gate length metal gate NMOS transistors fabricated by a replacement gate process", written by Chatterjee et al. and published in LEDM 97 (1997), pp. 821-824.
- a typical characteristic of the replacement gate technology is that the actual gate is built self-aligned to the source/drain zones with all high temperature anneals performed before the formation of the actual gate.
- the sacrificial gate of the transistor and the floating gate of the memory element are formed from a silicon-containing layer comprising polycrystalline silicon, or possibly amorphous silicon or Ge x Si(i_ x) with x the fraction of germanium lying in a range between 0 and 1.
- a relatively thick dielectric layer is applied covering the sacrificial gate of the transistor and the floating gate of the memory element.
- the dielectric layer is then removed by means of, for example, chemical- mechanical polishing over at least part of its thickness until the sacrificial gate and the floating gate are exposed. Subsequently, the sacrificial gate of the transistor is removed by means of selective etching.
- a dip-etch is carried out in order to remove the subjacent sacrificial gate dielectric of the transistor.
- the floating gate and the floating gate dielectric of the memory element are prevented from being exposed to the etch mixtures through the use of a non-critical mask. In this way a recess is formed in the dielectric layer at the positions of the former sacrificial gate and the former sacrificial gate dielectric of the transistor.
- a third insulating layer is applied in the recess which provides the actual gate dielectric of the transistor.
- the surface is subsequently coated with a conductive layer which fills the recess and is shaped into the actual gate of the transistor and the control gate of the memory element.
- CMP chemical- mechanical polishing
- the silicon-containing layer in order to improve the height definition of the process, it is preferred to apply the silicon-containing layer as a double layer consisting of a first sub-layer comprising the silicon with on top a second sub-layer composed of a material having a greater resistance to the material removing treatment than silicon and being selectively etchable with respect to the dielectric layer.
- the second sub-layer will act as etch stop layer during the removal of the dielectric layer.
- silicon nitride as the second sub-layer and silicon oxide as the dielectric layer.
- aluminum oxide may be used instead of silicon nitride and/or BPSG (borophosphosilicate glass) instead of silicon oxide.
- the second sub-layer is removed selectively from both the sacrificial gate of the transistor and the floating gate of the memory element prior to the removal of the sacrificial gate. Together with the recess of the transistor, a further recess is thus formed in the dielectric layer at the area of the memory element.
- the second insulating layer which provides the inter-gate dielectric of the memory element, is now applied inside the further recess.
- the conductive layer now fills both recesses.
- the conductive layer is preferably shaped into the gate and the control gate by maskless removal it until either the second or third insulating layer or the dielectric layer is exposed.
- the gate and the control gate are recessed in the dielectric layer.
- the above-mentioned maskless removal of the conductive layer is preferably accomplished by means of chemical-mechanical polishing (CMP).
- CMP chemical-mechanical polishing
- a subsequent maskless removal of the second or third insulating layer, if present, is not required, but can be beneficial if the second or third insulating layer compises a material with a high dielectric constant.
- the demands imposed on the gate dielectric as regards optimization of the logic device with gate lengths approaching one tenth of a micrometer are different from those imposed on the floating gate dielectric and inter-gate dielectric as regards optimization of the non-volatile device.
- a non-volatile memory element is formed by a transistor with a floating gate, whose threshold voltage is determined by the information written in the form of electric charge on the floating gate.
- the control gate on the one hand serves to detect what the threshold voltage and, thus, the written information is during reading and on the other hand serves to influence the potential of the floating gate during writing and/or erasing.
- the floating gate dielectric which insulates the floating gate from the channel of the memory element, should be thin enough to allow writing and/or erasing and should at the same time be thick enough to prevent leakage of charge from the floating gate once the threshold voltage of the transistor has been raised.
- Leakage of charge from the floating gate is detrimental to the retention time of the memory element, which obviously should be as long as possible.
- the floating gate dielectric of the memory element which is conventionally composed of silicon oxide, and, hence, the first insulating layer from which the floating gate dielectric is formed, is advantageously applied with a geometric thickness of about 6 to 10 nm.
- the inter-gate dielectric of the memory element which separates the control gate from the floating gate, should be thick enough to prevent charge leakage from the floating gate and should at the same time be thin enough to achieve a large capacitive coupling between the control gate and the floating gate.
- the capacitive coupling between the control gate and the floating gate may be not only improved through a decrease in the geometric thickness of the inter-gate dielectric, but also through an increase in the dielectric constant of the inter-gate dielectric at a given geometric thickness. It is therefore preferred to apply a dielectric material with a dielectric constant higher than that of silicon oxide ( ⁇ 4) as the inter-gate dielectric of the memory element and, hence, as the second insulating layer from which the inter-gate dielectric is formed. Furthermore, the gate dielectric of the field-effect transistor, which insulates the gate from the channel of the transistor, should be applied as thin as possible in order to achieve a capacitive coupling between the gate and the channel which is as high as possible.
- the gate dielectric of the transistor should be made sufficiently thick.
- a silicon oxide thickness of at least 1.5 nm is adopted in order to suppress leakage currents.
- the capacitive coupling between gate and channel can be improved by increasing the dielectric constant of the gate dielectric. It is therefore preferred to compose the gate dielectric of the transistor and, hence, the third insulating layer from which the gate dielectric is formed of a dielectric material having a dielectric constant higher than that of silicon oxide ( ⁇ 4).
- the gate dielectric of the transistor is advantageously applied in an equivalent oxide thickness, defined as d/ ⁇ r with d the geometric thickness of the layer and ⁇ r the dielectric constant of the layer relative to that of silicon oxide, of about 1.5 to 4 nm.
- the second insulating layer providing the inter-gate dielectric of the memory element as well as the third insulating layer providing the gate dielectric of the transistor is preferably composed of a dielectric material with a dielectric constant higher than that of silicon oxide ( ⁇ 4).
- tantalum oxide (Ta O 5 ; ⁇ 20- 25), aluminum oxide (Al O 3 ; ⁇ 10) or silicon nitride (Si 3 N 4 ; ⁇ 7) can be applied to advantage as these materials are deposited in a conformal and reproducible way by means of chemical vapor deposition (CVD).
- the application of a high dielectric constant gate dielectric/inter-gate dielectric in the prior art method may lead to a degradation of the corresponding dielectric properties upon exposure to the high temperatures of the anneal associated with the source/drain implantation of the transistor.
- the gate dielectric/inter-gate dielectric, once formed, is not exposed to high temperatures in subsequent process steps.
- the second insulating layer and the third insulating layer are part of one common layer which provides the inter-gate dielectric of the memory element as well as the gate dielectric of the transistor.
- the third insulating layer providing the gate dielectric of the transistor with an equivalent oxide thickness, defined as d/ ⁇ r with d the geometric thickness of the layer and ⁇ r the dielectric constant of the layer relative to that of silicon oxide, which is smaller than the equivalent oxide thickness of the first insulating layer providing the floating gate dielectric of the memory element.
- the third insulating layer is advantageously applied with an equivalent oxide thickness of about 1.5 to 4 nm while the first insulating layer is applied with an equivalent oxide thickness of about 6 to 10 nm.
- the gate as well as the control gate and, hence, the conductive layer from which both are formed, advantageously comprises a metal instead of conventional polycrystalline silicon.
- metals intrinsically have a relatively low resistance and do not suffer from detrimental depletion effects.
- a low-resistance metal such as aluminum, tungsten, copper or molybdenum can be advantageously applied.
- the conductive layer is preferably applied as a double layer consisting of a layer comprising the metal on top of a layer acting as an adhesion layer and/or barrier layer.
- titanium (Ti) may be applied as the adhesion layer and titanium nitride (TiN) or titanium tungsten (TiW) as the barrier layer.
- the application of a metal gate/control gate in the prior art method would lead to melting in the case of an aluminum gate/control gate or cause detrimental interaction between the metal gate/control gate and the gate dielectric/inter-gate dielectric upon exposure to the high temperatures of the anneal associated with the source/drain implantation of the transistor.
- the gate/control gate, once formed, is not exposed to high temperatures in subsequent process steps.
- Figs. 1 to 10 show in diagrammatic cross sectional view successive stages of a process for manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element by means of the method in accordance with the invention.
- the invention is illustrated below on the basis of a MOS transistor combined with a non-volatile memory element. It is to be noted that the invention may be advantageously used for any non-volatile memory element known per se, such as an EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory) or flash EEPROM.
- EPROM Erasable Programmable Read-Only Memory
- EEPROM Electrical Erasable Programmable Read-Only Memory
- flash EEPROM flash EEPROM
- the process starts (Fig. 1) with a semiconductor body 1 of a first conductivity type, in the present example a silicon body of, for instance, p-type conductivity, which is provided at a surface 2 with relatively thick oxide field insulating regions 3 which lie at least partly recessed in the semiconductor body 1 and which define a first active region 4 in which a field-effect transistor is to be manufactured and a second active region 5 in which a nonvolatile memory element is to be manufactured.
- the thick oxide insulating regions 3 are formed in a ⁇ sual way by means of LOCOS (LOCal Oxidation of Silicon) or STI (Shallow Trench Isolation).
- the surface 2 of the semiconductor body 1 is coated with a first insulating layer 6 composed of, for example, silicon oxide, which is covered by a silicon- containing layer 9.
- the first insulating layer 6 is preferably applied with a geometric thickness of about 6 to 10 nm.
- the silicon-containing layer 9 is a double layer consisting of a first sub-layer 7 of, for example, polycrystalline silicon which may be doped with a dopant such as phosphorus or possibly boron, with on top a second sub-layer 8 composed of, for example, silicon nitride. Any other suitable material such as, for example, aluminum oxide or a combination of materials may be used instead of silicon nitride.
- Amorphous silicon or Ge x Si ⁇ -x with x representing the fraction of germanium lying in the range between 0 and 1 may be used instead of polycrystalline silicon. It is to be noted that the silicon-containing layer may be a single layer as well, composed of polycrystalline silicon, amorphous silicon or Ge x Si ⁇ _ x .
- the silicon-containing layer 9 is patterned in a usual photolithographic way in order to provide a sacrificial gate 10 at the first active region 4 and a floating gate 11 at the second active region 5.
- the sacrificial gate 10 and the floating gate 11 are covered by the second sub-layer 8 and are insulated from the semiconductor body 1 by a sacrificial gate dielectric 12 and a floating gate dielectric 13, respectively, both provided by the first insulating layer 6.
- source/drain extensions 14 of a second, opposite conductivity type in the present example being n-type, are formed on mutually opposed sides of the sacrificial gate 10 at the first active region 4 and on mutually opposed sides of the floating gate 11 at the second active region 5 by means of a self- aligned implantation of a light dose of, for example, phosphorus or arsenic using the silicon- containing layer 9 together with the oxide field insulating regions 3 as a mask.
- the sacrificial gate 10 of the transistor and the floating gate 11 of the memory element, both covered by the second sub-layer 8, are provided with side wall spacers 15 in a known way, for example, by means of deposition and anisotropic etching-back of a silicon oxide layer (Fig. 3).
- highly-doped source zones 16 and drain zones 17 of the second conductivity type are formed on mutually opposed sides of the sidewall spacers 15 at both the first and the second active region 4 and 5 by means of a self-aligned implantation of a heavier dose of, for example, phosphorus or arsenic using the oxide field insulating regions 3 together with the silicon-containing layer 9 and the side wall spacers 15 as a mask.
- dielectric layer 18 in the present example composed of silicon oxide, is deposited.
- PSG phosphosilicate glass
- BPSG borophosphosilicate glass
- the dielectric layer 18 is removed over at least part of its thickness until the second sub-layer 8 at the first and the second active region 4 and 5 is exposed (Fig. 5). This can be accomplished, for example, by means of chemical-mechanical polishing (CMP) using a commercially available slurry.
- CMP chemical-mechanical polishing
- the second sub-layer 8 composed of silicon nitride in the present example, is removed selectively with respect to the dielectric layer 18 and the side wall spacers 15, both composed of silicon oxide in the present example, by means of, for example, wet etching using a mixture of hot phosphoric acid and sulphuric acid.
- the dielectric layer 18 is provided with a recess 19 at the first active region 4 and a further recess 20 at the second active region 5.
- a non-critical mask 21 of resist is applied at the second active region 5, after which the sacrificial gate 10 and the sacrificial gate dielectric 12 of the transistor at the first active region 4 are removed in two separate etch steps.
- the sacrificial gate in the present example composed of polycrystalline silicon, can be removed selectively by means of wet etching using a hot KOH solution or by means of plasma etching with, for example, a FfBr/Cli mixture.
- the sacrificial gate dielectric in the present example composed of silicon oxide, can be removed by means of wet etching using HF.
- the non-critical mask 21 prevents the floating gate 11 and the floating gate dielectric 13 of the memory element from being exposed to the above etchants.
- a second insulating layer 22 is deposited on all exposed surfaces, thereby providing an inter-gate dielectric 24 of the memory element at the second active region 5 together with an actual gate dielectric 23 of the transistor at the first active region 4.
- the second insulating layer 22 may be composed of silicon oxide, however, a dielectric material with a dielectric constant higher than that of silicon oxide, such as tantalum oxide, aluminum oxide or silicon nitride is more favorable.
- the gate dielectric 23 of the transistor is preferably applied with an equivalent oxide thickness, which is defined as d/ ⁇ r with d the geometric thickness of the layer and ⁇ r the dielectric constant of the layer relative to that of silicon oxide, of about 1.5 to 4 nm.
- the gate dielectric 23 of the transistor and the mter-gate dielect ⁇ c 24 of the memory element are formed as part of one common layer, i.e. the second insulating layer 22. It will be obvious that, besides a second insulating layer 22 providing, for example, the mter-gate dielect ⁇ c 24 of the memory element, a third insulating layer (not shown) may be applied providing the gate dielect ⁇ c 23 of the transistor. In this way the gate dielect ⁇ c 23 and the mter-gate dielect ⁇ c 24 are formed from separate insulating layers and, hence, the thickness/composition of the gate dielect ⁇ c 23 can be completely uncoupled from the thickness/composition of the inter-gate dielect ⁇ c 24.
- the third insulating layer will be composed of silicon oxide or preferably of a dielect ⁇ c mate ⁇ al with a dielect ⁇ c constant higher than that of silicon oxide, such as tantalum oxide, aluminum oxide or silicon mt ⁇ de. If silicon oxide is to be used for both the gate dielect ⁇ c 23 and the inter-gate dielect ⁇ c 24, it may be obtained by means of, for exanple, chemical vapor deposition or thermal oxidation of silicon, either in one step or in two separate steps, while one of the active regions is shielded with a mask.
- the thickness of the gate dielect ⁇ c 23 will be automatically smaller than that of the inter-gate dielect ⁇ c 24 owing to the higher oxidation rate of polycrystalline silicon compared with that of monocrystal ne silicon.
- the high dielect ⁇ c constant mate ⁇ als tantalum oxide, aluminum oxide and silicon nit ⁇ de can be applied, for example, by means of chemical vapor deposition (CVD), either in one step or in two separate steps, while one of the active regions is shielded with a mask.
- CVD chemical vapor deposition
- a conductive layer 25 is applied on the second insulating layer 22 in a usual way, thereby filling the recess 19 at the first active region 4 and the further recess 20 at the second active region 5.
- the conductive layer 25 now preferably comp ⁇ ses a metal such as aluminum, tungsten, copper or molybdenum, or a combination of metals. It is to be noted that the conductive layer 25 may also be applied as a double layer consisting of a layer comp ⁇ sing a metal oi combination of metals on top of a layer acting as an adhesion layer and/or bar ⁇ er layer. In this case Ti may be applied as the adhesion layer and TiN or TiW as the bar ⁇ er layer
- the conductive layer 25 is shaped into an actual gate 26 of the transistor at the first active region 4 and into a control gate 27 of the memory element at the second active region 5. This can be done, for example, by means of etching with an oversized mask at both the first and the second active region 4 and 5. In that case the conductive mate ⁇ al of the gate 26 and of the control gate 27 extends over the dielect ⁇ c layer 18, which is coated with the second insulating layer 22, to beyond the recess 19 and the further recess 20, respectively.
- the semiconductor device is completed by conventional CMOS process steps (not shown) for oxide deposition, contact definition and metallization with one or more metal layers.
- said gate and control gate may be formed from two separate conductive layers instead of one common conductive layer.
- the source and drain zones can optionally be implanted without drain extensions in order to obtain a sufficiently high electric field near the floating gate of the memory element for the program/erase procedure.
- the source and drain zones may be subjected to a saliciding process using Ti or Co, thereby forming self-aligned suicides of Ti (TiSi 2 ) or Co (CoSi 2 ), respectively, on the source and drain zones.
- the first and the second active regions are formed by surface regions of the original semiconductor body.
- the first and the second active region may represent conventional p and/or n wells, which are obtained by means of local doping of the original semiconductor body in regions adjoining its surface with doping concentrations suitable for providing an n-channel or p-channel field- effect transistor and non-volatile memory element.
Abstract
Description
Claims
Priority Applications (3)
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JP2000590216A JP2002533931A (en) | 1998-12-18 | 1999-12-01 | Method for manufacturing semiconductor device |
DE69939895T DE69939895D1 (en) | 1998-12-18 | 1999-12-01 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT |
EP99962194A EP1057218B1 (en) | 1998-12-18 | 1999-12-01 | A method of manufacturing a semiconductor device |
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EP98204342.4 | 1998-12-18 | ||
EP98204342 | 1998-12-18 |
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WO2000038237A1 true WO2000038237A1 (en) | 2000-06-29 |
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PCT/EP1999/009356 WO2000038237A1 (en) | 1998-12-18 | 1999-12-01 | A method of manufacturing a semiconductor device |
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US (1) | US6251729B1 (en) |
EP (1) | EP1057218B1 (en) |
JP (1) | JP2002533931A (en) |
KR (1) | KR100665416B1 (en) |
DE (1) | DE69939895D1 (en) |
TW (1) | TW449919B (en) |
WO (1) | WO2000038237A1 (en) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US7279735B1 (en) | 2004-05-05 | 2007-10-09 | Spansion Llc | Flash memory device |
US7579280B2 (en) | 2004-06-01 | 2009-08-25 | Intel Corporation | Method of patterning a film |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0305741A2 (en) * | 1987-07-31 | 1989-03-08 | Kabushiki Kaisha Toshiba | Semiconductor device with floating gate |
US4845046A (en) * | 1986-09-02 | 1989-07-04 | Seiko Instruments Inc. | Process for producing semiconductor devices by self-alignment technology |
EP0811983A1 (en) * | 1996-06-06 | 1997-12-10 | STMicroelectronics S.r.l. | Flash memory cell, electronic device comprising such a cell, and relative fabrication method |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5512505A (en) * | 1990-12-18 | 1996-04-30 | Sandisk Corporation | Method of making dense vertical programmable read only memory cell structure |
US5340764A (en) | 1993-02-19 | 1994-08-23 | Atmel Corporation | Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer |
US5474947A (en) * | 1993-12-27 | 1995-12-12 | Motorola Inc. | Nonvolatile memory process |
KR0136995B1 (en) * | 1994-09-08 | 1998-04-24 | 김주용 | Method of non-volatile memory cell |
JPH09205154A (en) * | 1996-01-25 | 1997-08-05 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
US5756384A (en) * | 1997-05-20 | 1998-05-26 | Vanguard International Semiconductor Corporation | Method of fabricating an EPROM cell with a high coupling ratio |
US5972752A (en) * | 1997-12-29 | 1999-10-26 | United Semiconductor Corp. | Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile |
TW390028B (en) * | 1998-06-08 | 2000-05-11 | United Microelectronics Corp | A flash memory structure and its manufacturing |
US6093945A (en) * | 1998-07-09 | 2000-07-25 | Windbond Electronics Corp. | Split gate flash memory with minimum over-erase problem |
JP2000232173A (en) * | 1998-12-09 | 2000-08-22 | Matsushita Electronics Industry Corp | Semiconductor memory and its manufacture |
US6168995B1 (en) * | 1999-01-12 | 2001-01-02 | Lucent Technologies Inc. | Method of fabricating a split gate memory cell |
TW479364B (en) * | 1999-04-28 | 2002-03-11 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device comprising a field effect transistor |
-
1999
- 1999-06-21 TW TW088110316A patent/TW449919B/en not_active IP Right Cessation
- 1999-12-01 JP JP2000590216A patent/JP2002533931A/en not_active Withdrawn
- 1999-12-01 WO PCT/EP1999/009356 patent/WO2000038237A1/en active IP Right Grant
- 1999-12-01 DE DE69939895T patent/DE69939895D1/en not_active Expired - Lifetime
- 1999-12-01 KR KR1020007009057A patent/KR100665416B1/en not_active IP Right Cessation
- 1999-12-01 EP EP99962194A patent/EP1057218B1/en not_active Expired - Lifetime
- 1999-12-15 US US09/464,004 patent/US6251729B1/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4845046A (en) * | 1986-09-02 | 1989-07-04 | Seiko Instruments Inc. | Process for producing semiconductor devices by self-alignment technology |
EP0305741A2 (en) * | 1987-07-31 | 1989-03-08 | Kabushiki Kaisha Toshiba | Semiconductor device with floating gate |
EP0811983A1 (en) * | 1996-06-06 | 1997-12-10 | STMicroelectronics S.r.l. | Flash memory cell, electronic device comprising such a cell, and relative fabrication method |
Non-Patent Citations (1)
Title |
---|
CHATTERJEE A ET AL: "SUB-100NM GATE LENGTH METAL GATE NMOS TRANSISTORS FABRICATED BY A REPLACEMENT GATE PROCESS", INTERNATIONAL ELECTRON DEVICES MEETING,US,NEW YORK, NY: IEEE, 1997, pages 821 - 824, XP000855919, ISBN: 0-7803-4101-5 * |
Cited By (15)
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US7476582B2 (en) | 2000-09-29 | 2009-01-13 | Fujitsu Limited | Semiconductor device and its manufacturing method |
EP1193762A3 (en) * | 2000-09-29 | 2003-02-12 | Fujitsu Limited | Semiconductor device and its manufacturing method |
EP1193762A2 (en) * | 2000-09-29 | 2002-04-03 | Fujitsu Limited | Semiconductor device and its manufacturing method |
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US6583043B2 (en) | 2001-07-27 | 2003-06-24 | Motorola, Inc. | Dielectric between metal structures and method therefor |
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EP1363324A1 (en) * | 2002-05-16 | 2003-11-19 | STMicroelectronics S.r.l. | Method for manufacturing non-volatile memory device |
US6812098B2 (en) | 2002-05-16 | 2004-11-02 | Stmicroelectronics S.R.L. | Method for manufacturing non-volatile memory device |
WO2009016437A1 (en) * | 2007-08-01 | 2009-02-05 | Freescale Semiconductor, Inc. | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith |
US8043951B2 (en) | 2007-08-01 | 2011-10-25 | Freescale Semiconductor, Inc. | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith |
EP2382665A2 (en) * | 2008-12-31 | 2011-11-02 | Intel Corporation | Flash cell with integrated high-k dielectric and metal-based control gate |
EP2382665A4 (en) * | 2008-12-31 | 2014-12-31 | Intel Corp | Flash cell with integrated high-k dielectric and metal-based control gate |
Also Published As
Publication number | Publication date |
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KR100665416B1 (en) | 2007-01-04 |
EP1057218B1 (en) | 2008-11-12 |
US6251729B1 (en) | 2001-06-26 |
KR20010041025A (en) | 2001-05-15 |
JP2002533931A (en) | 2002-10-08 |
EP1057218A1 (en) | 2000-12-06 |
DE69939895D1 (en) | 2008-12-24 |
TW449919B (en) | 2001-08-11 |
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