WO1999007000A2 - Two bit eeprom using asymmetrical charge trapping - Google Patents
Two bit eeprom using asymmetrical charge trapping Download PDFInfo
- Publication number
- WO1999007000A2 WO1999007000A2 PCT/IL1998/000363 IL9800363W WO9907000A2 WO 1999007000 A2 WO1999007000 A2 WO 1999007000A2 IL 9800363 W IL9800363 W IL 9800363W WO 9907000 A2 WO9907000 A2 WO 9907000A2
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- region
- charge
- bit
- voltage
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- 230000015654 memory Effects 0.000 claims abstract description 250
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
Definitions
- the present invention relates generally to semiconductor memory devices and
- non-volatile semiconductor memory include read only memory (ROM), programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable read only memory (EEPROM), programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable
- PROM read only memory
- EPROM erasable programmable read only memory
- EEPROM electrically erasable programmable read only memory
- flash EEPROM flash EEPROM
- the die size is larger due to the addition of programming circuitry and there are more
- EPROMs are electrically programmed, but for erasing
- EPROMs require exposure to ultraviolet (UV) light. These devices are constructed with
- Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e.,
- flash EEPROM The disadvantage of flash EEPROM is that it is very
- MNOS metal-oxide-semiconductor
- a conductive gate electrode such as polycrystalline silicon or
- oxide-nitride structure as opposed to an oxide-nitride-oxide structure is that during
- top oxide layer lowers the ability to control where the charge is stored in the nitride layer.
- the nitride layer is typically 350
- nitride must be neutralized either by moving electrons out of the nitride or by transferring
- Hayes teaches an erase mode for his memory cell whereby the
- Avalanche breakdown involves hot
- the hot holes are generated and caused to surmount the hole potential barrier of
- Another well known technique of erasing is to inject holes from the gate into the
- the nitride layer provides the charge retention mechanism for programming the
- the Mitchell device is programmed and read in the forward direction. Since reading in the forward direction is less effective
- the charge trapping region must be wider by default in
- oxide-nitride-oxide (ONO) layer of the device This article teaches programming and
- Multi-bit transistors are known in the art. Most multi-bit transistors utilize
- multi-level thresholds to store more than one bit with each threshold level representing a
- a memory cell having four threshold levels can store two bits. This
- the threshold of each cell is increased until the desired threshold is
- word line or bit line to program other cells will not interfere with or disturb the data in cells
- the cell In order to construct a multi-bit ROM memory cell, the cell must have four
- the threshold voltage programmed into a cell for a '0' bit only has to be
- L eff is the effective channel length
- K is a constant
- V G is the gate voltage
- the gate voltage also affects the distribution of read currents. For the same set
- the two level i.e., single bit, cell.
- the memory cell can store three levels of data: no electrons on
- Each reference potential having a plurality of reference potential transmission lines.
- Each memory cell includes a
- the cell's memory window is widened to store more than two binary states.
- the cell basically:
- the data transistor comprises a data storage transistor coupled to a series pass transistor.
- the data transistor is
- Sensing circuitry distinguishes the
- the present invention discloses an apparatus for and method of programming
- the two bit flash EEPROM memory cell is constructed having a charge
- the nonconducting dielectric layer functions as an electrical charge trapping medium.
- charge trapping layer is sandwiched between two layers of silicon dioxide which act as
- a conducting gate layer is placed over the upper silicon dioxide layer.
- the two individual bits i.e., left and right bits, are stored in physically different areas of
- a novel aspect of the memory device is that while both bits are programmed in
- each bit is read in a direction
- the right bit is programmed conventionally by applying programming voltages to the gate
- Hot electrons are accelerated sufficiently to be
- Another major benefit is that the erase mechanism of the memory cell is greatly
- Both bits of the memory cell can be erased by applying suitable erase voltages
- Electrons move from the nitride through the bottom oxide layer to the drain or the source
- Another benefit includes reduced wearout from
- the erase mechanism is enhanced when the charge trapping region is made as
- bottom and top oxide thickness can be scaled due to the deep trapping levels that function
- the final threshold of the cell after erasing is self limited by the device
- the second transistor acting as a control
- the second is that programming the
- the margin is defined as the parameters that will program one of the bits without
- the memory device also exhibits little or no disturb during programming. This is
- present invention cannot store two bits utilizing programming in the forward direction and
- Fig. 1 illustrates a sectional view of a single bit flash EEPROM cell of the prior
- Oxide-Nitride-Oxide As the gate dielectric
- Fig. 2 illustrates a sectional view of a two bit flash EEPROM cell constructed in
- Fig. 3 illustrates a sectional view of a two bit flash EEPROM cell constructed in
- Fig. 4 is a graph illustrating the threshold voltage as a function of programming
- Fig. 5A illustrates a sectional view of a flash EEPROM cell of the prior art
- Fig. 5B illustrates a sectional view of a flash EEPROM cell constructed in
- Fig. 6 is a graph illustrating the difference in threshold voltage in the forward
- Fig. 7 is a graph illustrating the difference in drain current in the forward
- Fig. 8 is a graph illustrating the threshold voltage of a flash EEPROM cell of the
- present invention as a function of programming time for reading in the forward and reverse
- Fig. 9 is a graph illustrating the leakage current through the region of trapped
- Fig. 10 is a graph illustrating the gate voltage required to sustain a given voltage
- Fig. 11 is a graph illustrating the effect of the gate voltage applied during
- Fig. 12 is a graph illustrating the effect- of the gate voltage (as measured by
- threshold channel current I-n ⁇ on the difference in threshold voltage between the forward
- Fig. 13 is a graph illustrating the effect programming one of the bits has on the
- Fig. 14 is a graph illustrating the effect programming one of the bits has on the
- FIG. 15 is a sectional view of a two bit EEPROM cell constructed in accordance
- Fig. 16 is a graph illustrating the effect of a low drain voltage on the read
- Fig. 17 is a graph illustrating the effect of programming on erase for the forward
- Fig. 18 is a graph illustrating the separate bit erase capability of the two bit
- Fig. 19 is a graph illustrating the effect of cycling on the program and erase
- Fig. 20 is a graph illustrating the effect of over programming on the ability to
- Fig. 21 is a graph illustrating the programming and erasing curves for using
- Fig. 22 is. a graph illustrating the erase curves for two different values of drain
- Fig. 23 is a graph illustrating the erase curve for two different values of gate
- Fig. 24A illustrates a sectional view of a flash EEPROM cell of the prior art
- Fig. 24B illustrates a sectional view of a flash EEPROM cell constructed in
- the two bit flash EEPROM cell of the present invention can best be understood
- ONO EEPROM memory cells and the conventional method used to program, read and erase
- the memory cell generally referenced 41, comprises a P-type silicon substrate
- non conducting nitride layer 38 sandwiched between two oxide layers 36, 40 and a
- source 32 is grounded.
- 10V is applied to the gate and 9V is applied to the
- the probability of this occurring is a maximum in the region of the gate next to the drain 34 because it is near the drain that the electrons gain the most energy.
- the trapped charge remains in a localized trapping region in the nitride
- nitride layer in Hayes has no top oxide layer.
- a top oxide layer would serve as a low
- the nitride layer would be lost to holes entering from the overlying conductive gate.
- elevated temperatures typically in the range from about 150 degrees Centigrade to 250
- holes from the gate can enter the nitride and combine with the
- the relatively thick nitride layer such as disclosed by Hayes causes the electrons to move laterally in response to this lateral field and come to rest either in traps between the conduction and valence bands or in localized regions of
- the device cannot be erased at all because the charge trapping region was
- threshold voltage increases because the electrons that become stored in the gate screen the
- threshold voltage to increase only in the localized trapping region. This is in contrast to the
- threshold voltage of the entire channel rises as programming time increases.
- an increase in the gate threshold voltage causes the current flowing through the channel to decrease for a given
- the programming time is reduced less than with the conductive
- the threshold is therefore high for the entire channel and the process of reading
- the process of programming typically includes writing followed by reading.
- the gate threshold voltage is measured by
- the gate voltage that provides 1 p. A of channel current is termed the threshold
- programming pulses i.e., write pulses
- read cycles i.e., read cycles
- the threshold voltage has reached a certain predetermined point (i.e., the channel current is
- the flash EEPROM memory cell comprises a P-type
- substrate 12 having two buried PN junctions, one being between the source 14 and
- substrate 12 termed the left junction and the other being between the drain 16 and the
- layer 20 constructed preferably in the range of 20 to 100 Angstroms thick and preferably
- the charge trapping layer serves as the memory retention layer. Note that the programming, reading and erasing of the memory cell of the
- present invention is based on the movement of electrons as opposed to movement of holes.
- the charge trapping dielectric can be constructed using silicon nitride, silicon dioxide with
- the oxide can be implanted with arsenic, for example.
- the thickness of layer 18 is chosen
- cell 10 is capable of storing two bits of data, a right bit represented by the dashed circle 23
- the two bit memory cell of the present invention is a
- the right junction serves as the drain terminal for the right bit.
- the left bit the left bit
- junctions are utilized most of the time rather than source and drain.
- the second bit are reversed compared to the source and drain terminals for the first bit.
- Another layer of silicon dioxide 22 is formed over the charge trapping layer,
- silicon nitride layer (i.e., silicon nitride layer), and is preferably between approximately 60 to 100 Angstroms
- the silicon dioxide layer 22 functions to electrically isolate a conductive gate 24 formed over the silicon dioxide layer 22 from charge trapping layer 20.
- gate 24 is approximately 4,000 Angstroms. Gate 24 can be constructed from
- polycrystalline silicon commonly known as polysilicon.
- Charge trapping dielectric materials other than nitride may also be suitable for
- One such material is silicon dioxide with
- polysilicon islands 57 is sandwiched between two layers of silicon dioxide 52, 56.
- Covering oxide layer 52 is polysilicon gate 50.
- Gate 50 is typically heavily doped with an
- N-type impurity such as phosphorus in the 10 19 to 10 20 atom cc range. Similar to the two
- bit memory cell of igure 2 the memory cell of Figure 3 is capable of storing two data
- the charge trapping dielectric can be constructed by implanting an
- impurity such as arsenic
- a key aspect of the present invention lies in the manner in which the flash
- EEPROM memory cell 10 ( Figure 2) is programmed and read. Rather than performing
- bit i.e. the left bit and the right bit
- Figure 2 point in opposite directions to signify this
- the electron trapping occurs in a region near the
- the electrons have a maximum
- the width of the charge trapping region increases. If
- the trapped electrons are stored in a narrower region near the drain also
- programming means the device is programmed and read in the same forward direction. During reading, voltages having levels lower than the voltages applied during
- the channel current should be very low and if the
- the difference in the channel current between the '0' and T logic is generated.
- Illustrated in Figure 4 is a graph showing the rise in gate threshold voltage as a
- Figures 5 A and 5B illustrates a sectional view of a flash EEPROM cell of the
- FIG. 5B illustrates a
- logic '0' is programmed, there can be little or no channel current through the device when it
- the length of the trapping area If the memory cell is programmed for a sufficiently long period of time.
- the channel is in a conductive state
- the potential in the inversion layer is pinned to ground
- V DSAT the saturation voltage
- punch through occurs if the lateral electric field is strong enough to
- memory cells are read in the forward direction. As the memory device is programmed for
- Fig. 4 shows that at programming time of approximately 3 milliseconds
- the memory device of Figure 5A is programmed in the
- nitride 20 is a nonconductor, the trapped charge remains localized to the region near the
- drain for the right bit, for example.
- the left bit is similar except that source and drain
- the threshold voltage rises, for example, to approximately 4V
- the remainder of the channel remains at, for example, approximately 1 V.
- drain 16 is grounded. A major difference between reading in the forward direction and
- reading in the reverse direction is that when reading in the reverse direction, the gate
- the source 14 (which functions as the drain in read) is not inverted because 2V is applied to
- the source 14 and the channel, to be inverted must be inverted relative to 2 V.
- Figure 5A similar to the voltage drop achieved when reading the same device in the forward direction, a higher gate voltage is required, for example, 4 V. This is in contrast to
- FIG. 4 shows that a programming time of
- the cell is read in the forward direction.
- Fig. 4 shows the difference in charge (measured as a function of programming time required to achieve a given threshold
- temperature retention bake typically requires temperatures between 150 degrees Centigrade
- memory cells is particularly prone to lateral diffusion and dispersion through the nitride
- the memory cell is read in the forward direction. Accordingly, the internal electric fields
- nitride does not disperse laterally through the nitride due to the internally self generated
- the drawn width of the channel measures 0.6 microns and the drawn length of the channel measures 0.65
- V DSAT V DSAT
- V D the drain voltage
- the forward curve can represent a logic '0' and the reverse curve a logic T.
- the voltage V x is defined as the voltage in the channel at a distance X from the
- the channel will be in saturation as long as the gate
- V G is higher than the threshold voltage V ⁇ and the voltage V x at any point in the
- V v X V v DSAT with
- V T (V X ) V T0 + ⁇ V T (V X )
- the threshold voltage in the channel is equal
- V x spanning the distance from the drain to the edge 27 of the channel under the edge 25 of the charge trapping area for one of the two bits while reading in the reverse
- the threshold voltage is zero. In this case, the threshold voltage is constant along the entire channel.
- the threshold voltage is not constant along
- the threshold voltage increases nonlinearly as the
- threshold voltage as a function of channel voltage is well known in the art. A more
- V G For a particular drain voltage, e.g., 2V, applying a high enough V G such as 5V,
- V G should lie. If V G is too low, insufficient current is developed in the channel. On the
- the 1 ⁇ , level for the lower two curves is 1 ⁇ A, and is 40
- threshold voltages start to separate from each other at a V D of approximately 0.35V while
- each bit i.e., the bit
- the left bit is programmed by applying prograrnming voltages to the
- the right bit is shown being programmed while the left bit is read.
- the threshold is shown being programmed while the left bit is read.
- This graph also illustrates the read through of the programmed right bit in order to perform
- the second pass is represented by the curves RIGHT BIT-PASS #2 and LEFT BIT-PASS
- the gate voltage during programming is
- charge trapping region to be formed at both the right side and the left side of charge trapping layer 20 which is easy to be punched through when the bit is read in the forward
- left bit 70 the charge trapping region 70 is referred to as a bit
- bit 68 is being read in the reverse direction.
- prograrnming voltage is not being applied to the drain for the bit previously programmed.
- the programming voltage is applied to the drain for the
- the programming duration must be limited for each bit in
- worst case may appear to be a logic '0' because the over-programmed right bit prevents the
- variable parameters is the voltage that is applied to the functional drain region during read. As the drain voltage is increased, a longer
- the upper limit of the programming time for the window is the programming time such
- the percentage compared to the read current for a reverse read is compared to the percentage compared to the read current for a reverse read.
- a designer may wish to have three orders of magnitude margin between the
- the gate voltage, drain voltage and implant level are all adjusted accordingly to determine a
- the second bit can be programmed as long as the
- gate voltage during programming is higher than the threshold voltage of the channel with
- each bit is treated as if the
- the right bit is read in the reverse direction by applying read voltages to the source 14 and
- a read of, the two bit memory device of -the present invention falls into one of
- the second case requires reading through the programmed bit to read the
- the margin is the delta between reading a single bit in the
- the third case requires read through to read both programmed bits.
- the sense amplifier circuitry is required to distinguish between two states
- the sense amplifiers must also distinguish between only two states:
- the programmed bit may cause the channel to be
- the read current In order to read, for example, the right bit 68, the read current must be
- the charge trapping region must be short enough to
- the two bit transistor may need to be scaled by a smaller
- V ⁇ high V ⁇
- V ⁇ low V ⁇
- the first is the V G , applied during reading and the second is the width of
- Hayes a major disadvantage of the Hayes prior art insulated gate device is the difficulty in
- oxide-nitride structure as opposed to an oxide-nitride-oxide structure is that during
- top oxide layer lowers the ability to control where the charge is stored in the nitride layer
- the relatively thick nitride layer causes the charge trapping region to be very wide thus
- Avalanche breakdown involves hot hole injection and requires relatively high voltages on
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU85589/98A AU8558998A (en) | 1997-08-01 | 1998-08-02 | Two bit non-volatile electrically erasable and programmable semiconductor memor ycell utilizing asymmetrical charge trapping |
JP2000505640A JP2001512290A (en) | 1997-08-01 | 1998-08-02 | 2-bit non-volatile electrically erasable programmable semiconductor memory cell using asymmetric charge trapping |
IL13430498A IL134304A (en) | 1997-08-01 | 1998-08-02 | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
IL15728998A IL157289A0 (en) | 1997-08-01 | 1998-08-02 | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
EP98936654A EP1010182A4 (en) | 1997-08-01 | 1998-08-02 | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/905,286 US6768165B1 (en) | 1997-08-01 | 1997-08-01 | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US08/905,286 | 1997-08-01 |
Publications (2)
Publication Number | Publication Date |
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WO1999007000A2 true WO1999007000A2 (en) | 1999-02-11 |
WO1999007000A3 WO1999007000A3 (en) | 1999-04-08 |
Family
ID=25420566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IL1998/000363 WO1999007000A2 (en) | 1997-08-01 | 1998-08-02 | Two bit eeprom using asymmetrical charge trapping |
Country Status (6)
Country | Link |
---|---|
US (8) | US6768165B1 (en) |
EP (1) | EP1010182A4 (en) |
JP (1) | JP2001512290A (en) |
AU (1) | AU8558998A (en) |
IL (1) | IL134304A (en) |
WO (1) | WO1999007000A2 (en) |
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Also Published As
Publication number | Publication date |
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EP1010182A2 (en) | 2000-06-21 |
US7116577B2 (en) | 2006-10-03 |
US20050111257A1 (en) | 2005-05-26 |
JP2001512290A (en) | 2001-08-21 |
EP1010182A4 (en) | 2000-09-27 |
US6768165B1 (en) | 2004-07-27 |
US6649972B2 (en) | 2003-11-18 |
IL134304A (en) | 2004-07-25 |
IL134304A0 (en) | 2001-04-30 |
WO1999007000A3 (en) | 1999-04-08 |
US20090032862A1 (en) | 2009-02-05 |
US20060262598A1 (en) | 2006-11-23 |
US20070206415A1 (en) | 2007-09-06 |
AU8558998A (en) | 1999-02-22 |
US7405969B2 (en) | 2008-07-29 |
US6011725A (en) | 2000-01-04 |
US20030011020A1 (en) | 2003-01-16 |
US20080111177A1 (en) | 2008-05-15 |
US7400529B2 (en) | 2008-07-15 |
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