WO1998042015A1

WO1998042015A1 - Method of producing a vertical mos transistor

Info

Publication number: WO1998042015A1
Application number: PCT/EP1998/001405
Authority: WO
Inventors: Thomas Aeugle; Wolfgang RÖSNER; Lili Vescan; Dag Behammer
Original assignee: Siemens Aktiengesellschaft; Forschungszentrum Jülich GmbH; RUHR-UNIVERSITäT BOCHUM
Priority date: 1997-03-19
Filing date: 1998-03-11
Publication date: 1998-09-24
Also published as: DE19711481A1; TW392254B

Abstract

In order to produce a vertical MOS transistor, a mask (13) with an opening is formed on a semiconductor substrate. Grown in the opening by selective epitaxy is a layer sequence (14) comprising a lower source/drain region (141), a channel region (142) and an upper source/drain region (143). Facets are formed at the edge such that the layers are thinner at the edge than in the centre. A gate dielectric (16) and gate electrode are formed at the edge of the layer sequence.

Description

description

Method of manufacturing a vertical MOS transistor.

With regard to ever faster components with a higher integration density, the structure sizes of integrated circuits decrease from generation to generation. This also applies to CMOS technology. It is generally expected (see, for example, Roadmap of Semiconductor Technology, Solid State Technology 3, (1995)) that MOS transistors with a gate length of less than 100 nm will be used around the year 2010.

On the one hand, attempts are being made to develop planar MOS transistors with such gate lengths by scaling today's common CMOS technology (see, for example, A. Hori, H. Nakakaka, H. Umimoto, K. Yamashita, M. Takase, N Shimizu, B. Mizuno, S. Odanaka, A 0.05 μ-CMOS with Ultra Shallow Source / Drain Junctions Fabricated by 5 keV Ion Implantation and Rapid Thermal Annealing, IEDM 1994, 485 and H. Hu, LT Su, Y. Yang, DA Antoniadis, HI Smith, Channel and Source / Drain Engineering in High-Performance sub-0.1 um NMOSFETs using X-Ray lithography, Sympl. VLSI Technology, 17, (1994)). Producing such planar MOS transistors with channel lengths below 100 nm requires the use of electron beam lithography and has so far only been possible on a laboratory scale. The use of electron beam lithography leads to a disproportionate increase in development costs.

At the same time, vertical transistors are being investigated to achieve short channel lengths (see, for example, L. Risch, WH Krautschneider, F. Hofmann, H. Schäfer, Vertical MOS Transistor with 70 nm Channel length, ESSDERC 1995, pages 101 to 104). Layer sequences corresponding to source, channel and drain are formed, which are surrounded in a ring by the gate dielectric and gate electrode. These vertical MOS transistors have been compared to planar MOS transistors in terms of their high-frequency and logic properties unsatisfactory. This is attributed on the one hand to parasitic capacitances of the overlapping gate and on the other hand to the formation of a parasitic bipolar transistor in the vertical layer sequence.

The invention is therefore based on the problem of specifying a method for producing a vertical MOS transistor in which the high-frequency and logic properties of the vertical MOS transistor can be compared with those of planar MOS transistors.

This problem is solved according to the invention by a method according to claim 1. Further refinements of the invention emerge from the remaining claims.

In the method, a mask with an opening is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate being exposed within the opening. In this opening, a layer sequence is grown by selective epitaxy, each of which has a layer for a lower source / drain region, a channel region and an upper source / drain region. When the layer sequence is grown, facets are formed at the edge of the layer sequence, so that the thickness of the layers at the edge of the opening is less than in the middle. Gate dielectric and gate electrode are formed at the edge of the layer sequence.

In the process, the knowledge is exploited that facets form in the selective epitaxy at the edges of a mask, since the growth rate at the edges at these edges. selective epitaxy is lower. An investigation into the formation of facets in selective epitaxy is, for example, from L. Vescan, Radiative recombination in SiGe / Si dots ... r, Mater. Science and Eng. B28, 1-8 (1994).

This property of selective epitaxy is used to reduce the thickness of the layers at the edge of the layer sequence than to realize in the middle of the layer sequence. It is thereby achieved that the base width of the parasitic bipolar transistor, which forms in the middle of the layer sequence, is larger than the channel width of the vertical MOS transistor, which is formed at the edge of the layer sequence. The channel properties are therefore decoupled from the volume properties in the layer sequence. Since the parasitic bipolar transistor has a larger base width than the channel length of the vertical MOS transistor, the vertical MOS transistor determines the properties of the structure.

The mask preferably has SiO 2 and / or Si3N4 at least on the surface. Using a mask made of these materials, the thickness ratio between the middle and the edge of the layer sequence can be set between 2 and 3 depending on the growth conditions.

It is within the scope of the invention to form a first insulating layer, a conductive layer and a second insulating layer over the entire surface when the mask is formed, in which the opening is produced. Before the selective epitaxy to form the layer sequence, the gate dielectric is formed on the exposed surface of the conductive layer. The gate electrode is formed from the conductive layer. This method has the advantage that the side wall of the

Layer sequence in the manufacture of the gate dielectric and the gate electrode is no longer subjected to an etching process.

The lower source / drain region is preferably grown at such a height that it closes with the first insulating layer at the edge of the opening. The channel region is grown in height such that it ends at the edge of the opening with the ^"conductive layer. In this way the advertising, the parasitic capacitances of the gate electrode is minimized, resulting in a further improvement in high frequency characteristics. It is also within the scope of the invention to form the mask from insulating material. After the layer sequence has been formed, the side wall of the channel region is then exposed such that the side wall of the lower source / drain region remains essentially covered by the insulating material of the mask. The gate dielectric and the gate electrode are then formed on the exposed side wall of the channel region, the height of the gate electrode preferably being matched to the height of the channel region.

In this embodiment too, the capacitances of the gate electrode are minimized, which leads to an improvement in the high-frequency properties. The gate electrode is formed, for example, by depositing and structuring a conductive layer.

The mask is preferably formed from insulating material, in this case from a first insulating layer and a second insulating layer. The first insulating layer is arranged on the main surface of the substrate. The second insulating layer is arranged on the first insulating layer. The second insulating layer can be etched selectively with respect to the first insulating layer and the layer sequence. In this case, the lower source / drain region is grown to such a height that it is flush with the first insulating layer at the edge of the opening. After the layer sequence has grown, an opening is formed in the second insulating layer, which surrounds the channel region in a ring. After the gate dielectric has been formed, the opening is filled with a conductive layer.

The gate electrode is finally formed by structuring the conductive layer, for example with the aid of planarization steps.

It is particularly advantageous here for the opening in the second insulating layer to protrude significantly beyond the layer sequence on at least one side of the layer sequence allow. In this case, the opening has an expansion on at least one side of the layer sequence. In the area of this expansion, island-shaped auxiliary structures made of the material of the second insulating layer are arranged. As a result, the opening in the region of the widening has a lattice-shaped cross section. The conductive layer also fills the opening in the area of the expansion. As a result, the gate electrode also has a grid-shaped cross section, at least in part. In the area of the widening, a contact hole to the gate electrode can subsequently be opened, which can be considerably coarser in its structural fineness than the structures of the opening. In this way, the contact hole can be dimensioned such that electrical properties of the gate contact are optimized.

A further improvement of the high-frequency properties by minimizing the parasitic capacitances is achieved in that the layer sequence is structured in a ring shape and the ring structure layer sequence is provided with an insulating filling. The removal of the semiconductor material in the interior of the layer sequence suppresses the formation of space charge zones, which in turn cause parasitic capacitances.

The invention is explained in more detail below on the basis of exemplary embodiments which are illustrated in the figures.

FIG. 1 shows a section through a semiconductor substrate with a connection region and a mask.

FIG. 2 shows the section through the semiconductor substrate after formation of a layer sequence by selective epitaxy. FIG. 3 shows the section after the formation of an opening which surrounds the layer sequence in a ring and the formation of a gate dielectric.

FIG. 4 shows a top view of FIG. 3.

Figure 5 shows the section shown in Figure 3 after filling the opening with a conductive layer and creating a planarizing insulation layer.

FIG. 6 shows the section after formation of a gate electrode by structuring the conductive layer.

Figure 7 shows the section after opening of contact holes.

FIG. 8 shows the section after the formation of metal silicide connection surfaces, a passivation layer and contacts.

FIG. 9 shows a section through a semiconductor substrate with a connection region and a mask.

Figure 10 shows the section after formation of a layer sequence by selective epitaxy.

FIG. 11 shows the section after forming an opening which surrounds the layer sequence in a ring.

FIG. 12 shows the section after formation of a gate electrode, a passivation layer and contacts.

Figure 13 shows a section through a semiconductor substrate having a terminal area and a mask having a conductivity ^"compatible layer, is formed on the surface of a Ga tedielektrikum. FIG. 14 shows the section after formation of a layer sequence by selective epitaxy and deposition and planarization of an insulating layer.

FIG. 15 shows the section after etching back the insulating layer and forming spacers on the side walls of the mask.

FIG. 16 shows the section after the layer sequence has been structured in a ring using the spacer as a mask, the surface of the connection region being exposed.

FIG. 17 shows the section after the annularly structured layer sequence has been provided with an insulating filling and after the formation of contacts.

The representations in the figures are not to scale.

In a first exemplary embodiment, a connection region 12 is placed in a substrate 11 made of monocrystalline silicon, for example a monocrystalline silicon wafer or the monocrystalline silicon layer of an SOI substrate, by implantation with arsenic or phosphorus with 5 × 10 ¹ ^ _c 2 _# 40 k _e y and Subsequent annealing to activate the dopant is formed (see Figure 1).

A mask 13 is then formed on the substrate 11. For this purpose, a silicon nitride layer 131 with a thickness of, for example, 70 nm is applied over the entire surface and a silicon oxide layer 132 with a thickness of, for example, 500 nm is applied thereon. The silicon oxide layer 132 and the silicon nitride layer 131 are subsequently patterned by anisotropic etching, an opening 130 being formed. The surface of the connection region 12 is exposed within the opening 130. Within the opening 130, a layer sequence 14 is grown by selective epitaxy, which has a first layer 141 for a lower source / drain region, a second layer 142 for a channel region and a third layer 143 for an upper source / drain region (see Figure 2). The first layer 141 is grown, for example, from n-doped silicon with a dopant concentration of 5 × 10 - ^ - 9 c ^~ 3 in a layer thickness of 100 nm. The second layer 142 is grown, for example, from p-doped silicon with a dopant concentration of lO ¹ ^ cm ^~ 3 in a layer thickness of 100 nm. The third layer 143 is of n-doped silicon with a dopant concentration of 5 x lO ^ ¹ cm ^~ 3 nm grown in a layer thickness of 200th The selective epitaxy is carried out in such a way that facets are formed at the edge of the opening 130. That is, the first layer 141, second layer 142 and the third layer 143 have a smaller layer thickness at the edge of the opening 130 than in the center of the opening 130. The specified layer thicknesses apply to the center of the opening. The selective epitaxy is carried out, for example, using the following process gases Si2H2Cl2 B2H, ASH3, PH3, HC1, H2 in the temperature range between 700 to 950 ° C. and the pressure range between 5 to 20,000 Pa on silicon wafers with a [110] fat orientation . The first layer 141 is grown in such a way that its thickness at the edge of the opening 130 approximately corresponds to the thickness of the silicon nitride layer 131.

Using a photolithographically generated mask (not shown), an opening 15 is then formed in the silicon oxide layer 132 which covers the side walls of the

Layer sequence 14 exposed (see Figure 3 and supervision in Figure 4). The surface of the silicon nitride layer 131 is exposed in the opening 15. The opening 15 has a widening 150 to the side of the layer sequence 14, in which inseil-shaped structures 132 'made of the material of the silicon oxide layer

132 are arranged (see Figure 4). The insular structures 132 'are arranged in a matrix, so that the opening 15 has a lattice-shaped cross section in the area of the widening 150.

The opening 15 overlaps the layer sequence 14 laterally. Since the adjustment in lithographic processes is more precise than the minimum structure size, the distance between the layer sequence 14 and the structured silicon oxide layer 132 is less than a minimum structure size. When using a lithography with a minimum structure size of 0.6 μm and an alignment accuracy of 0.2 μm, the distance between the layer sequence 14 and the silicon oxide layer 132 or the island-shaped structures 132 ′ is, for example, 0.3 μm. The structure size of the island-shaped structures 132 'is in each case a minimum structure size, for example 0.6 µm.

A thermal dielectric is subsequently formed on the exposed surface of the second layer 142 and the third layer 143 from SiO 2 in a layer thickness of 3 to 5 nm.

A conductive layer 17 is then deposited over the entire surface. The thickness of the conductive layer 17 is adjusted so that the space between the layer sequence 14 and the silicon oxide layer 132 is filled. All materials that are suitable as gate electrodes are suitable for the conductive layer 17, in particular doped polysilicon, metal silicide, metal. The conductive layer 17 is formed, for example, from n-doped polysilicon in a layer thickness of 400 nm (see FIG. 5). A planarization layer 18 is then formed on the conductive layer 17, for example from photoresist or another spin-on material. The surface of the conductive layer 17 is leveled, for example, by planarization etching or chemical mechanical polishing. Subsequently, the conductive layer 17 is etched highly selectively to SiO 2. It will be from a conductive electrode 170 is formed in the conductive layer 17 (see FIG. 6).

A further SiO 2 layer is then applied over the entire surface in a layer thickness of, for example, 70 nm and structured with the aid of a photoresist mask 19. The surface of the connection region 12, the gate electrode 170 and the third layer 143 are partially exposed (see FIG. 7).

Self-aligned siliconization, for example in a salicide process with titanium, forms silicide connections 110 on the exposed surface of the connection region 12, the gate electrode 170 and the third layer 143 (see FIG. 8). The silicide connections 110 each serve to reduce the parasitic series resistances.

After application of a passivation layer 111 over the entire surface, for example made of SiO 2 in the contact holes to the silicide connections 110 to the connection region 12 and to the third layer 143 and to the gate electrode 170, contacts 112 to the connection region 12 are formed by forming a metal layer and structuring the metal layer third layer 143, which forms the upper source / drain region, and to the gate electrode 170. The contact hole to the gate electrode 170 is not visible in the section shown in FIG. 8. It is located in the area of the widening 150 (see FIG. 4). Due to the grid-like structure of the gate electrode 170 in the area of the widening 150 (see FIG. 4), it is possible to provide the contact hole to the gate electrode 170 with a larger cross section than corresponds to the structure sizes of the gate electrode 170 in this area. The contact hole to the gate electrode 170 overlaps one or more of the island-shaped structures 132 '.

In a substrate 21, for example a monocrystalline silicon wafer or the monocrystalline silicon layer one In a second exemplary embodiment, SOI substrate is formed, for example, by masked implantation and subsequent tempering to heal the implantation damage. A mask 23 is then formed on the surface of the substrate 21, which has an opening 230 in which the surface of the connection region 22 is exposed (see FIG. 9).

To form the mask 23, a connection layer 231, a silicon nitride layer 232 and a silicon oxide layer 233 are applied to the substrate 21. The connection layer 231 is formed, for example, from highly doped polysilicon in a layer thickness of 50 nm. All electrically conductive materials, in particular doped polysilicon, silicide, metal, are suitable for the connection layer 231. The silicon nitride layer 232 is applied in a layer thickness of 20 nm. The silicon oxide layer 233 is applied in a layer thickness of, for example, 500 nm.

Using a photolithographically generated mask

(not shown), the connection layer 231, the silicon nitride layer 232 and the silicon oxide layer are structured by anisotropic etching, for example with CHF3, O2 (for nitride, oxide) HBr, CI2 He, O2 (for polysilicon). The opening 230 is thereby formed. Silicon oxide spacers 234 are subsequently formed on the side walls of the connection layer 231, the silicon nitride layer 232 and the silicon oxide layer 233 facing the opening 230 by conformal deposition and anisotropic etching back. The silicon oxide spacers have a width of 10 nm (see FIG. 9).

By means of selective epitaxy, a layer sequence ^" 24 is grown in the opening 230, which has a first layer 241 for a lower source / drain region, a second layer 242 for a channel region and a third layer 243 for an upper source / drain region (see FIG 10) .The selective epi- co o to to P> cn CD cn o cn o cn

to co to to P ¹ cn σ cn o cn cn

P ¹ co

co co t to P ^» P ¹ cn D cn o cn o cn

co co to to P> cn o cn o cn o cn

, _,

Layer 312 contacts 312 to the gate electrode 370, to the polysilicon layer 35 and to the connection region 32 are subsequently formed.

Claims

claims

1. Method for producing a vertical MOS transistor,

- In which a mask (13) with an opening (130) is formed on a main surface of a semiconductor substrate (11), in which the main surface is exposed,

- in which a layer sequence (14) is grown in the opening (130) by selective epitaxy, each of which has a layer (141, 142, 143) for a lower source / drain region, a channel region and an upper source / drain region, wherein facets are formed at the edge of the layer sequence (14), so that the thickness of the layers (141, 142, 143) at the edge of the opening (130) is less than in the middle,

a gate dielectric (16) is formed which adjoins a surface of the channel region (142),

- In which a gate electrode (170) is formed, which is adjacent to the gate dielectric (16).

2. The method according to claim 1, wherein the mask (13) has at least on the surface silicon oxide and / or silicon nitride.

3. The method according to claim 1 or 2,

in which a first insulating layer (331, 332), a conductive layer (370) and a second insulating layer (333) are formed to form the mask (33), in which the opening (330) is produced, - in which the gate dielectric (36) is formed before the selective epitaxy to form the layer sequence (34) on the exposed surface of the conductive layer (370),

- In which the gate electrode (370) is formed from the conductive layer.

4. The method of claim 3, wherein at the edge of the opening (330) the lower source / drain region (341) in height substantially with the first insulating layer and the channel region (342) in height substantially with the conductive layer (370) completes.

5. The method according to claim 1 or 2,

- in which the mask (13) is formed from insulating material,

- in which after the formation of the layer sequence (14) the side wall of the channel region (142) is exposed in such a way that the side wall of the lower source / drain region (141) remains essentially covered by the insulating material of the mask (131)

- on the exposed side wall of the canal area

(142) the gate dielectric (16) and the gate electrode (170) are formed.

6. The method according to claim 5,

- In which the mask (13) from a first insulating

Layer (131) and a second insulating layer (132) is formed, wherein the first insulating layer (131) is arranged on the main surface and on the first insulating layer (131) the second insulating layer (132) and wherein the second insulating layer (132) selective to the first insulating layer (131) and the layer sequence (14) can be etched,

- in which the lower source drain region (141) is essentially level with the first insulating layer (131),

- in which an opening (130) is formed in the second insulating layer (132) and surrounds the channel region (142) in a ring shape,

- in which, after formation of the gate dielectric (16), the opening is filled with a conductive layer (17),

- In which the gate electrode (170) is formed by structuring the conductive layer (17).

7. The method according to claim 6,

- In which the opening (15) in the second insulating

Layer (132) has an expansion (150) on at least one side of the layer sequence (14) and island-shaped structures (132 ') are arranged in the area of the expansion (150), so that the opening (15) in the area of the expansion ( 150) has a grid-shaped cross section,

- In which the conductive layer (17) fills the opening (15) in the region of the widening (150).

8. The method according to any one of claims 1 to 7, in which the layer sequence (34) is structured in a ring and in which the ring-structured layer sequence (34) is provided with an insulating filling (39).