WO1995010899A1

WO1995010899A1 - Forming a higher hierarchy level signal in a synchronous digital communication system

Info

Publication number: WO1995010899A1
Application number: PCT/FI1994/000461
Authority: WO
Inventors: Esa Viitanen; Vesa Kemppainen; Kari Sahlman; Toni Oksanen; Jari Patana
Original assignee: Nokia Telecommunications Oy
Priority date: 1993-10-14
Filing date: 1994-10-13
Publication date: 1995-04-20
Also published as: FI934543A; FI934543A0; FI94699C; GB2297228A; AU7815294A; DE4497673T1; GB2297228B; GB9607821D0; FI94699B

Abstract

The invention relates to a method and a circuit arrangement for forming a higher hierarchy level signal in a synchronous digital communication system. According to the method, (a) several lower hierarchy level signals are formed by means of separate circuits (22), and (b) a higher hierarchy level signal is formed by combining several lower level signals into one higher level signal. To form a higher hierarchy level signal as simply as possible, said separate circuits (22) are chained by means of a common bus (51) into a chain where said bus connects the separate circuits (22), in each circuit (22) the data of the channels to be formed by that circuit is added to the time slots corresponding to these channels in a higher hierarchy level frame, to the data of channels possibly added already in the other circuits of the chain, and the formed signal is connected forward from the circuit at the end of the chain.

Description

Forming a higher hierarchy level signal in a synchronous digital communication system

The invention relates to a method according to the preamble of the appended claim 1 and a circuit arrangement according to the preamble of the appended claim 3 for forming a higher hierarchy level signal in a synchronous digital communication system. The solution according to the invention is intended for use in particular in devices of the SDH system, but the invention is applicable in the corresponding American SONET system as well, or in any other corresponding system where the frame structure consists of a predetermined number of bytes having a fixed length.

In synchronous digital systems, such as the SDH system, a higher hierarchy level signal is formed by time-divisionally combining lower hierarchy level signals. The contents of a higher hierarchy level signal vary according to from which level and how the construction of the signal has started. Thus an STM-1 signal may comprise for example 3 TU-3 signals, 21 TU-2 signals or 63 TU-12 signals. This description uses as an example the last case, where one higher hierarchy level signal, i.e. an STM-1 signal, comprises 63 TU-12 signals.

When a higher hierarchy level signal comprises several lower hierarchy level signals, the lower level signals are mapped in a higher level frame by using interleaving, so that the first bytes of each lower level signal come first in succession, after that the second bytes, etc. Thus, when an STM-1 signal comprises for example the aforementioned 63 TU-12 signals, these are located in the STM-1 frame in such a way that first comes the first byte of the first TU-12 signal, after that the first byte of the second TU-12 signal, etc. After the first byte of the last, or the 63rd, TU-12 signal comes the second byte of the first TU-12 signal, etc. One row (the length of which is 270 bytes) of the STM-1 frame comprises four bytes and the whole frame comprises 4x9=36 bytes of each TU-12 signal. The length of one entire TU-12 frame is 500 μs, so in the basic case it is divided into four successive STM-1 frames. The frame structures shortly described above and the SDH system itself are described in greater detail for example in Finnish Patent Application 922,657 and in references mentioned in the application, which are referred to for a more detailed description.

Figure 1 shows a common way of combining several signals to the same line for forming a higher hierarchy level signal. In this case, combining is provided by means of a separate circuit or a circuit board, and all the lower level signals, i.e. in the case of the aforementioned example 63 TU-12 signals, are applied to the inputs of a multiplexer 11 formed on the circuit or circuit board. Control is provided to the select input of the multiplexer in a control unit 12 by means of a frame-synchronizing signal FSYNC and a clock signal CLK. A control word indicates which of the input signals is to be selected to the output of the multiplexer in each particular situation.

The drawback of this kind of solution is that the combining has to be provided by one (large) circuit, which will prevent all signals from getting through if it breaks down.

Another common method is to realize the multiplexing by means of ASICs (Application Specific Integrated Circuit) and tristate buffers. This alternative is described in the accompanying Figure 2. A higher hierarchy level signal, for example an STM-1 signal, is formed on a data bus DBUS (formed for example on the mother board of the device) , which is controlled by means of adjacent circuit boards 21, which are mutually similar. Each circuit board comprises one or more ASICs 22, each of which forms one lower hierarchy level signal (channel) to the higher hierarchy level signal to be formed on the bus. Each ASIC controls the bus (controlled by a clock signal CLK) in its own turn in relation to the frame-synchronizing signal FSYNC by means of its own tristate buffer 23. The advantage of this solution is that an individual circuit board can be removed from the device without disturbing the traffic on the bus (only the traffic of the time slots corresponding to that particular board is left out). However, since each channel requires its own tristate buffer, the practical implementation will contain numerous conductors, for example in the case of 63 channels, 63x8 conductors outbound from the circuit boards (when the byte length is 8 bits). Another drawback of this solution is that it is power-consuming. To reduce the number of conductors from the circuit board, the signals to be formed on the board can be multiplexed before they are connected to the bus, as the accompanying Figure 3 shows. In this case, all ASICs on the same circuit board 21 have their own multiplexer 31, which multiplexes all the channels formed on the board through an output bus 32 to the common bus DBUS. The multiplexer of each circuit board controls the common bus DBUS in its own turn in relation to the frame- synchronizing signal FSYNC by means of its tristate buffer 33.

One disadvantage of this solution is that the multiplexer circuit and the tristate buffer occupy a great deal of space on each circuit board. Since in practice it is also desired to improve the operating capacity of the apparatus by forming it of several adjacent circuit boards, this increases further the need for space as the number of multiplexers grows.

A multiplexer on a circuit board 21 can also be realized by means of an internal bus, in the same way as the multiplexer operation was provided in the embodiment of Figure 2 by means of an external bus. Figure 4 shows such an alternative where an internal bus 41 is formed on the circuit board 21, and each ASIC on the board controls the bus in its own turn in relation to the frame-synchronizing signal FSYNC. In this case, a tristate buffer 42 is formed in each ASIC, the ASIC controlling the internal bus 41 by means of the tristate buffer. Each circuit board comprises one common tristate buffer 43 through which the internal bus 41 controls the external bus DBUS common to all boards. The tristate buffer of each ASIC is connected to a common AND gate 44, which provides control to the common tristate buffer 43, thus attending to the control of the circuit board to the bus DBUS.

The alternative shown in Figure 4 would be the best of the alternatives presented above for forming a higher hierarchy level signal, if it did not have timing problems which require in practice that the speed of the internal bus is doubled. This is due to the fact that there are such big differences in the timings of the ASICs that there is a danger that two circuits control the internal bus simultaneously, whereupon the ASICs will break down. To ensure that there is no simultaneous control, the clock frequency has to be doubled, thus providing a security gap between two successive controls. This in turn considerably increases the power consumption of the device. The doubling of the clock frequency is used in several different applications as well as in commercial circuits. The purpose of the present invention is to eliminate the above problems and to provide a method and a circuit arrangement by means of which a higher hierarchy level signal can be formed as simply as possible. This object is achieved by means of a method and circuit arrangement according to the invention, the method being characterized by what is described in the characterizing portion of the appended claim 1, and the circuit arrangement being characterized by what is described in the characterizing portion of the appended claim 3.

The idea of the invention is to form a higher hierarchy level signal by chaining those circuits where lower hierarchy level signals are formed, and by combining, in each circuit in the chain, the data of those time slots the channels corresponding to which are formed in that particular circuit, to the higher hierarchy level frame structure.

For example the following advantages are achieved by means of the solution according to the invention:

- The ASIC requires no buffer circuits, which are difficult to control, and neither does the clock frequency need increasing. - There is no need for a big multiplexer in each ASIC.

- There is only one outbound data bus from the circuit board.

- A broken circuit does not break the adjacent circuits.

- No extra logic is needed in an individual ASIC.

In the following, the invention and its preferred embodiments will be described in greater detail with reference, by way of example, to Figures 5 to 8 in the accompanying drawings, in which

Figure 1 shows the forming of a higher hierarchy level signal in a known manner by one multiplexer circuit,

Figure 2 shows the forming of a higher hierarchy level signal in a second known manner by using tristate buffers,

Figure 3 shows the forming of a higher hierarchy level signal in a third known manner by using one common multiplexer circuit for each circuit board,

Figure 4 shows the forming of a higher hierarchy level signal in a fourth known manner by using an internal bus of the circuit board, Figure 5 shows the characterizing features of a circuit arrangement according to the invention for forming a higher hierarchy level signal,

Figure 6 shows the solution according to the invention in one ASIC, Figure 7 shows a counter used in the circuit of Figure 6 for compensating a delay, and

Figure 8 is a timing diagram which illustrates the operation of the elements shown in Figures 6 and 7.

Figure 5 shows the solution according to the invention according to which a higher hierarchy level signal is formed by chaining through ASICs, so that each circuit adds the data of its own time slots to the frame to be transmitted. An individual circuit board comprises

M ASICs: ASIC1, ASIC2, ...ASICM (different circuit boards may comprise mutually different numbers of circuits), and a bus 51 shared by the ASICs is formed on the circuit board in such a way that the bus extends from the first ASIC (ASICM) in the chain through each ASIC to the last ASIC (ASIC1) in the chain, thus chaining all ASICs together. The last ASIC in the chain is connected via a tristate buffer 52 common for the entire circuit board to control an external bus DBUS, where the higher hierarchy level signal, in this exemplary case the payload portion of an STM-1 signal, is formed. In addition to the data CH_DATA to be chained, an enable signal CH_EN to be chained is also transmitted between the ASICs in the chain, the enable signal being fed from the last ASIC (ASICl) in the chain to control the common tristate buffer of the circuit board. For example a totem-pole, open-collector or open-drain type transistor structure may be used as the tristate buffer.

Figure 6 shows the solution according to the invention in one ASIC in the chain. Firstly, each ASIC comprises a synchronizing unit 61, which indicates the serial number of the ASIC in the chain. This unit obtains its control information for example from the microprocessor (not shown in the figure) of the device, which supplies each ASIC with its own (programmable) delay value D_SEL indicating the serial number of the ASIC in the chain. In this example, the value of the last circuit (ASICl) in the chain is 4, the value of the second last circuit (ASIC2) is 6, the value of the last circuit but two (ASIC3) is 8, etc. The difference between the delay values of two successive ASICs is thus 2 (two clock cycles), which is used to compensate the delay caused in the chain by registers 70 and 72 (described f rther on) .

Figure 7 shows in greater detail the compensation of the chain delay in the synchronizing unit 61. The delay value D_SEL is applied to a counter 71, which counts continuously from zero to 9719 (the. figure results from the fact that there are 270 time slots in nine rows in an STM-1 frame, and the length of one TU-12 frame corresponds to four STM-1 frames, i.e. 9x270x4=9720). The last ASIC (ASICl) in the chain loads value 4 to the counter, when it obtains a synchronizing pulse in its input LD. Correspondingly, the second last ASIC (ASIC2) in the chain loads value 6 to the counter, when it receives a synchronizing pulse in its input LD. The different positions of the ASICs in the chain are compensated for by forming in this way a phase difference separately for each circuit with respect to the synchronizing signal. The value of the counter is incremented with each clock pulse, and after the counter has reached its maximum value it goes back to zero.

To return to Figure 6, each TU-12 channel in an ASIC is formed in its own channel unit 62, and there are thus N channel units when N TU-12 channels (N may be any arbitrary integer between 1 and 63 ) are formed in the ASIC. Data entering the first channel unit 62 is denoted by R1DATA, and data entering the last unit is correspondingly denoted by RNDATA. The corresponding clock signals are denoted by R1CLK and RNCLK. The data signals entering the channel units are typically 2048 kbit/s signals conforming to CCITT Recommendations G.703 or G.704. Since the TU-12 channels are formed in a manner known per se and their formation is not related to the actual inventive idea, it will not be discussed further in this connection. The channel units 62 also receive a signal

TU12_SYNC from the synchronizing unit 61, the signal indicating where the first TU-12 channel is to be located in the STM-1 frame and distinguishing the different quarters of the TU-12 frame from each other, and a signal TU12_EN indicating which time slots in the row of the STM-1 frame belong to the TU-12 channels. Each channel unit 62 also receives a control word SLOTX (X=1...N) consisting of 6 bits from the microprocessor of the device, the control word informing the channel unit about which TU-12 time slot it can use. According to this, the channel unit forms its own enable signal SLX_EN (X=1...N). These signals are connected to an encoder 64, each signal to its own input (0...N). The encoder encodes an enable signal for the multiplexer 65, the signal being fed to the select input SEL of the multiplexer. This enable signal determines from which input of the multiplexer a signal is selected in each case for the output of the multiplexer. The combining of the channels to be formed in that particular ASIC thus takes place in the multiplexer 65 in such a way that the multiplexer selects to its output the data of a channel indicated as active in each time slot (by means of the enable signal) .

In a second multiplexer 74 of the ASIC, the data of the channels from that particular ASIC is combined with the data of channels formed in previous ASICs of the chain. For this purpose, the output signal of the first multiplexer 65 is fed to the first input (input 1) of the second multiplexer 74, and chain data CH_DATA received from the bus 51 is fed via a register 70 formed by a D flip-flop to the second input (input 0) of the second multiplexer 74. The multiplexer 74 selects to its output either the chain data or one of the channels of its own ASIC (the data of the channel) . It must be noted that no D flip-flops 69 and 70, OR gate 68, or multiplexer 74 are needed in the first circuit of the chain. If the circuits are realized as ASICs, the aforementioned circuit elements are in the circuit, but not in use. A signal SLX_EN (X=1...N) is connected from each channel unit 62 to a corresponding input in the OR gate 67 comprising N inputs, whereby information is obtained from the output of the OR gate 67 if one of the TU-12 channels is active. The output of the OR gate is connected directly to the select input of the second multiplexer 74, this signal from the OR gate giving priority to transmitting the data of that particular ASIC over transmitting the chain data CH_DATA. The output of the OR gate 67 is also connected to the first input of the second OR gate 68. A chain enable signal CH_EN (cf. Figure 5) obtained from a register 69 formed by a D flip-flop is connected to the second input of the OR gate 68, the signal being fed from the previous ASIC to the input D of the register 69. In the second OR gate 68, the SL0TX_EN signals formed by that particular ASIC are combined to the chain enable signal formed by the SLOTX_EN signals formed by the previous ASICs in the chain. The combined signal is connected from the output of the register 71 formed by the D flip-flop either to the next ASIC (the input D of the register 69) in the chain, whereby it is shown as signal CH_EN, or if the circuit is the last ASIC in the chain, the signal is connected to control the tristate buffer 52 common to the circuit board, whereby it is shown as signal STM- 1_EN.

Figure 8 illustrates the timing of the chaining as an example concerning a few time slots. Topmost in the figure is the synchronizing signal FSYNC (which in this case has a frequency of 2 kHz, thus corresponding to the frequency of one TU-12 frame). This example shows the forming of the second, fourth, sixth and seventh TU- 12 channel of the STM-1 frame, and in this example they are formed in such a way that the second and seventh TU- 12 channel are formed in the second last ASIC (ASIC2) in the chain, and the fourth and sixth TU-12 channel are formed in the last ASIC (ASICl) in the chain. (It must be noted that each row in an STM-1 frame comprises first altogether 18 overhead and stuff bytes, and the TU-12 channels only begin with the counter number 18. In this case, an AU-4 pointer is selected to indicate a fixed place 522.) The first and fourth channel unit (signals SL1_EN and SL4_EN) from the second last ASIC are randomly selected, and so are the first and second channel unit (signals SL1_EN and SL2_EN) from the last ASIC. The horizontal row preceded by reference symbol 71:, shows readings of the counter 71. As the figure shows, the counter of the last ASIC in the chain has the value 4 after the synchronizing pulse, and correspondingly the counter of the second last ASIC (ASIC2) of the chain has the value 6. Taking into account the fact that the enable signals formed in the circuit ASIC2 pass through altogether three registers (cf. Figure 6) before they appear in the output of the last ASIC of the chain, and correspondingly the enable signals formed in the circuit ASICl pass through one register, an STM-1_EN signal according to the figure is obtained at the output of the last ASIC ( for these time slots). The first bytes (VI bytes) of TU-12 channels two, four, six and seven are thus obtained in the outbound higher hierarchy level signal STM-1_0UT.

Figure 8 only illustrated the operation for the TU-12 channels two, four, six and seven, but in reality the operation is similar for all channels, whereby a perfect payload portion of an STM-1 signal is formed. The final STM-1 signal is formed by adding the overhead bytes of a VC-4 frame and the overhead bytes of an STM-1 frame with their AU-4 pointers. This addition can be done in the last circuit of the chain or at later stages. Since the addition is performed in a manner known per se and is not related to the actual inventive idea, it will not be described in greater detail in this connection.

If all TU-12 channels are not to be formed on the same circuit board 21, but the operational reliability of the device is- to be improved by forming the channels on more than one adjacent circuit boards, as shown in Figure 5, the situation is the same, but the tristate buffer of each circuit board controls the external bus in those time slots the channels corresponding to which are formed on that circuit board. A higher hierarchy level signal is thus ultimately formed only on the external bus DBUS.

Even though the invention is described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but it can be modified in many ways within the scope of the inventive idea disclosed above and in the appended claims. For example, the circuit board can be realized by using MCM technology or the like (MCM, MultiChip Module, a circuit module comprising several circuit chips) instead of conventional circuit board technology. The separate circuit 22 in turn may be an ASIC, a commercially available IC circuit or a unit realized by means of MCM or circuit board technology. The terms "circuit" and "circuit board" must thus be understood in a broader sense as covering the alternatives described above.

Claims

Claims:

1. A method for forming a higher hierarchy level signal in a synchronous digital communication system, according to which method

- several lower hierarchy level signals are formed by means of separate circuits (22) ,

- a higher hierarchy level signal is formed by time-divisionally combining several lower level signals into one higher level signal, c h a r a c t e r i z e d in that

- said separate circuits ( 22) are chained by means of a common bus (51) into a chain, where said bus connects the separate circuits (22) , - in each circuit (22) the data of channels to be formed by said circuit is added to the time slots corresponding to these channels in a higher hierarchy level frame, to the data of channels possibly added already in other circuits of the chain, and - the formed signal is connected forward from the circuit at the end of the chain.

2. A method according to claim 1, c h a r a c t e r i z e d in that the higher hierarchy level signal is formed by means of circuits (22) located at least on two separate circuit boards (21) in such a way that all circuit boards drive a common external bus (DBUS) where the final higher hierarchy level signal is formed.

3. A circuit arrangement for forming a higher hierarchy level signal in a synchronous digital communication system, the circuit arrangement comprising separate circuits (22) by means of which several lower hierarchy level signals are formed, c h a r a c t e r i z e d in that - said separate circuits (22 ) are chained into one chain by means of a common bus ( 51 ) , which connects said circuits with each other,

- each circuit (22) comprises adding means (67, 74) for adding the data of the channels to be formed by said circuit to the time slots corresponding to these channels in a higher hierarchy level frame, to the data of channels possibly added already in other circuits of the chain, and - the circuit arrangement also comprises means

(52) for connecting the formed signal forward from the circuit (22) at the end of the chain.

4. A circuit arrangement according to claim 3, c h a r a c t e r i z e d in that said means comprise a tristate buffer (52), which drives the external bus (DBUS) .

5. A circuit arrangement according to claim 4, c h a r a c t e r i z e d in that it comprises several adjacent circuit boards (21), whereby the tristate buffer of each circuit board drives the external bus (DBUS) .