USRE43025E1 - Mixed composition interface layer and method of forming - Google Patents

Mixed composition interface layer and method of forming Download PDF

Info

Publication number
USRE43025E1
USRE43025E1 US12/566,533 US56653309A USRE43025E US RE43025 E1 USRE43025 E1 US RE43025E1 US 56653309 A US56653309 A US 56653309A US RE43025 E USRE43025 E US RE43025E
Authority
US
United States
Prior art keywords
layer
chemical element
interface layer
interface
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime, expires
Application number
US12/566,533
Inventor
Cem Basceri
Gurtej S. Sandhu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Priority to US12/566,533 priority Critical patent/USRE43025E1/en
Assigned to MOSAID TECHNOLOGIES INCORPORATED reassignment MOSAID TECHNOLOGIES INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Priority to US13/293,778 priority patent/US20120120549A1/en
Application granted granted Critical
Publication of USRE43025E1 publication Critical patent/USRE43025E1/en
Assigned to ROYAL BANK OF CANADA reassignment ROYAL BANK OF CANADA U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM Assignors: 658276 N.B. LTD., 658868 N.B. INC., MOSAID TECHNOLOGIES INCORPORATED
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BASCERI, CEM, SANDHU, GURTEJ S.
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MOSAID TECHNOLOGIES INCORPORATED
Assigned to CONVERSANT IP N.B. 868 INC., CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CONVERSANT IP N.B. 276 INC. reassignment CONVERSANT IP N.B. 868 INC. RELEASE OF SECURITY INTEREST Assignors: ROYAL BANK OF CANADA
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. CHANGE OF ADDRESS Assignors: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Assigned to ROYAL BANK OF CANADA, AS LENDER, CPPIB CREDIT INVESTMENTS INC., AS LENDER reassignment ROYAL BANK OF CANADA, AS LENDER U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Assignors: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Assigned to CPPIB CREDIT INVESTMENTS, INC. reassignment CPPIB CREDIT INVESTMENTS, INC. AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Assignors: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS) Assignors: ROYAL BANK OF CANADA, AS LENDER
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: CPPIB CREDIT INVESTMENTS INC.
Assigned to MOSAID TECHNOLOGIES INCORPORATED reassignment MOSAID TECHNOLOGIES INCORPORATED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: CONVERSANT INTELLECTUAL PROPERTY INC.
Adjusted expiration legal-status Critical
Assigned to MOSAID TECHNOLOGIES INCORPORATED reassignment MOSAID TECHNOLOGIES INCORPORATED CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED AT REEL: 058297 FRAME: 0458. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Assignors: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0272Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C23C16/029Graded interfaces
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/405Oxides of refractory metals or yttrium
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Definitions

  • the present invention relates to chemisorbed interface layers of mixed composition and methods of forming interfaces, including interface layers in electronic devices and methods of formation.
  • an interface forming method can include forming a first layer comprising a first chemical element and chemisorbing on the first layer an interface layer including the first chemical element intermixed with a second chemical element different from the first chemical element.
  • the interface layer can include at least one monolayer.
  • a second layer is formed on the interface layer and can contain the second chemical element.
  • the first layer might not contain the second chemical element.
  • the second layer might not contain the first chemical element.
  • the first layer can be conductive and the second layer can be insulative.
  • the first layer can include a metal other than Ta, such as Pt, and the second layer can include Ta 2 O 5 .
  • an electronic device interface forming method includes forming a first layer containing a first chemical element and chemisorbing a first portion of at least one monolayer over the first layer, the first portion including the first chemical element.
  • a second portion of the at least one monolayer can be chemisorbed over the first layer and include a second chemical element different from the first chemical element.
  • the first and second portions of the at least one monolayer can be contained in an interface layer.
  • a second layer can be formed on the interface layer and contain the second chemical element.
  • the first portion of the at least one monolayer can be chemisorbed on first parts of the first layer and the second portion of the at least one monolayer can be chemisorbed on second parts of the first layer.
  • an electronic device interface forming method can include forming a first device layer containing a first chemical element and chemisorbing a first unsaturated interface layer including the first chemical element on the first device layer.
  • the first interface layer can have a thickness of about 1 to about 10 monolayers.
  • a second unsaturated interface layer may be chemisorbed at least on the first device layer in areas not saturated by the first interface layer.
  • the second interface layer can contain a second chemical element.
  • a second device layer containing a second chemical element can be formed on the first and second interface layers.
  • An apparatus can include a first layer containing a first chemical element and an interface layer chemisorbed on the first layer.
  • the interface layer can contain a first chemical element intermixed with a second chemical element different from the first chemical element.
  • the apparatus can further include a second layer on the interface layer containing a second chemical element.
  • an electronic device in another aspect of the invention includes a first layer containing a first chemical element, a first portion of at least one monolayer chemisorbed on the first layer, a second portion of the at least one monolayer chemisorbed on the first layer, an interface layer comprising the first and second portions of the at least one monolayer, and a second layer on the interface layer.
  • the first portion can contain the first chemical element and the second portion can contain a second chemical element different from the first chemical element.
  • the second layer can contain the second chemical element.
  • FIG. 1 shows a sectional view of a substrate portion at a processing step according to an aspect of the invention.
  • FIG. 2 shows a sectional view of a substrate portion at a processing step subsequent to that shown in FIG. 1 .
  • FIG. 3 shows a sectional view of a substrate portion at a processing step subsequent to that shown in FIG. 2 .
  • FIG. 4 shows a sectional view of a substrate portion at a processing step subsequent to that shown in FIG. 3 .
  • ALD atomic layer deposition
  • ALD involves formation of successive atomic layers on a substrate. Such layers may comprise an epitaxial, polycrystalline, amorphous, etc. material. ALD may also be referred to as atomic layer epitaxy, atomic layer processing, etc. Further, the invention may encompass other deposition methods not traditionally referred to as ALD, for example, chemical vapor deposition (CVD), but nevertheless including the method steps described herein. The deposition methods herein may be described in the context of formation on a semiconductor wafer. However, the invention encompasses deposition on a variety of substrates besides semiconductor substrates.
  • semiconductor substrate or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
  • substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • ALD includes exposing an initial substrate to a first chemical species to accomplish chemisorption of the species onto the substrate.
  • the chemisorption forms a monolayer that is uniformly one atom or molecule thick on the entire exposed initial substrate. In other words, a saturated monolayer.
  • chemisorption might not occur on all portions of the substrate. Nevertheless, such an imperfect monolayer is still a monolayer in the context of this document.
  • the first species is purged from over the substrate and a second chemical species is provided to chemisorb onto the first monolayer of the first species.
  • the second species is then purged and the steps are repeated with exposure of the second species monolayer to the first species.
  • the two monolayers may be of the same species.
  • a third species or more may be successively chemisorbed and purged just as described for the first and second species.
  • Purging may involve a variety of techniques including, but not limited to, contacting the substrate and/or monolayer with a carrier gas and/or lowering pressure to below the deposition pressure to reduce the concentration of a species contacting the substrate and/or chemisorbed species.
  • carrier gases include N 2 , Ar, He, Ne, Kr, Xe, etc.
  • Purging may instead include contacting the substrate and/or monolayer with any substance that allows chemisorption byproducts to desorb and reduces the concentration of a contacting species preparatory to introducing another species.
  • a suitable amount of purging can be determined experimentally as known to those skilled in the art.
  • Purging time may be successively reduced to a purge time that yields an increase in film growth rate.
  • the increase in film growth rate might be an indication of a change to a non-ALD process regime and may be used to establish a purge time limit.
  • ALD is often described as a self-limiting process, in that a finite number of sites exist on a substrate to which the first species may form chemical bonds. The second species might only bond to the first species and thus may also be self-limiting. Once all of the finite number of sites on a substrate are bonded with a first species, the first species will often not bond to other of the first species already bonded with the substrate.
  • process conditions can be varied in ALD to promote such bonding and render ALD not self-limiting. Accordingly, ALD may also encompass a species forming other than one monolayer at a time by stacking of a species, forming a layer more than one atom or molecule thick.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • plasma enhanced CVD plasma enhanced CVD
  • ALD is commonly used to form non-selectively a complete, deposited material on a substrate.
  • One characteristic of CVD is the simultaneous presence of multiple species in the deposition chamber that react to form the deposited material. Such condition is contrasted with the purging criteria for traditional ALD wherein a substrate is contacted with a single deposition species that chemisorbs to a substrate or previously deposited species.
  • An ALD process regime may provide a simultaneously contacted plurality of species of a type or under conditions such that ALD chemisorption, rather than CVD reaction occurs. Instead of reacting together, the species may chemisorb to a substrate or previously deposited species, providing a surface onto which subsequent species may next chemisorb to form a complete layer of desired material.
  • chemisorption rate in ALD might be influenced by the composition, crystalline structure, and other properties of a substrate or chemisorbed species.
  • Other process conditions for example, pressure and temperature, may also influence chemisorption rate. Accordingly, observation indicates that chemisorption might not occur appreciably on portions of a substrate though it occurs at a suitable rate on other portions of the same substrate.
  • an interface forming method may include forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.
  • the method can further include forming a second layer containing the second chemical element on the interface layer.
  • the first and second layers can be formed by any method. Since the interface layer:contains the first chemical element, the interface layer can adhere well to the first layer. Also, since the interface layer contains the second chemical element, the interface layer also can adhere well to the second layer. Accordingly, the interface layer potentially can improve adherence of the second layer over the first layer.
  • the above described method can be particularly advantageous when the second layer might not adhere well to the first layer.
  • the first and second layer might not adhere well when the first layer does not substantially contain the second chemical element, the second layer does not substantially contain the first chemical element, or both.
  • Observation indicates that such circumstance can arise, for example, when the first layer is conductive and the second layer is insulative, or vice versa.
  • the method may be particularly useful when the first layer contains a metal other than Ta and the second layer contains Ta 2 O 5 .
  • the metal other than Ta can be Pt.
  • An exemplary metal-insulator-metal capacitor stack can include, respectively, Pt, Ta 2 O 5 , and Pt.
  • the interfacial properties in the stack can influence current leakage and other performance characteristics of the capacitor.
  • suitable adhesion of the stack layers maintains integrity of the device.
  • an interface layer can be formed between the Pt and Ta 2 O 5 that includes intermixed Pt and Ta 2 O 5 formed by ALD.
  • Such a concept can also be used to enhance adhesion of other materials, for example, adhesion of Pt and Ru to oxide containing surfaces, such as barium strontium titanate, lead zirconate titanate, Ta 2 O 5 , etc.
  • an electronic device interface forming method includes forming an interface layer between and in contact with a first layer containing a first chemical element and a second layer containing a second chemical element different from the first chemical element.
  • the interface layer can be formed separately from forming the first and second layers and contain the first and second chemical elements.
  • the interface layer can also be formed such that it does not substantially contain material from the first or second layers as separately formed.
  • the interface layer contains at least one monolayer of intermixed first and second chemical elements chemisorbed on the first layer.
  • the interface layer is described as not substantially containing material from the first or second layers to indicate that the method used to form the interface layer adds material to a surface of the preexisting first or second layer without reliance on material therein to form part of the composition of the interface layer. It is recognized that after formation of the interface layer, insignificant amounts of material from the first or second layers can potentially diffuse into the interface layer. However, such diffusion still allows formation of an interface layer not substantially containing material from the first or second layers.
  • Surface nitridation or surface oxidation as known to those skilled in the art are examples of methods that rely on existing materials to form part of a composition in a subsequently formed layer.
  • first layer does not substantially contain the second chemical element or the second layer does not substantially contain the first chemical element
  • first chemical element refers to the primary composition of the first or second layer excluding contaminants, trace elements, and diffused material from surrounding structures. Understandably, contaminants, trace elements, and diffused materials can potentially insignificantly alter the composition of the first or second layers in a manufacturing process without causing such layers to substantially contain the first or second chemical elements.
  • a still further aspect of the invention provides an electronic device interface forming method that includes forming a first layer containing a first chemical element, chemisorbing a first portion of at least one monolayer over the first layer, and chemisorbing a second portion of the at least one monolayer over the first layer.
  • the first portion of the at least one monolayer can contain the first chemical element.
  • the second portion of the at least one monolayer can contain a second chemical element different from the first chemical element.
  • the first and second portions of the at least one monolayer can form part of an interface layer.
  • the method can further include forming a second layer containing a second chemical element on the interface layer.
  • the first portion of the at least one monolayer can be chemisorbed on first parts of the first layer and the second portion of the at least one monolayer can be chemisorbed on second parts of the first layer.
  • an electronic device interface forming method includes forming a first device layer containing a first chemical element, chemisorbing a first unsaturated interface layer containing the first chemical element on the first device layer, and chemisorbing a second unsaturated interface layer at least on the first device layer in areas not saturated by the first interface layer.
  • the first interface layer can have a thickness of from about 1 to about 10 monolayers.
  • the second interface layer can have a thickness of from about 1 to about 10 monolayers and contain a second chemical element different from the first chemical element.
  • the method can further include forming a second device layer containing the second chemical element on the first and second interface layers.
  • a first device layer can be a capacitor plate while a second device layer can be a capacitor dielectric.
  • the first device layer can be a capacitor dielectric while the second device layer is a capacitor plate.
  • a substrate 2 is shown with a first layer 4 formed thereon.
  • a first material 6 is formed on parts of first layer 4 but not on other parts of first layer 4 , namely unsaturated areas 14 .
  • the first material 6 is shown in FIG. 2 as a graphical representation of individual molecules or atoms chemisorbed to the surface of first layer 4 .
  • a second material 8 is shown in graphical representation chemisorbed in formerly unsaturated areas 14 on first layer 4 .
  • the monolayer of first material 6 and monolayer of second material 8 formed in unsaturated areas 14 thus form an interface layer 10 .
  • Interface layer 10 can have a thickness of from about 1 to about 10 monolayers, or a greater thickness depending on a particular application.
  • FIG. 4 shows a second layer 12 formed on interface layer 10 with interface layer 10 shown as a material layer, rather than a graphical representation of chemisorbed molecules or atoms.
  • FIGS. 1-4 Although the preferred method described above in relation to FIGS. 1-4 includes separate formation of first material 6 and second material 8 on first layer 4 , the layers of first and second materials 6 , 8 could conceivably be formed simultaneously. Thus, the structure of FIG. 3 can be obtained by forming both first and second materials 6 , 8 on first layer 4 of FIG. 1 simultaneously rather than as shown in FIG. 2 .
  • An advantage of using ALD to form first and second materials 6 , 8 is that desired properties of interface layer 10 can be controlled at the atomic level. Interfacial properties such as dead layers, surface defects, vacancies, and impurities, as known to those skilled in the art can be improved with selection of suitable components for the interface layer and ALD processing conditions. For example, saturation of the surface of first layer 4 with intermixed first and second materials 6 , 8 can reduce vacancies at the interface between first layer 4 and second layer 12 . Further, selection of elements exhibiting suitable atomic diameters for interface layer 10 can improve the packing density of the interface between first layer 4 and second layer 12 . The reduction in defects at the interface can provide a better functioning device.
  • an interface layer formed according to the various aspects of the invention described above can improve adhesion between first layer 4 and second layer 12 .
  • Existing knowledge of those skilled in the art regarding adhesion between particular materials can be used to select a compositional ratio of first material 6 to second material 8 in interface layer 10 .
  • such information can be used to select potentially different compositional ratios for each monolayer formed as part of an interface layer.
  • interface layer 10 can have a fixed composition among monolayers.
  • a ratio of first material 6 to second material 8 may be selected and then processing structured to produce the fixed composition.
  • For an interface layer between Ta 2 O 5 and Pt about 5 monolayers of Pt can be chemisorbed on the Ta 2 O 5 followed by about 5 monolayers of Ta 2 O 5 . Additional alternating Pt and Ta 2 O 5 material can be added in about equal numbers of monolayers to a desired interface layer depth.
  • the resulting interface layer can exhibit about a 1:1 ratio of Pt to Ta 2 O 5 .
  • interface layer 10 can have a composition gradient among monolayers.
  • a beginning ratio of first material 6 to second material 8 may be initially selected and then altered as successive monolayers are added to form interface layer 10 .
  • a ratio proximate an inner surface of interface layer 10 can thus be different from a ratio proximate an outer surface of interface layer 10 .
  • For an interface layer between Ta 2 O 5 and Pt about 5 monolayers of Pt can be chemisorbed on the Ta 2 O 5 followed by about 5 monolayers of Ta 2 O 5 . Additional alternating Pt and Ta 2 O 5 material can be added with one further monolayer of Pt included in each turn.
  • Formation of Pt monolayers by ALD can be performed using a precursor pair of a cyclopentadienyl-platinum (Cp-Pt) complex and an oxidizer such as H 2 O, O 3 , O 2 , N 2 O, NO, isopropyl alcohol (IPA), mixtures thereof, and other oxidizers known to those skilled in the art.
  • Cp-Pt cyclopentadienyl-platinum
  • IPA isopropyl alcohol
  • the oxidizer may be pulsed for a time similar to Cp-Pt, followed by another purge to complete one cycle and to form one monolayer having a typical depth of about 1 Angstrom. Completion of five cycles can thus form 5 monolayers.
  • Formation of Pt monolayers by ALD can be performed in a similar manner alternatively using Cp-Pt, platinum-hexafluoroacetylacetonate (Pt-HFA), platinum-acetylacetonate, platinum-tetrakis(trifluorophosphine) (Pt(PF 3 ) 4 ), cyclopentadienyl-platinum-trimethyl (CpPtMe 3 ), methylcyclopentadienyl-platinum-trimethyl ((MeCp)PtMe 3 ), or mixtures thereof.
  • Cp-Pt platinum-hexafluoroacetylacetonate
  • Pt(PF 3 ) 4 platinum-tetrakis(trifluorophosphine)
  • CpPtMe 3 platinum-tetrakis(trifluorophosphine)
  • CpPtMe 3 cyclopentadienyl-platinum-trimethyl
  • Formation of Ta 2 O 5 monolayers by ALD can be performed using a precursor pair of tantalum tetraethoxide dimethylaminoethoxide (TATDMAE) and an oxidizer such as H 2 O, O 3 , O 2 , N 2 O, NO, isopropyl alcohol (IPA), mixtures thereof, and other oxidizers known to those skilled in the art.
  • TATDMAE tantalum tetraethoxide dimethylaminoethoxide
  • IPA isopropyl alcohol
  • the oxidizer may be pulsed for a time similar to TATDMAE, followed by another purge to complete one cycle and to form one monolayer having a typical depth of about 1 Angstrom. Completion of five cycles can thus form 5 monolayers.
  • Formation of Ta 2 O 5 monolayers by ALD can be performed in a similar manner alternatively using TATDMAE, TaCl 5 , TaF 5 , tantalum pentaethoxide (TAETO), or mixtures thereof.
  • an apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer on the interface layer.
  • the interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.
  • the second layer can contain the second chemical element. Examples of material types and compositions for the first layer, interface layer, and second layer are described above.
  • an electronic device can include a first layer containing a first chemical element, a second layer containing a second chemical element different from the first chemical element, and an interface layer between and in contact with the first and second layers.
  • the interface layer can contain first and second chemical elements and not substantially contain material originating from the first or second layers.
  • the interface layer contains at least one monolayer of intermixed first and second chemical elements chemisorbed on the first layer.
  • An interface layer still does not substantially comprise material originating from the first or second layers when contaminants or trace elements of the first or second layers diffuse into the interface layer.
  • an electronic device in a further aspect of the invention, includes a first layer containing a first chemical element, a first portion of at least one monolayer chemisorbed on the first layer, a second portion of the at least one monolayer chemisorbed on the first layer, an interface layer comprising the first and second portions of the at least one monolayer, and a second layer on the interface layer.
  • the first portion can contain the first chemical element and the second portion can contain a second chemical element different from the first chemical element.
  • the second layer can also contain the second chemical element.
  • the first portion of the at least one monolayer is chemisorbed on first parts of the first layer and the second portion of the at least one monolayer is chemisorbed on second parts of the first layer.
  • the at least one monolayer can include from about 1 to about 10 monolayers.

Abstract

An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. A second layer comprising the second chemical element can be formed on the interface layer. The first layer might not substantially contain the second chemical element, the second layer might not substantially contain the first chemical element, or both. An apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer containing a second element on the interface layer. The interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.

Description

This patent resulted from a divisional application of Ser. No. 09/825,087 U.S. Pat. No. 6,908,639, filed Apr. 2, 2001.
TECHNICAL FIELD
The present invention relates to chemisorbed interface layers of mixed composition and methods of forming interfaces, including interface layers in electronic devices and methods of formation.
BACKGROUND OF THE INVENTION
The need for better performing electronic devices, such as semiconductor devices, is increasing and a wider variety of materials are becoming candidates for incorporation into such devices. Although such materials may provide the necessary physical characteristics desired of a semiconductor, conductor, insulator, etc., incompatibilities can arise wherein materials do not adhere well together, creating defects in finished products. Surface defects, vacancies, misalignments, etc. can adversely impact adherence of one layer to another and can impact the interface there between. Accordingly, improvements in adherence of layers and interfaces would provide significant advantages in reducing product defects.
SUMMARY OF THE INVENTION
According to one aspect of the invention, an interface forming method can include forming a first layer comprising a first chemical element and chemisorbing on the first layer an interface layer including the first chemical element intermixed with a second chemical element different from the first chemical element. The interface layer can include at least one monolayer. A second layer is formed on the interface layer and can contain the second chemical element. As an example, the first layer might not contain the second chemical element. Similarly, the second layer might not contain the first chemical element. The first layer can be conductive and the second layer can be insulative. As a further example, the first layer can include a metal other than Ta, such as Pt, and the second layer can include Ta2O5.
In another aspect of the invention an electronic device interface forming method includes forming a first layer containing a first chemical element and chemisorbing a first portion of at least one monolayer over the first layer, the first portion including the first chemical element. A second portion of the at least one monolayer can be chemisorbed over the first layer and include a second chemical element different from the first chemical element. The first and second portions of the at least one monolayer can be contained in an interface layer. A second layer can be formed on the interface layer and contain the second chemical element. As an example, the first portion of the at least one monolayer can be chemisorbed on first parts of the first layer and the second portion of the at least one monolayer can be chemisorbed on second parts of the first layer.
As yet another aspect of the invention, an electronic device interface forming method can include forming a first device layer containing a first chemical element and chemisorbing a first unsaturated interface layer including the first chemical element on the first device layer. The first interface layer can have a thickness of about 1 to about 10 monolayers. A second unsaturated interface layer may be chemisorbed at least on the first device layer in areas not saturated by the first interface layer. The second interface layer can contain a second chemical element. A second device layer containing a second chemical element can be formed on the first and second interface layers.
An apparatus according to one aspect of the invention can include a first layer containing a first chemical element and an interface layer chemisorbed on the first layer. The interface layer can contain a first chemical element intermixed with a second chemical element different from the first chemical element. The apparatus can further include a second layer on the interface layer containing a second chemical element.
In another aspect of the invention an electronic device includes a first layer containing a first chemical element, a first portion of at least one monolayer chemisorbed on the first layer, a second portion of the at least one monolayer chemisorbed on the first layer, an interface layer comprising the first and second portions of the at least one monolayer, and a second layer on the interface layer. The first portion can contain the first chemical element and the second portion can contain a second chemical element different from the first chemical element. The second layer can contain the second chemical element.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
FIG. 1 shows a sectional view of a substrate portion at a processing step according to an aspect of the invention.
FIG. 2 shows a sectional view of a substrate portion at a processing step subsequent to that shown in FIG. 1.
FIG. 3 shows a sectional view of a substrate portion at a processing step subsequent to that shown in FIG. 2.
FIG. 4 shows a sectional view of a substrate portion at a processing step subsequent to that shown in FIG. 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
The methods and apparatuses of the aspects of the invention described herein are applicable to a variety of technologies. One example of an apparatus is an electronic device. Similarly, one example of an interface forming method is an electronic device interface forming method. However, the aspects of the invention are not limited to such devices or interface forming methods. The steps of the methods described herein may be accomplished by a variety of methods as well. For example, atomic layer deposition (ALD) can be a suitable technique for accomplishing the steps of the methods described herein.
ALD involves formation of successive atomic layers on a substrate. Such layers may comprise an epitaxial, polycrystalline, amorphous, etc. material. ALD may also be referred to as atomic layer epitaxy, atomic layer processing, etc. Further, the invention may encompass other deposition methods not traditionally referred to as ALD, for example, chemical vapor deposition (CVD), but nevertheless including the method steps described herein. The deposition methods herein may be described in the context of formation on a semiconductor wafer. However, the invention encompasses deposition on a variety of substrates besides semiconductor substrates.
In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Described in summary, ALD includes exposing an initial substrate to a first chemical species to accomplish chemisorption of the species onto the substrate. Theoretically, the chemisorption forms a monolayer that is uniformly one atom or molecule thick on the entire exposed initial substrate. In other words, a saturated monolayer. Practically, as further described below, chemisorption might not occur on all portions of the substrate. Nevertheless, such an imperfect monolayer is still a monolayer in the context of this document.
The first species is purged from over the substrate and a second chemical species is provided to chemisorb onto the first monolayer of the first species. The second species is then purged and the steps are repeated with exposure of the second species monolayer to the first species. In some cases, the two monolayers may be of the same species. Also, a third species or more may be successively chemisorbed and purged just as described for the first and second species.
Purging may involve a variety of techniques including, but not limited to, contacting the substrate and/or monolayer with a carrier gas and/or lowering pressure to below the deposition pressure to reduce the concentration of a species contacting the substrate and/or chemisorbed species. Examples of carrier gases include N2, Ar, He, Ne, Kr, Xe, etc. Purging may instead include contacting the substrate and/or monolayer with any substance that allows chemisorption byproducts to desorb and reduces the concentration of a contacting species preparatory to introducing another species. A suitable amount of purging can be determined experimentally as known to those skilled in the art. Purging time may be successively reduced to a purge time that yields an increase in film growth rate. The increase in film growth rate might be an indication of a change to a non-ALD process regime and may be used to establish a purge time limit.
ALD is often described as a self-limiting process, in that a finite number of sites exist on a substrate to which the first species may form chemical bonds. The second species might only bond to the first species and thus may also be self-limiting. Once all of the finite number of sites on a substrate are bonded with a first species, the first species will often not bond to other of the first species already bonded with the substrate. However, process conditions can be varied in ALD to promote such bonding and render ALD not self-limiting. Accordingly, ALD may also encompass a species forming other than one monolayer at a time by stacking of a species, forming a layer more than one atom or molecule thick. The various aspects of the present invention described herein are applicable to any circumstance where ALD may be desired.
Often, traditional ALD occurs within an often-used range of temperature and pressure and according to established purging criteria to achieve the desired formation of an overall ALD layer one monolayer at a time. Even so, ALD conditions can vary greatly depending on the particular precursors, layer composition, deposition equipment, and other factors according to criteria known by those skilled in the art. Maintaining the traditional conditions of temperature, pressure, and purging minimizes unwanted reactions that may impact monolayer formation and quality of the resulting overall ALD layer. Accordingly, operating outside the traditional temperature and pressure ranges may risk formation of defective monolayers.
The general technology of chemical vapor deposition (CVD) includes a variety of more specific processes, including, but not limited to, plasma enhanced CVD and others. CVD is commonly used to form non-selectively a complete, deposited material on a substrate. One characteristic of CVD is the simultaneous presence of multiple species in the deposition chamber that react to form the deposited material. Such condition is contrasted with the purging criteria for traditional ALD wherein a substrate is contacted with a single deposition species that chemisorbs to a substrate or previously deposited species. An ALD process regime may provide a simultaneously contacted plurality of species of a type or under conditions such that ALD chemisorption, rather than CVD reaction occurs. Instead of reacting together, the species may chemisorb to a substrate or previously deposited species, providing a surface onto which subsequent species may next chemisorb to form a complete layer of desired material.
Under most CVD conditions, deposition occurs largely independent of the composition or surface properties of an underlying substrate. By contrast, chemisorption rate in ALD might be influenced by the composition, crystalline structure, and other properties of a substrate or chemisorbed species. Other process conditions, for example, pressure and temperature, may also influence chemisorption rate. Accordingly, observation indicates that chemisorption might not occur appreciably on portions of a substrate though it occurs at a suitable rate on other portions of the same substrate.
According to one aspect of the invention, an interface forming method may include forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. The method can further include forming a second layer containing the second chemical element on the interface layer. The first and second layers can be formed by any method. Since the interface layer:contains the first chemical element, the interface layer can adhere well to the first layer. Also, since the interface layer contains the second chemical element, the interface layer also can adhere well to the second layer. Accordingly, the interface layer potentially can improve adherence of the second layer over the first layer.
The above described method can be particularly advantageous when the second layer might not adhere well to the first layer. For example, the first and second layer might not adhere well when the first layer does not substantially contain the second chemical element, the second layer does not substantially contain the first chemical element, or both. Observation indicates that such circumstance can arise, for example, when the first layer is conductive and the second layer is insulative, or vice versa. The method may be particularly useful when the first layer contains a metal other than Ta and the second layer contains Ta2O5. By way of example, the metal other than Ta can be Pt.
An exemplary metal-insulator-metal capacitor stack can include, respectively, Pt, Ta2O5, and Pt. The interfacial properties in the stack can influence current leakage and other performance characteristics of the capacitor. Also, suitable adhesion of the stack layers maintains integrity of the device. In keeping with the various aspects of the invention described herein, an interface layer can be formed between the Pt and Ta2O5 that includes intermixed Pt and Ta2O5 formed by ALD. Such a concept can also be used to enhance adhesion of other materials, for example, adhesion of Pt and Ru to oxide containing surfaces, such as barium strontium titanate, lead zirconate titanate, Ta2O5, etc.
In another aspect of the invention, an electronic device interface forming method includes forming an interface layer between and in contact with a first layer containing a first chemical element and a second layer containing a second chemical element different from the first chemical element. The interface layer can be formed separately from forming the first and second layers and contain the first and second chemical elements. The interface layer can also be formed such that it does not substantially contain material from the first or second layers as separately formed. Preferably, the interface layer contains at least one monolayer of intermixed first and second chemical elements chemisorbed on the first layer.
The interface layer is described as not substantially containing material from the first or second layers to indicate that the method used to form the interface layer adds material to a surface of the preexisting first or second layer without reliance on material therein to form part of the composition of the interface layer. It is recognized that after formation of the interface layer, insignificant amounts of material from the first or second layers can potentially diffuse into the interface layer. However, such diffusion still allows formation of an interface layer not substantially containing material from the first or second layers. Surface nitridation or surface oxidation as known to those skilled in the art are examples of methods that rely on existing materials to form part of a composition in a subsequently formed layer.
Similarly, when the first layer does not substantially contain the second chemical element or the second layer does not substantially contain the first chemical element such a circumstance refers to the primary composition of the first or second layer excluding contaminants, trace elements, and diffused material from surrounding structures. Understandably, contaminants, trace elements, and diffused materials can potentially insignificantly alter the composition of the first or second layers in a manufacturing process without causing such layers to substantially contain the first or second chemical elements.
Accordingly, a still further aspect of the invention provides an electronic device interface forming method that includes forming a first layer containing a first chemical element, chemisorbing a first portion of at least one monolayer over the first layer, and chemisorbing a second portion of the at least one monolayer over the first layer. The first portion of the at least one monolayer can contain the first chemical element. The second portion of the at least one monolayer can contain a second chemical element different from the first chemical element. The first and second portions of the at least one monolayer can form part of an interface layer. The method can further include forming a second layer containing a second chemical element on the interface layer. Preferably, the first portion of the at least one monolayer can be chemisorbed on first parts of the first layer and the second portion of the at least one monolayer can be chemisorbed on second parts of the first layer.
In a still further aspect of the invention, an electronic device interface forming method includes forming a first device layer containing a first chemical element, chemisorbing a first unsaturated interface layer containing the first chemical element on the first device layer, and chemisorbing a second unsaturated interface layer at least on the first device layer in areas not saturated by the first interface layer. The first interface layer can have a thickness of from about 1 to about 10 monolayers. The second interface layer can have a thickness of from about 1 to about 10 monolayers and contain a second chemical element different from the first chemical element. The method can further include forming a second device layer containing the second chemical element on the first and second interface layers. One example of a first device layer can be a capacitor plate while a second device layer can be a capacitor dielectric. Similarly, the first device layer can be a capacitor dielectric while the second device layer is a capacitor plate.
Turning to FIG. 1, a substrate 2 is shown with a first layer 4 formed thereon. In FIG. 2, a first material 6 is formed on parts of first layer 4 but not on other parts of first layer 4, namely unsaturated areas 14. The first material 6 is shown in FIG. 2 as a graphical representation of individual molecules or atoms chemisorbed to the surface of first layer 4. In FIG. 3, a second material 8 is shown in graphical representation chemisorbed in formerly unsaturated areas 14 on first layer 4. The monolayer of first material 6 and monolayer of second material 8 formed in unsaturated areas 14 thus form an interface layer 10. Interface layer 10 can have a thickness of from about 1 to about 10 monolayers, or a greater thickness depending on a particular application. FIG. 4 shows a second layer 12 formed on interface layer 10 with interface layer 10 shown as a material layer, rather than a graphical representation of chemisorbed molecules or atoms.
Although the preferred method described above in relation to FIGS. 1-4 includes separate formation of first material 6 and second material 8 on first layer 4, the layers of first and second materials 6, 8 could conceivably be formed simultaneously. Thus, the structure of FIG. 3 can be obtained by forming both first and second materials 6, 8 on first layer 4 of FIG. 1 simultaneously rather than as shown in FIG. 2.
An advantage of using ALD to form first and second materials 6, 8 is that desired properties of interface layer 10 can be controlled at the atomic level. Interfacial properties such as dead layers, surface defects, vacancies, and impurities, as known to those skilled in the art can be improved with selection of suitable components for the interface layer and ALD processing conditions. For example, saturation of the surface of first layer 4 with intermixed first and second materials 6, 8 can reduce vacancies at the interface between first layer 4 and second layer 12. Further, selection of elements exhibiting suitable atomic diameters for interface layer 10 can improve the packing density of the interface between first layer 4 and second layer 12. The reduction in defects at the interface can provide a better functioning device. It is an additional advantage that an interface layer formed according to the various aspects of the invention described above can improve adhesion between first layer 4 and second layer 12. Existing knowledge of those skilled in the art regarding adhesion between particular materials can be used to select a compositional ratio of first material 6 to second material 8 in interface layer 10. Similarly, such information can be used to select potentially different compositional ratios for each monolayer formed as part of an interface layer.
For example, interface layer 10 can have a fixed composition among monolayers. A ratio of first material 6 to second material 8 may be selected and then processing structured to produce the fixed composition. For an interface layer between Ta2O5 and Pt, about 5 monolayers of Pt can be chemisorbed on the Ta2O5 followed by about 5 monolayers of Ta2O5. Additional alternating Pt and Ta2O5 material can be added in about equal numbers of monolayers to a desired interface layer depth. The resulting interface layer can exhibit about a 1:1 ratio of Pt to Ta2O5.
As another example, interface layer 10 can have a composition gradient among monolayers. A beginning ratio of first material 6 to second material 8 may be initially selected and then altered as successive monolayers are added to form interface layer 10. A ratio proximate an inner surface of interface layer 10 can thus be different from a ratio proximate an outer surface of interface layer 10. For an interface layer between Ta2O5 and Pt, about 5 monolayers of Pt can be chemisorbed on the Ta2O5 followed by about 5 monolayers of Ta2O5. Additional alternating Pt and Ta2O5 material can be added with one further monolayer of Pt included in each turn. Accordingly, 6 Pt monolayers could chemisorbed, then 7 Pt monolayers, 8 Pt monolayers, and so on, each time followed by chemisorption of 5 Ta2O5 monolayers or less. As an alternative, the number of Ta2O5 monolayers could be decreased while holding the number of Pt monolayers constant. In either case, the ratio of Pt to Ta2O5 can increase as the interface layer depth increases to the point where a Pt layer is formed on the interface layer.
Formation of Pt monolayers by ALD can be performed using a precursor pair of a cyclopentadienyl-platinum (Cp-Pt) complex and an oxidizer such as H2O, O3, O2, N2O, NO, isopropyl alcohol (IPA), mixtures thereof, and other oxidizers known to those skilled in the art. At a temperature of about 175 to about 275° C. and a pressure of about 10 milliTorr to about 10 Torr, Cp-Pt may be pulsed over a substrate for about 0.3 to about 3 seconds. After purging for about 0.5 to about 10 seconds, the oxidizer may be pulsed for a time similar to Cp-Pt, followed by another purge to complete one cycle and to form one monolayer having a typical depth of about 1 Angstrom. Completion of five cycles can thus form 5 monolayers.
Formation of Pt monolayers by ALD can be performed in a similar manner alternatively using Cp-Pt, platinum-hexafluoroacetylacetonate (Pt-HFA), platinum-acetylacetonate, platinum-tetrakis(trifluorophosphine) (Pt(PF3)4), cyclopentadienyl-platinum-trimethyl (CpPtMe3), methylcyclopentadienyl-platinum-trimethyl ((MeCp)PtMe3), or mixtures thereof.
Formation of Ta2O5 monolayers by ALD can be performed using a precursor pair of tantalum tetraethoxide dimethylaminoethoxide (TATDMAE) and an oxidizer such as H2O, O3, O2, N2O, NO, isopropyl alcohol (IPA), mixtures thereof, and other oxidizers known to those skilled in the art. At a temperature of about 200 to about 500° C. and a pressure of about 10 milliTorr to about 10 Torr, TATDMAE may be pulsed over a substrate for about 0.3 to about 3 seconds. After purging for about 0.5 to about 10 seconds, the oxidizer may be pulsed for a time similar to TATDMAE, followed by another purge to complete one cycle and to form one monolayer having a typical depth of about 1 Angstrom. Completion of five cycles can thus form 5 monolayers.
Formation of Ta2O5 monolayers by ALD can be performed in a similar manner alternatively using TATDMAE, TaCl5, TaF5, tantalum pentaethoxide (TAETO), or mixtures thereof.
The present aspects of the invention include apparatuses as well as, the methods described above. In one aspect, an apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer on the interface layer. The interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. The second layer can contain the second chemical element. Examples of material types and compositions for the first layer, interface layer, and second layer are described above.
In another aspect, an electronic device can include a first layer containing a first chemical element, a second layer containing a second chemical element different from the first chemical element, and an interface layer between and in contact with the first and second layers. The interface layer can contain first and second chemical elements and not substantially contain material originating from the first or second layers. Preferably, the interface layer contains at least one monolayer of intermixed first and second chemical elements chemisorbed on the first layer. An interface layer still does not substantially comprise material originating from the first or second layers when contaminants or trace elements of the first or second layers diffuse into the interface layer.
In a further aspect of the invention, an electronic device includes a first layer containing a first chemical element, a first portion of at least one monolayer chemisorbed on the first layer, a second portion of the at least one monolayer chemisorbed on the first layer, an interface layer comprising the first and second portions of the at least one monolayer, and a second layer on the interface layer. The first portion can contain the first chemical element and the second portion can contain a second chemical element different from the first chemical element. The second layer can also contain the second chemical element. Preferably, the first portion of the at least one monolayer is chemisorbed on first parts of the first layer and the second portion of the at least one monolayer is chemisorbed on second parts of the first layer. The at least one monolayer can include from about 1 to about 10 monolayers.
The apparatuses and electronic devices described above can exhibit similar advantages to those indicated in relation to the interface forming methods of the present invention.
In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (45)

1. A capacitor comprising:
a first capacitor plate over a semiconductive substrate, the first plate comprising a first metal selected from the group consisting of Pt and Ru;
an interface layer chemisorbed on and in contact with the first plate, the interface layer comprising at least one monolayer of the first metal intermixed with a second metal selected from the group consisting of Ba, Sr, Ti, Pb, Zr, and Ta;
a capacitor dielectric layer comprising the second metal on and in contact with the interface layer, the interface layer improving adhesion between the first plate and the dielectric layer compared to adhesion otherwise occurring with the dielectric layer formed on and in contact with the first plate in the absence of the interface layer; and
a second capacitor plate over the dielectric layer.
2. The article of claim 1 wherein the dielectric layer does not substantially comprise the first metal.
3. The article of claim 1 wherein the first plate consists of Pt or Ru.
4. The article of claim 1 wherein the interface layer provides a composition gradient across a thickness of the interface layer from the first plate to the dielectric layer.
5. The capacitor of claim 1 wherein the interface layer does not substantially comprise material originating from the first plate or the dielectric layer.
6. The capacitor of claim 1 wherein the interface layer reduces defects between the first plate and the dielectric layer compared to defects otherwise occurring with the dielectric layer formed on and in contact with the first plate in the absence of the interface layer.
7. The article of claim 1 wherein the first plate does not substantially comprise the second metal.
8. The article of claim 7 wherein the dielectric layer does not substantially comprise the first metal.
9. The article of claim 1 wherein the dielectric layer consists of barium strontium titanate, lead zirconate titanate, or Ta2O5.
10. The article of claim 9 wherein the metal comprises Pt.
11. An electronic device comprising:
a capacitor plate with a conductive first layer comprising a first chemical element;
a capacitor dielectric with an insulative second layer comprising a second chemical element different from the first chemical element; and
an interface layer between and in contact with the first and second layers, the interface layer comprising the first and second chemical elements, not substantially comprising material originating from the first or second layers, and providing a composition gradient across a thickness of the interface layer such that a first ratio of the first chemical element to the second chemical element in the interface layer proximate the first layer is greater than a second ratio of the first chemical element to the second chemical element in the interface layer proximate the second layer.
12. The device of claim 11 wherein the second layer does not substantially comprise the first chemical element.
13. The electronic device of claim 11 further comprising a semiconductor substrate, the first layer being over the substrate.
14. The capacitor of claim 11 wherein the interface layer reduces defects between the first layer and the second layer compared to defects otherwise occurring with the second layer formed on and in contact with the first layer in the absence of the interface layer.
15. The capacitor of claim 11 wherein the interface layer improves adhesion between the first layer and the second layer compared to adhesion otherwise occurring with the second layer formed on and in contact with the first layer in the absence of the interface layer.
16. The device of claim 11 wherein the first layer does not substantially comprise the second chemical element.
17. The device of claim 16 wherein the second layer does not substantially comprise the first chemical element.
18. An electronic device comprising:
a capacitor plate with a conductive first layer comprising a first chemical element;
a capacitor dielectric with an insulative second layer comprising a second chemical element different from the first chemical element; and
an interface layer between and in contact with the first and second layers, the interface layer comprising the first and second chemical elements, not substantially comprising material originating from the first or second layers, providing a composition gradient across a thickness of the interface layer, and comprising at least one monolayer of intermixed first and second chemical elements chemisorbed on the first layer.
19. The capacitor of claim 18 wherein the interface layer reduces defects between the first layer and the second layer compared to defects otherwise occurring with the second layer formed on and in contact with the first layer in the absence of the interface layer.
20. The capacitor of claim 18 wherein the interface layer improves adhesion between the first layer and the second layer compared to adhesion otherwise occurring with the second layer formed on and in contact with the first layer in the absence of the interface layer.
21. A capacitor comprising:
a first capacitor plate comprising a first chemical element;
a first portion of at least one monolayer chemisorbed on the first plate, the first portion comprising the first chemical element;
a second portion of the at least one monolayer chemisorbed on the first plate, the second portion comprising a second chemical element different from the first chemical element;
an interface layer comprising the first and second portions of the at least one monolayer;
a dielectric layer comprising the second chemical element on the interface layer; and
a second capacitor plate over the dielectric layer.
22. The device of claim 21 wherein the dielectric layer does not substantially comprise the first chemical element.
23. The device of claim 21 wherein the first portion of the at least one monolayer is chemisorbed on first parts of the first plate and the second portion of the at least one monolayer is chemisorbed on second parts of the first plate.
24. The device of claim 21 wherein the at least one monolayer comprises from about 1 to about 10 monolayers.
25. The electronic device of claim 21 further comprising a semiconductor substrate, the first layer being over the substrate.
26. The capacitor of claim 21 wherein the interface layer does not substantially comprise material originating from the first plate or the dielectric layer.
27. The capacitor of claim 21 wherein the interface layer reduces defects between the first plate and the dielectric layer compared to defects otherwise occurring with the dielectric layer formed on and in contact with the first plate in the absence of the interface layer.
28. The capacitor of claim 21 wherein the interface layer improves adhesion between the first plate and the dielectric layer compared to adhesion otherwise occurring with the dielectric layer formed on and in contact with the first plate in the absence of the interface layer.
29. The device of claim 21 wherein the first plate does not substantially comprise the second chemical element.
30. The device of claim 29 wherein the dielectric layer does not substantially comprise the first chemical element.
31. An electronic device comprising:
a conductive first layer comprising a metal containing Pt and/or Ru;
an insulative second layer comprising Ta; and
an interface layer between and in contact with the first and second layers, the interface layer comprising the metal and Ta, not substantially comprising material originating from the first or second layers, and providing a composition gradient across a thickness of the interface layer such that a first ratio of the metal to Ta in the interface layer proximate the first layer is greater than a second ratio of the metal to Ta in the interface layer proximate the second layer.
32. The capacitor of claim 31 wherein the interface layer reduces defects between the first layer and the second layer compared to defects otherwise occurring with the second layer formed on and in contact with the first layer in the absence of the interface layer.
33. The capacitor of claim 31 wherein the interface layer improves adhesion between the first layer and the second layer compared to adhesion otherwise occurring with the second layer formed on and in contact with the first layer in the absence of the interface layer.
34. A capacitor comprising:
a first conductive plate over a semiconductor substrate, the first plate comprising a first metal;
an interface layer in contact with the first plate, the interface layer comprising at least one monolayer of the first metal intermixed with a second metal which is different from the first metal;
a dielectric layer comprising the second metal on and in contact with the interface layer, the interface layer being disposed between the first plate and the dielectric layer such that the interface layer adheres to both the dielectric layer and the first plate; and
a second conductive plate over the dielectric layer.
35. A capacitor comprising:
a first conductive layer comprising a first chemical element;
a first portion of at least one monolayer on the first conductive layer, the first portion comprising the first chemical element;
a second portion of the at least one monolayer on the first conductive layer, the second portion comprising a second chemical element different from the first chemical element;
an interface layer comprising the first and second portions of the at least one monolayer;
a dielectric layer comprising the second chemical element on the interface layer; and
a second conductive layer over the dielectric layer.
36. An electronic device comprising:
a conductive first layer comprising a first chemical element;
a dielectric second layer comprising a second chemical element different from the first chemical element; and
an interface layer between and in contact with the first and second layers, the interface layer comprising the first and second chemical elements, and providing a composition gradient across a thickness of the interface layer such that a first ratio of the first chemical element to the second chemical element in the interface layer proximate the first layer is greater than a second ratio of the first chemical element to the second chemical element in the interface layer proximate the second layer.
37. The capacitor of claim 34 wherein the first metal is selected from the group consisting of Ru, Ta, and Pt.
38. The capacitor of claim 34 wherein the dielectric layer comprises at least one of: barium strontium titanate, lead zirconate titanate, and tantalum oxide.
39. The capacitor of claim 34 wherein the second metal comprises at least one of: Ba, Sr, Ti, Pb, Zr, and Ta.
40. The capacitor of claim 35 wherein the first chemical element is selected from the group consisting of Ru, Ta, and Pt.
41. The capacitor of claim 35 wherein the dielectric layer comprises at least one of: barium strontium titanate, lead zirconate titanate, and tantalum oxide.
42. The capacitor of claim 35 wherein the second chemical element comprises at least one of: Ba, Sr, Ti, Pb, Zr, and Ta.
43. The electronic device of claim 36 wherein the first chemical element is selected from the group consisting of Ru, Ta, and Pt.
44. The electronic device of claim 36 wherein the dielectric second layer comprises at least one of: barium strontium titanate, lead zirconate titanate, and tantalum oxide.
45. The capacitor of claim 36 wherein the second chemical element comprises at least one of: Ba, Sr, Ti, Pb, Zr, and Ta.
US12/566,533 2001-04-02 2009-09-24 Mixed composition interface layer and method of forming Expired - Lifetime USRE43025E1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/566,533 USRE43025E1 (en) 2001-04-02 2009-09-24 Mixed composition interface layer and method of forming
US13/293,778 US20120120549A1 (en) 2001-04-02 2011-11-10 Mixed Composition Interface Layer and Method of Forming

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/825,087 US6908639B2 (en) 2001-04-02 2001-04-02 Mixed composition interface layer and method of forming
US10/228,404 US7273660B2 (en) 2001-04-02 2002-08-26 Mixed composition interface layer and method of forming
US12/566,533 USRE43025E1 (en) 2001-04-02 2009-09-24 Mixed composition interface layer and method of forming

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US10/228,404 Reissue US7273660B2 (en) 2001-04-02 2002-08-26 Mixed composition interface layer and method of forming
US10/228,404 Continuation US7273660B2 (en) 2001-04-02 2002-08-26 Mixed composition interface layer and method of forming

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/293,778 Continuation US20120120549A1 (en) 2001-04-02 2011-11-10 Mixed Composition Interface Layer and Method of Forming

Publications (1)

Publication Number Publication Date
USRE43025E1 true USRE43025E1 (en) 2011-12-13

Family

ID=25243080

Family Applications (4)

Application Number Title Priority Date Filing Date
US09/825,087 Expired - Fee Related US6908639B2 (en) 2001-04-02 2001-04-02 Mixed composition interface layer and method of forming
US10/228,404 Ceased US7273660B2 (en) 2001-04-02 2002-08-26 Mixed composition interface layer and method of forming
US12/566,533 Expired - Lifetime USRE43025E1 (en) 2001-04-02 2009-09-24 Mixed composition interface layer and method of forming
US13/293,778 Abandoned US20120120549A1 (en) 2001-04-02 2011-11-10 Mixed Composition Interface Layer and Method of Forming

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US09/825,087 Expired - Fee Related US6908639B2 (en) 2001-04-02 2001-04-02 Mixed composition interface layer and method of forming
US10/228,404 Ceased US7273660B2 (en) 2001-04-02 2002-08-26 Mixed composition interface layer and method of forming

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/293,778 Abandoned US20120120549A1 (en) 2001-04-02 2011-11-10 Mixed Composition Interface Layer and Method of Forming

Country Status (1)

Country Link
US (4) US6908639B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140166956A1 (en) * 2012-12-13 2014-06-19 Intermolecular Inc. Using saturated and unsaturated ALD processes to deposit oxides as ReRAM switching layer

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060219157A1 (en) * 2001-06-28 2006-10-05 Antti Rahtu Oxide films containing titanium
US6943392B2 (en) * 1999-08-30 2005-09-13 Micron Technology, Inc. Capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen
US6558517B2 (en) * 2000-05-26 2003-05-06 Micron Technology, Inc. Physical vapor deposition methods
US20030017266A1 (en) * 2001-07-13 2003-01-23 Cem Basceri Chemical vapor deposition methods of forming barium strontium titanate comprising dielectric layers, including such layers having a varied concentration of barium and strontium within the layer
US6838122B2 (en) * 2001-07-13 2005-01-04 Micron Technology, Inc. Chemical vapor deposition methods of forming barium strontium titanate comprising dielectric layers
US7011978B2 (en) * 2001-08-17 2006-03-14 Micron Technology, Inc. Methods of forming capacitor constructions comprising perovskite-type dielectric materials with different amount of crystallinity regions
KR100427030B1 (en) * 2001-08-27 2004-04-14 주식회사 하이닉스반도체 Method for forming film with muli-elements and fabricating capacitor using the same
US7517751B2 (en) * 2001-12-18 2009-04-14 Tokyo Electron Limited Substrate treating method
KR100474072B1 (en) * 2002-09-17 2005-03-10 주식회사 하이닉스반도체 Method for forming noble metal films
JP4009550B2 (en) * 2003-03-27 2007-11-14 エルピーダメモリ株式会社 Method for forming metal oxide film
US7482037B2 (en) * 2004-08-20 2009-01-27 Micron Technology, Inc. Methods for forming niobium and/or vanadium containing layers using atomic layer deposition
US8025922B2 (en) * 2005-03-15 2011-09-27 Asm International N.V. Enhanced deposition of noble metals
US7582549B2 (en) 2006-08-25 2009-09-01 Micron Technology, Inc. Atomic layer deposited barium strontium titanium oxide films
US8092721B2 (en) * 2008-03-26 2012-01-10 L'air Liquide Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude Deposition of ternary oxide films containing ruthenium and alkali earth metals
US8383525B2 (en) 2008-04-25 2013-02-26 Asm America, Inc. Plasma-enhanced deposition process for forming a metal oxide thin film and related structures
JP5384291B2 (en) 2008-11-26 2014-01-08 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing method, and substrate processing apparatus
WO2011106072A2 (en) 2010-02-23 2011-09-01 L'air Liquide Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude Use of ruthenium tetroxide as a precursor and reactant for thin film depositions
US20110293830A1 (en) 2010-02-25 2011-12-01 Timo Hatanpaa Precursors and methods for atomic layer deposition of transition metal oxides
US9062390B2 (en) 2011-09-12 2015-06-23 Asm International N.V. Crystalline strontium titanate and methods of forming the same
CN106569624B (en) * 2015-10-09 2020-09-29 群创光电股份有限公司 Touch substrate and touch device

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058430A (en) 1974-11-29 1977-11-15 Tuomo Suntola Method for producing compound thin films
US4109031A (en) 1976-12-27 1978-08-22 United Technologies Corporation Stress relief of metal-ceramic gas turbine seals
US4228212A (en) * 1979-06-11 1980-10-14 General Electric Company Composite conductive structures in integrated circuits
US5879459A (en) 1997-08-29 1999-03-09 Genus, Inc. Vertically-stacked process reactor and cluster tool system for atomic layer deposition
US6015989A (en) 1996-06-28 2000-01-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a capacitor electrode formed of iridum or ruthenium and a quantity of oxygen
US6111321A (en) * 1992-12-31 2000-08-29 International Business Machines Corporation Ball limiting metalization process for interconnection
US6241821B1 (en) 1999-03-22 2001-06-05 Motorola, Inc. Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
US20010041250A1 (en) * 2000-03-07 2001-11-15 Werkhoven Christian J. Graded thin films
US6407435B1 (en) * 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
US6428859B1 (en) * 2000-12-06 2002-08-06 Angstron Systems, Inc. Sequential method for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD)
US20020106536A1 (en) * 2001-02-02 2002-08-08 Jongho Lee Dielectric layer for semiconductor device and method of manufacturing the same
US20020110991A1 (en) 2001-02-13 2002-08-15 Micron Technology, Inc. Sequential pulse deposition
US6458416B1 (en) 2000-07-19 2002-10-01 Micron Technology, Inc. Deposition methods
US6465828B2 (en) * 1999-07-30 2002-10-15 Micron Technology, Inc. Semiconductor container structure with diffusion barrier
US6524868B2 (en) 2000-06-30 2003-02-25 Hyundai Electronics Industries Co., Ltd. Method for fabricating semiconductor memory device
US6570253B1 (en) * 1999-10-19 2003-05-27 Samsung Electronics Co., Ltd. Multi-layer film for a thin film structure and a capacitor using the same
US6576053B1 (en) * 1999-10-06 2003-06-10 Samsung Electronics Co., Ltd. Method of forming thin film using atomic layer deposition method
US6597029B2 (en) 2000-06-30 2003-07-22 Hynix Semiconductor Inc. Nonvolatile semiconductor memory device
US6818935B2 (en) 2001-09-12 2004-11-16 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4530322A (en) * 1980-10-31 1985-07-23 Nippon Kokan Kabushiki Kaisha Exhaust valve for diesel engine and production thereof
US4822312A (en) * 1983-12-05 1989-04-18 Gte Products Corporation Electrode for high intensity discharge lamps
US5100714A (en) * 1986-07-24 1992-03-31 Ceramic Packaging, Inc. Metallized ceramic substrate and method therefor
US5161728A (en) * 1988-11-29 1992-11-10 Li Chou H Ceramic-metal bonding
JP2924177B2 (en) * 1990-11-30 1999-07-26 株式会社村田製作所 Functionally graded circuit board
US5455000A (en) * 1994-07-01 1995-10-03 Massachusetts Institute Of Technology Method for preparation of a functionally gradient material
CA2232517C (en) * 1997-03-21 2004-02-17 Honda Giken Kogyo Kabushiki Kaisha .) Functionally gradient material and method for producing the same
GB9910842D0 (en) * 1999-05-10 1999-07-07 Univ Nanyang Composite coatings

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058430A (en) 1974-11-29 1977-11-15 Tuomo Suntola Method for producing compound thin films
US4109031A (en) 1976-12-27 1978-08-22 United Technologies Corporation Stress relief of metal-ceramic gas turbine seals
US4228212A (en) * 1979-06-11 1980-10-14 General Electric Company Composite conductive structures in integrated circuits
US6111321A (en) * 1992-12-31 2000-08-29 International Business Machines Corporation Ball limiting metalization process for interconnection
US6015989A (en) 1996-06-28 2000-01-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a capacitor electrode formed of iridum or ruthenium and a quantity of oxygen
US5879459A (en) 1997-08-29 1999-03-09 Genus, Inc. Vertically-stacked process reactor and cluster tool system for atomic layer deposition
US6241821B1 (en) 1999-03-22 2001-06-05 Motorola, Inc. Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
US6465828B2 (en) * 1999-07-30 2002-10-15 Micron Technology, Inc. Semiconductor container structure with diffusion barrier
US6576053B1 (en) * 1999-10-06 2003-06-10 Samsung Electronics Co., Ltd. Method of forming thin film using atomic layer deposition method
US6570253B1 (en) * 1999-10-19 2003-05-27 Samsung Electronics Co., Ltd. Multi-layer film for a thin film structure and a capacitor using the same
US6407435B1 (en) * 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
US20010041250A1 (en) * 2000-03-07 2001-11-15 Werkhoven Christian J. Graded thin films
US6534395B2 (en) 2000-03-07 2003-03-18 Asm Microchemistry Oy Method of forming graded thin films using alternating pulses of vapor phase reactants
US20030032281A1 (en) 2000-03-07 2003-02-13 Werkhoven Christiaan J. Graded thin films
US6524868B2 (en) 2000-06-30 2003-02-25 Hyundai Electronics Industries Co., Ltd. Method for fabricating semiconductor memory device
US6597029B2 (en) 2000-06-30 2003-07-22 Hynix Semiconductor Inc. Nonvolatile semiconductor memory device
US6458416B1 (en) 2000-07-19 2002-10-01 Micron Technology, Inc. Deposition methods
US6428859B1 (en) * 2000-12-06 2002-08-06 Angstron Systems, Inc. Sequential method for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD)
US20020106536A1 (en) * 2001-02-02 2002-08-08 Jongho Lee Dielectric layer for semiconductor device and method of manufacturing the same
US20020110991A1 (en) 2001-02-13 2002-08-15 Micron Technology, Inc. Sequential pulse deposition
US6818935B2 (en) 2001-09-12 2004-11-16 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Suntola, "Atomic Layer Epitaxy", Handbook of Crystal Growth, vol. 3, Chapter 14, pp. 602-663.
Suntola, "Surface Chemistry of Materials Deposition at Atomic Layer Level", Applied Surface Science, vol. 100/101, Mar. 1996, pp. 391-398.
Webster's II New Riverside University Dictionary, 1994, Riverside Publishing Company, p. 118. *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140166956A1 (en) * 2012-12-13 2014-06-19 Intermolecular Inc. Using saturated and unsaturated ALD processes to deposit oxides as ReRAM switching layer
US9040413B2 (en) * 2012-12-13 2015-05-26 Intermolecular, Inc. Using saturated and unsaturated ALD processes to deposit oxides as ReRAM switching layer

Also Published As

Publication number Publication date
US6908639B2 (en) 2005-06-21
US20020192509A1 (en) 2002-12-19
US20020142588A1 (en) 2002-10-03
US7273660B2 (en) 2007-09-25
US20120120549A1 (en) 2012-05-17

Similar Documents

Publication Publication Date Title
USRE43025E1 (en) Mixed composition interface layer and method of forming
US7160817B2 (en) Dielectric material forming methods
US6458416B1 (en) Deposition methods
US6420230B1 (en) Capacitor fabrication methods and capacitor constructions
US7109542B2 (en) Capacitor constructions having a conductive layer
US8481122B2 (en) Methods of forming material over substrates
US7112503B1 (en) Enhanced surface area capacitor fabrication methods
US8299462B2 (en) Constructions comprising hafnium oxide and/or zirconium oxide
US6468924B2 (en) Methods of forming thin films by atomic layer deposition
US7431966B2 (en) Atomic layer deposition method of depositing an oxide on a substrate
US6919243B2 (en) Methods of forming an integrated circuit capacitor in which a metal preprocessed layer is formed on an electrode thereof
US7468108B2 (en) Metal layer forming methods and capacitor electrode forming methods
US7365028B2 (en) Methods of forming metal oxide and semimetal oxide
KR100528799B1 (en) Method for forming a dielectric film and method for manufacturing a capacitor using the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:024612/0397

Effective date: 20090609

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: ROYAL BANK OF CANADA, CANADA

Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276 N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196

Effective date: 20111223

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASCERI, CEM;SANDHU, GURTEJ S.;REEL/FRAME:027539/0172

Effective date: 20010314

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,

Free format text: CHANGE OF NAME;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:032439/0638

Effective date: 20140101

AS Assignment

Owner name: CONVERSANT IP N.B. 868 INC., CANADA

Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344

Effective date: 20140611

Owner name: CONVERSANT IP N.B. 276 INC., CANADA

Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344

Effective date: 20140611

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,

Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344

Effective date: 20140611

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA

Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096

Effective date: 20140820

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,

Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096

Effective date: 20140820

AS Assignment

Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA

Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367

Effective date: 20140611

Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA

Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367

Effective date: 20140611

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: CPPIB CREDIT INVESTMENTS, INC., CANADA

Free format text: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:046900/0136

Effective date: 20180731

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA

Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424

Effective date: 20180731

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,

Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424

Effective date: 20180731

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CPPIB CREDIT INVESTMENTS INC.;REEL/FRAME:054387/0186

Effective date: 20201028

AS Assignment

Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA

Free format text: CHANGE OF NAME;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY INC.;REEL/FRAME:058297/0458

Effective date: 20210401

AS Assignment

Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED AT REEL: 058297 FRAME: 0458. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:064761/0349

Effective date: 20210401