USRE39211E1 - Method for manufacturing a liquid crystal display - Google Patents

Method for manufacturing a liquid crystal display Download PDF

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USRE39211E1
USRE39211E1 US10/613,064 US61306403A USRE39211E US RE39211 E1 USRE39211 E1 US RE39211E1 US 61306403 A US61306403 A US 61306403A US RE39211 E USRE39211 E US RE39211E
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film
metal film
pad
electrode
gate
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Young-chan Kweon
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Samsung Display Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Definitions

  • the present invention relates to a method for manufacturing a liquid crystal display. More particularly, the present invention relates to a method for manufacturing a liquid crystal display having a thin film transistor as an active device, by which it is possible to reduce the number of the photolithography processes.
  • the liquid crystal display is currently the most widely used flat-panel display device.
  • Other devices being developed and rapidly becoming popular include the plasma display panel (PDP), the electro luminescence (EL) device, the field emission display (FED), and the reflex deformable mirror device (DMD), which controls the movement of a mirror.
  • PDP plasma display panel
  • EL electro luminescence
  • FED field emission display
  • DMD reflex deformable mirror device
  • the LCD uses an optical characteristic of liquid crystal molecules in which the arrangement thereof changes according to an electrical field and a semiconductor technology which forms minute patterns.
  • a thin film transistor LCD (“TFT-LCD”), which uses the thin film transistor as the active device, has various advantages over other LCDs. These advantages include low power consumption, low drive voltage, a thinness, and lightness of weight, among others.
  • the process of manufacturing a TFT is complicated, resulting in low productivity and high manufacturing costs.
  • a mask is used in every step for manufacturing a TFT, at least seven masks are required. Therefore, various methods for increasing productivity of the TFT and lowering the manufacturing costs have been studied. In particular, a method for reducing the number of the masks used during the manufacturing process has been widely researched.
  • FIGS. 1 to 5 are sectional views for explaining a conventional method for manufacturing an LCD, as disclosed in U.S. Pat. No. 5,054,887.
  • reference characters “A” and “B” denote a TFT area and a pad area, respectively.
  • FIG. 1 after forming a first metal film by depositing pure Al on a transparent substrate 2 , gate patterns 4 and 4 a are formed out of the first metal film by performing a first photolithography on the first metal film. The gate patterns are then used as a gate electrode 4 in the TFT area and as a gate pad 4 a in the pad area.
  • an anodized film 6 is formed by oxidizing the first metal film using the photoresist pattern as an anti-oxidation film.
  • the anodized film 6 is then formed on the entire surface of the gate electrode 4 formed in the TFT area, and on a portion of the gate pad 4 a in the pad area.
  • an insulating film 8 is formed by depositing a layer such as a nitride film over the anodized film 6 .
  • a semiconductor film is then formed by subsequently depositing an amorphous silicon film 10 and an amorphous silicon film 12 doped with impurities on the entire surface of the substrate 2 on which the insulating film 8 is formed.
  • a semiconductor film pattern 10 and 12 to be used as an active portion is then formed in the TFT area by performing a third photolithography on the semiconductor film.
  • a fourth photoresist pattern (not shown) is then formed that exposes a portion of the gate pad 4 a formed in the pad area by performing a fourth photolithography on the entire surface of the substrate 2 on which the semiconductor film pattern is formed. Then, a contact hole is then formed in the insulating film 8 , which contact hole exposes a portion of the gate pad 4 a. The contact hole is formed by etching the insulating film 8 using the fourth photoresist pattern as a mask. A source electrode 14 a and a drain electrode 14 b are then formed in the TFT area by depositing a chromium (“Cr”) film on the entire surface of the substrate having the contact hole and performing a fifth photolithography on the Cr film.
  • Cr chromium
  • a pad electrode 14 c connected to the gate pad 4 a through the contact hole is formed.
  • the impurity doped-amorphous silicon film 12 on the upper portion of the gate electrode 4 formed in the TFT area during the photolithography process is partially etched, thus exposing a portion of the amorphous silicon film 10 .
  • a protection film 16 is then formed by depositing an oxide film over the entire surface of the substrate 2 on which the source electrode 14 a, the drain electrode 14 b and the pad electrode 14 c are formed. Then, contact holes are formed that expose a portion of the drain electrode 14 b of the TFT area and a portion of the pad electrode 14 c of the pad area. The contact holes are formed by performing a sixth photolithography on the protection film 16 .
  • pixel electrodes 18 and 18 a are formed by depositing indium tin oxide (“ITO”), a transparent conductive material, over the entire surface of the substrate, including the contact hole, and performing a seventh photolithography process on the resultant ITO film.
  • ITO indium tin oxide
  • the drain electrode 14 b and the pixel electrode 18 are connected in the TFT area
  • the pad electrode 14 c and the pixel electrode 18 a are connected in the pad area.
  • pure aluminum (“Al”) is used as the gate electrode material to lower the resistance of a gate line.
  • An anodizing process is therefore required to prevent a hillock caused by the Al. This additional anodizing step complicates the manufacturing process, reduces productivity, and increases manufacturing costs.
  • a method for manufacturing a liquid crystal display comprising the steps of forming a gate electrode and a gate pad by depositing a first metal film and a second metal film over a substrate in a TFT area and a gate-pad connecting area, respectively, by a first photolithography process; forming an insulating film over the gate electrode and the gate pad; forming a semiconductor film pattern over the insulating film in the TFT area by a second photolithography process; forming a source electrode/drain electrode and pad electrode in the TFT portion and pad portion, respectively, using a third photolithography process, the source electrode/drain electrode and pad electrode all being comprised of a third metal film; forming a passivation film pattern by a fourth photolithography process, the passivation film exposing a portion of the drain electrode, a portion of the gate pad, and a portion of the pad electrode; exposing the first metal film by etching a portion of the second metal film that comprises the gate pad
  • the first metal film is preferably formed of a refractory metal, i.e., one selected from the group consisting of Cr, Ta, Mo, and Ti and the second metal film is preferably formed of Al or an Al-alloy.
  • the third metal film preferably comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti.
  • Taper-etching is preferably performed on the second metal film in the first photolithography process and then etching the first metal film is performed, thus the first metal film is wider than the second metal film.
  • a method for manufacturing a liquid crystal display comprising the steps of forming a gate electrode and a gate pad by depositing a first metal film and a second metal film over a substrate of a TFT area and a pad area, respectively, by a first photolithography process; forming an insulating film over the gate electrode and the gate pad; forming a semiconductor film pattern over the insulating film in the TFT area by a second photolithography process; forming a source electrode and a drain electrode in the TFT area by a third photolithography process, the source electrode and the drain electrode comprising a third metal film; forming a passivation film pattern that exposes a portion of the drain electrode of the TFT area and a portion of the gate pad of the pad area by forming a passivation film over the source electrode and the drain electrode and performing a fourth photolithography process on the passivation film and the insulating film; exposing the first metal film of the pad area by etching the second metal film using the pass
  • the first metal film is preferably formed of a refractory metal, i.e., one selected from the group consisting of Cr, Ta, Mo, and Ti and the second metal film is preferably formed of Al or an Al-alloy.
  • the third metal film preferably comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti and the insulating film preferably comprises a nitride film SiN x or a double film of a nitride film SiN x and an oxide film SiO x .
  • Taper-etching is preferably performed on the second metal film in the first photolithography process and then etching the first metal film is performed.
  • the present invention it is possible to reduce the number of photolithography processes by forming the gate electrode in a double structure of a refractory metal film and an Al film formed on the upper portion of the refractory metal film, thus sharply reducing manufacturing costs and improving manufacturing yield. Also, it is possible to suppress growth of a hillock of the Al film due to a stress relaxation of the refractory metal film and to reduce contact resistance between a pixel electrode to be formed in a following process and the Al film by etching the Al film which constitutes the gate electrode prior to forming the pixel electrode.
  • FIGS. 1 through 5 are sectional views illustrating a conventional method for manufacturing a liquid crystal display
  • FIG. 6 is a schematic plan view illustrating the mask patterns used in manufacturing a liquid crystal display according to first and second preferred embodiments of the present invention.
  • FIGS. 7 through 12 are sectional views illustrating a method for manufacturing a liquid crystal display according to a first preferred embodiment of the present invention.
  • FIGS. 13 through 16 are sectional views illustrating a method for manufacturing a liquid crystal display according to a second preferred embodiment of the present invention.
  • FIG. 6 is a schematic plan view of the mask patterns used for manufacturing a liquid crystal display according to the present invention, in which reference numeral 100 denotes a mask pattern for forming a gateline; reference numeral 105 denotes a mask pattern for forming a gate pad; reference numeral 110 denotes a mask pattern for forming a data line, reference numeral 115 denotes a mask pattern for forming a data pad; reference numeral 120 denotes a mask pattern for forming a semiconductor film; reference numeral 130 denotes a mask pattern for forming a source electrode/drain electrode; reference numeral 140 denotes a mask pattern for forming a contact hole for connecting a pixel electrode to the drain electrode in the TFT area; reference numeral 145 denotes a mask pattern for forming a contact hole for connecting a gate pad in the pad area to the pixel electrode; reference numeral 150 denotes a mask pattern for forming a pixel electrode in the TFT area; and reference numeral 155 denotes
  • the gate line 100 is arranged horizontally, and the data line 110 is arranged perpendicular to the gate line.
  • the plurality of gate lines 100 and data lines 110 in the device are arranged together in a matrix pattern.
  • the gate pad 105 is provided at the end portion of the gate line 100
  • the data pad 115 is provided at the end portion of the data line 110 .
  • Pixel portions are respectively arranged in the matrix pattern in the portion bounded by the two adjacent gate lines and the data line.
  • the gate electrodes of the respective TFTs are formed so as to protrude into the pixel portions from the respective gate lines.
  • the semiconductor film 120 is formed between the drain electrodes and the gate electrodes of the respective TFTs.
  • the source electrodes of the TFTs are formed in protruding portions from the data line 110 .
  • the pixel electrodes 150 comprise transparent ITO and are formed in the respective pixel portions.
  • FIGS. 7 to 12 are sectional views illustrating a method for manufacturing a liquid crystal display according to a first embodiment of the present invention.
  • the reference character “C” denotes the TFT area, which is a sectional view taken along I-I′of FIG. 6 .
  • the reference characters “D” and “E” denote the gate-pad connecting area and the pad area, respectively, which are sectional views taken along II-II′ of FIG. 6 .
  • FIG. 7 shows the steps for forming a gate electrode.
  • a first metal film 31 is formed by depositing a thick film of refractory metal on a transparent substrate 30 .
  • a second metal film 33 is then formed by depositing a thick film of Al or an Al-alloy over the first metal film 31 .
  • the first metal film 31 is preferably a 300 ⁇ -4,000 ⁇ thick, and preferably comprises one of Cr, Ta, Mo, and Ti, most preferably Cr.
  • the second metal film 33 is preferably 1,000 ⁇ -4,000 ⁇ thick and comprises Al or an Al-alloy such as Al—Nd or Al—Ta.
  • Gate electrodes are then formed in the TFT area and the gate-pad connecting area by performing a first photolithography on the first and the second metal films 31 and 33 .
  • the first photolithography process is performed by taper-etching the second metal film 33 and then the first metal film 31 . In this way, the width of the first metal film 31 is made larger than that of the second metal film 33 .
  • FIG. 8 shows the steps for forming a semiconductor film pattern.
  • An insulating film 35 is formed by depositing a nitride film or an oxide film, for example, over the entire surface of the substrate 30 on which the gate electrode is formed.
  • a semiconductor film is then formed by depositing an amorphous silicon film 37 and a doped amorphous silicon film 39 over the entire surface of the substrate 30 on which the insulating layer is formed.
  • the semiconductor film pattern which is itself comprised of the amorphous silicon film 37 and the doped amorphous silicon film 39 , is formed in the TFT area by performing a second photolithography on the doped and undoped semiconductor films 39 and 37 .
  • the insulating film 35 , the amorphous silicon film 37 , and the doped amorphous silicon film 39 are preferably formed to thicknesses of 2,000 ⁇ 9,000 ⁇ , 1,000 ⁇ 4,000 ⁇ , and 300 ⁇ 1,000 ⁇ , respectively.
  • FIG. 9 shows the steps for forming a source electrode 41 a and a drain electrode 41 b.
  • a third metal film is initially deposited over the entire surface of the substrate on which the semiconductor film pattern is formed.
  • a source electrode 41 a and a drain electrode 41 b are then formed in the TFT area and a pad electrode 41 c is formed in the pad area by performing a third photolithography on the third metal film.
  • the third metal film is preferably about 300 ⁇ 4,000 ⁇ thick, and comprises a refractory metal such as the Cr.
  • a portion of the doped amorphous silicon film 39 is also etched, thus exposing a portion of the amorphous silicon film 37 .
  • FIG. 10 shows the steps for forming a passivation film pattern 43 .
  • a passivation film is formed over the entire surface of the substrate 30 .
  • the passivation film is preferably a nitride film.
  • the passivation film pattern 43 is then subjected to a fourth photolithography to create the passivation film pattern 43 .
  • a portion of the drain electrode 41 b of the TFT area and a portion of the pad electrode 41 c of the pad area are exposed.
  • the gate electrode formed in the gate pad connecting portion is simultaneously etched, thus exposing the second metal film 33 .
  • the gate pad connecting portion includes the passivation film pattern 43 and the insulating film 35 formed on the second metal film 33 .
  • FIG. 11 shows steps of etching the exposed second metal film 33 of the gate-pad connecting area.
  • the first metal film 31 is initially exposed by etching the second metal film 33 in the gate pad connecting portion 45 and the passivation film pattern 43 . This process reduces the contact resistance between the pixel electrode 47 to be formed in a subsequent process and the second metal film 33 .
  • FIG. 12 shows the steps for forming a pixel electrode 47 .
  • an ITO film is deposited over the entire surface of the substrate 30 on which the passivation film pattern is formed.
  • the ITO film is then subjected to a fifth photolithography to create the pixel electrode 47 .
  • the pixel electrode 47 and the drain electrode 41 b are connected in the TFT area.
  • the gate electrode of the gate-pad connecting area and the pad electrode 41 c of the pad area are connected through the pixel electrode 47 .
  • FIGS. 13 through 16 are sectional views for explaining a method for manufacturing a liquid crystal display according to a second preferred embodiment of the present invention.
  • Reference character “F” denotes a TFT area, which is a sectional view taken along the line I-I′ of FIG. 6 and reference character “G” represents a pad area, which is a sectional view taken along the line II-II′ of FIG. 6 .
  • FIG. 13 shows the step for forming the gate electrode.
  • a first metal film 51 is formed by depositing a film of a refractory metal over the entire surface of the transparent substrate 50 .
  • a second metal film 53 is then formed by depositing a film of Al or Al-alloy over the first metal film.
  • the refractory metal is preferably 300 ⁇ 4,000 ⁇ thick, and preferably comprises Cr, Ta, or Ti.
  • the second metal film in preferably 1,000 ⁇ 4,000 ⁇ thick.
  • the gate electrode and the gate pad are then formed in the TFT area and the pad area by performing a first photolithography on the first and second metal films 51 and 53 .
  • the gate electrode and the gate pad are simultaneously formed using a single mask.
  • taper-etching is performed on the second metal film 53 and then on the first metal film 51 .
  • the first metal film 51 is made wider than the second metal film 53 .
  • FIG. 14 shows the step of forming a semiconductor film pattern.
  • a semiconductor film pattern to be used as an active area is formed in the TFT area.
  • the semiconductor film pattern is formed by depositing an insulating film 55 and a semiconductor film over the entire surface of the substrate 50 in which the gate electrode and the gate pad are formed, and then performing a second photolithography on the semiconductor film.
  • the insulating film 55 is preferably formed to a thickness of 2,000 ⁇ 9,000 ⁇ using a single-film nitride film SiN x or a double-film comprising a nitride film SiN x and an oxide film SiO x .
  • the semiconductor film pattern preferably comprises an amorphous silicon layer 57 and a doped amorphous silicon layer 59 .
  • FIG. 15 shows the steps for forming a source electrode 61 a and a drain electrode 61 b.
  • the source electrode 61 a and the drain electrode 61 b are formed in the TFT area from a third metal film of a refractory metal.
  • the third metal film is initially deposited over the entire surface of the substrate 50 on which the semiconductor film pattern 57 , and is then subjected to a third photolithography to form the source electrode 61 a and the drain electrode 61 b.
  • the third metal film is preferably 300 ⁇ 4,000 ⁇ thick and preferably comprises Cr, Ti, or Mo.
  • FIG. 16 shows the steps of forming a passivation film pattern 63 and a pixel electrode 65 .
  • a passivation film is initially formed by depositing a film such as a nitride film over the entire surface of the substrate in which the source electrode 61 a and the drain electrode 61 b are formed.
  • a fourth photolithography is then performed on the passivation film to form the passivation film patters 63 .
  • the fourth photolithography a portion of the drain electrode 61 b of the TFT area is exposed and the insulating film and the passivation film in the upper portion of the gate pad are simultaneously etched in the pad area, thus exposing a portion of the gate pad.
  • the first metal film 51 is then exposed by etching the portion of the second metal film 53 that is exposed by the passivation film pattern. It is possible to reduce the contact resistance between a pixel electrode 65 to be formed in a subsequent process and the second metal film 53 by etching the second metal film 53 .
  • the pixel electrode 65 which is connected to the drain electrode 61 b of the TFT area and to the first metal film of the pad area, is then formed by depositing the ITO film over the existing structure.
  • the method for manufacturing the liquid crystal display according to the present invention makes it possible to reduce manufacturing costs and to improve the manufacturing yield by using double gate electrodes. Using these methods, only five photolithography processings are required compared to the seven or more photolithography processings required by conventional methods.

Abstract

A method for manufacturing a liquid crystal display which reduces the number of photolithography processes is provided. The method includes the steps of forming a gate electrode and a gate pad by depositing a first metal film and a second metal film on a substrate of a TFT area and a gate-pad connecting area, respectively, in the described order, by a first photolithography process, forming an insulation film on the entire surface of the substrate on which the gate electrode and the gate pad are formed, forming a semiconductor film pattern on the insulating film of the TFT area by a second photolithography process, forming a source electrode/drain electrode and pad electrode composed of a third metal film using a third photolithography process in the TFT portion and pad portion, respectively, forming a passivation film pattern which exposes a portion of the drain electrode, a portion of the gate pad, and a portion of the pad electrode by a fourth photolithography process, exposing the first metal film by etching the second metal film which constitutes the gate pad using the passivation film pattern as a mask, and forming a pixel electrode connected to the drain electrode of the TFT area for connecting the gate pad of the gate-pad connecting area to the pad electrode of the pad area using a fifth photolithography process. Therefore, it is possible to reduce the number of photolithography processes, to improve the manufacturing yield, and to suppress growth of a hillock of an Al film.

Description

Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,811,318. The present reissue application is a continuation of reissue application Ser. No. 09/667,643, which is a reissue of U.S. Pat. No. 5,811,318.
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a liquid crystal display. More particularly, the present invention relates to a method for manufacturing a liquid crystal display having a thin film transistor as an active device, by which it is possible to reduce the number of the photolithography processes.
The liquid crystal display (LCD) is currently the most widely used flat-panel display device. Other devices being developed and rapidly becoming popular include the plasma display panel (PDP), the electro luminescence (EL) device, the field emission display (FED), and the reflex deformable mirror device (DMD), which controls the movement of a mirror.
The LCD uses an optical characteristic of liquid crystal molecules in which the arrangement thereof changes according to an electrical field and a semiconductor technology which forms minute patterns. A thin film transistor LCD (“TFT-LCD”), which uses the thin film transistor as the active device, has various advantages over other LCDs. These advantages include low power consumption, low drive voltage, a thinness, and lightness of weight, among others.
Since the thin film transistor (“TFT”) is significantly thinner than a conventional transistor, the process of manufacturing a TFT is complicated, resulting in low productivity and high manufacturing costs. In particular, since a mask is used in every step for manufacturing a TFT, at least seven masks are required. Therefore, various methods for increasing productivity of the TFT and lowering the manufacturing costs have been studied. In particular, a method for reducing the number of the masks used during the manufacturing process has been widely researched.
FIGS. 1 to 5 are sectional views for explaining a conventional method for manufacturing an LCD, as disclosed in U.S. Pat. No. 5,054,887.
In the drawings, reference characters “A” and “B” denote a TFT area and a pad area, respectively. Referring to FIG. 1, after forming a first metal film by depositing pure Al on a transparent substrate 2, gate patterns 4 and 4a are formed out of the first metal film by performing a first photolithography on the first metal film. The gate patterns are then used as a gate electrode 4 in the TFT area and as a gate pad 4a in the pad area.
As shown in FIG. 2, after forming by general photolithography a second photoresist pattern (not shown) that covers a portion of the pad area, an anodized film 6 is formed by oxidizing the first metal film using the photoresist pattern as an anti-oxidation film. The anodized film 6 is then formed on the entire surface of the gate electrode 4 formed in the TFT area, and on a portion of the gate pad 4a in the pad area.
Referring to FIG. 3, an insulating film 8 is formed by depositing a layer such as a nitride film over the anodized film 6. A semiconductor film is then formed by subsequently depositing an amorphous silicon film 10 and an amorphous silicon film 12 doped with impurities on the entire surface of the substrate 2 on which the insulating film 8 is formed. A semiconductor film pattern 10 and 12 to be used as an active portion is then formed in the TFT area by performing a third photolithography on the semiconductor film.
As shown in FIG. 4, a fourth photoresist pattern (not shown) is then formed that exposes a portion of the gate pad 4a formed in the pad area by performing a fourth photolithography on the entire surface of the substrate 2 on which the semiconductor film pattern is formed. Then, a contact hole is then formed in the insulating film 8, which contact hole exposes a portion of the gate pad 4a. The contact hole is formed by etching the insulating film 8 using the fourth photoresist pattern as a mask. A source electrode 14a and a drain electrode 14b are then formed in the TFT area by depositing a chromium (“Cr”) film on the entire surface of the substrate having the contact hole and performing a fifth photolithography on the Cr film. In the pad area, a pad electrode 14c connected to the gate pad 4a through the contact hole is formed. At this time, the impurity doped-amorphous silicon film 12 on the upper portion of the gate electrode 4 formed in the TFT area during the photolithography process is partially etched, thus exposing a portion of the amorphous silicon film 10.
Referring to FIG. 5, a protection film 16 is then formed by depositing an oxide film over the entire surface of the substrate 2 on which the source electrode 14a, the drain electrode 14b and the pad electrode 14c are formed. Then, contact holes are formed that expose a portion of the drain electrode 14b of the TFT area and a portion of the pad electrode 14c of the pad area. The contact holes are formed by performing a sixth photolithography on the protection film 16.
Subsequently, pixel electrodes 18 and 18a are formed by depositing indium tin oxide (“ITO”), a transparent conductive material, over the entire surface of the substrate, including the contact hole, and performing a seventh photolithography process on the resultant ITO film. As a result of this seventh lithography, the drain electrode 14b and the pixel electrode 18 are connected in the TFT area, and the pad electrode 14c and the pixel electrode 18a are connected in the pad area.
According to the conventional method for manufacturing the LCD, pure aluminum (“Al”) is used as the gate electrode material to lower the resistance of a gate line. An anodizing process is therefore required to prevent a hillock caused by the Al. This additional anodizing step complicates the manufacturing process, reduces productivity, and increases manufacturing costs.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a more efficient method for manufacturing a liquid crystal display in which manufacturing costs are reduced by reducing the number of photolithography processes.
To achieve the above object, there is provided a method for manufacturing a liquid crystal display according to the present invention, comprising the steps of forming a gate electrode and a gate pad by depositing a first metal film and a second metal film over a substrate in a TFT area and a gate-pad connecting area, respectively, by a first photolithography process; forming an insulating film over the gate electrode and the gate pad; forming a semiconductor film pattern over the insulating film in the TFT area by a second photolithography process; forming a source electrode/drain electrode and pad electrode in the TFT portion and pad portion, respectively, using a third photolithography process, the source electrode/drain electrode and pad electrode all being comprised of a third metal film; forming a passivation film pattern by a fourth photolithography process, the passivation film exposing a portion of the drain electrode, a portion of the gate pad, and a portion of the pad electrode; exposing the first metal film by etching a portion of the second metal film that comprises the gate pad using the passivation film pattern as a mask; and forming a pixel electrode connected to the drain electrode of the TFT area by a fifth photolithography process, the pixel electrode acting to connect the gate pad of the gate-pad connecting area to the pad electrode of the pad area.
The first metal film is preferably formed of a refractory metal, i.e., one selected from the group consisting of Cr, Ta, Mo, and Ti and the second metal film is preferably formed of Al or an Al-alloy.
The third metal film preferably comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti.
Taper-etching is preferably performed on the second metal film in the first photolithography process and then etching the first metal film is performed, thus the first metal film is wider than the second metal film.
To achieve the above object, there is provided another method for manufacturing a liquid crystal display, comprising the steps of forming a gate electrode and a gate pad by depositing a first metal film and a second metal film over a substrate of a TFT area and a pad area, respectively, by a first photolithography process; forming an insulating film over the gate electrode and the gate pad; forming a semiconductor film pattern over the insulating film in the TFT area by a second photolithography process; forming a source electrode and a drain electrode in the TFT area by a third photolithography process, the source electrode and the drain electrode comprising a third metal film; forming a passivation film pattern that exposes a portion of the drain electrode of the TFT area and a portion of the gate pad of the pad area by forming a passivation film over the source electrode and the drain electrode and performing a fourth photolithography process on the passivation film and the insulating film; exposing the first metal film of the pad area by etching the second metal film using the passivation film pattern as a mask; and forming a pixel electrode that is connected to the drain electrode of the TFT area and contacts the first metal film of the pad area by a fifth photolithography process.
The first metal film is preferably formed of a refractory metal, i.e., one selected from the group consisting of Cr, Ta, Mo, and Ti and the second metal film is preferably formed of Al or an Al-alloy.
The third metal film preferably comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti and the insulating film preferably comprises a nitride film SiNx or a double film of a nitride film SiNx and an oxide film SiOx.
Taper-etching is preferably performed on the second metal film in the first photolithography process and then etching the first metal film is performed.
According to the present invention, it is possible to reduce the number of photolithography processes by forming the gate electrode in a double structure of a refractory metal film and an Al film formed on the upper portion of the refractory metal film, thus sharply reducing manufacturing costs and improving manufacturing yield. Also, it is possible to suppress growth of a hillock of the Al film due to a stress relaxation of the refractory metal film and to reduce contact resistance between a pixel electrode to be formed in a following process and the Al film by etching the Al film which constitutes the gate electrode prior to forming the pixel electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
The above object and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:
FIGS. 1 through 5 are sectional views illustrating a conventional method for manufacturing a liquid crystal display;
FIG. 6 is a schematic plan view illustrating the mask patterns used in manufacturing a liquid crystal display according to first and second preferred embodiments of the present invention;
FIGS. 7 through 12 are sectional views illustrating a method for manufacturing a liquid crystal display according to a first preferred embodiment of the present invention; and
FIGS. 13 through 16 are sectional views illustrating a method for manufacturing a liquid crystal display according to a second preferred embodiment of the present invention.
 DETAILED DESCRIPTION OF THE INVENTION
FIG. 6 is a schematic plan view of the mask patterns used for manufacturing a liquid crystal display according to the present invention, in which reference numeral 100 denotes a mask pattern for forming a gateline; reference numeral 105 denotes a mask pattern for forming a gate pad; reference numeral 110 denotes a mask pattern for forming a data line, reference numeral 115 denotes a mask pattern for forming a data pad; reference numeral 120 denotes a mask pattern for forming a semiconductor film; reference numeral 130 denotes a mask pattern for forming a source electrode/drain electrode; reference numeral 140 denotes a mask pattern for forming a contact hole for connecting a pixel electrode to the drain electrode in the TFT area; reference numeral 145 denotes a mask pattern for forming a contact hole for connecting a gate pad in the pad area to the pixel electrode; reference numeral 150 denotes a mask pattern for forming a pixel electrode in the TFT area; and reference numeral 155 denotes a mask pattern for forming a pixel electrode in the pad portion.
Referring to FIG. 6, the gate line 100 is arranged horizontally, and the data line 110 is arranged perpendicular to the gate line. The plurality of gate lines 100 and data lines 110 in the device are arranged together in a matrix pattern. The gate pad 105 is provided at the end portion of the gate line 100, and the data pad 115 is provided at the end portion of the data line 110. Pixel portions are respectively arranged in the matrix pattern in the portion bounded by the two adjacent gate lines and the data line. The gate electrodes of the respective TFTs are formed so as to protrude into the pixel portions from the respective gate lines. The semiconductor film 120 is formed between the drain electrodes and the gate electrodes of the respective TFTs. The source electrodes of the TFTs are formed in protruding portions from the data line 110. The pixel electrodes 150 comprise transparent ITO and are formed in the respective pixel portions.
FIGS. 7 to 12 are sectional views illustrating a method for manufacturing a liquid crystal display according to a first embodiment of the present invention. The reference character “C” denotes the TFT area, which is a sectional view taken along I-I′of FIG. 6. The reference characters “D” and “E” denote the gate-pad connecting area and the pad area, respectively, which are sectional views taken along II-II′ of FIG. 6.
FIG. 7 shows the steps for forming a gate electrode. Initially, a first metal film 31 is formed by depositing a thick film of refractory metal on a transparent substrate 30. A second metal film 33 is then formed by depositing a thick film of Al or an Al-alloy over the first metal film 31. The first metal film 31 is preferably a 300 Å-4,000 Å thick, and preferably comprises one of Cr, Ta, Mo, and Ti, most preferably Cr. The second metal film 33 is preferably 1,000 Å-4,000 Å thick and comprises Al or an Al-alloy such as Al—Nd or Al—Ta.
Gate electrodes are then formed in the TFT area and the gate-pad connecting area by performing a first photolithography on the first and the second metal films 31 and 33. At this time, the first photolithography process is performed by taper-etching the second metal film 33 and then the first metal film 31. In this way, the width of the first metal film 31 is made larger than that of the second metal film 33.
It is possible to prevent generation of an Al hillock caused by the differences in thermal expansion between the Al film or the Al-alloy film and the substrate by forming a refractory metal film in the lower portion of the Al film or the Al-alloy film. Also, it is possible to perform the taper-etching using the difference in etching ratio between the Al film or the Al-alloy film and the substrate even though a conventional etching processing is applied. Therefore, a step coverage is preferably performed when depositing a following material after forming the gate electrode.
FIG. 8 shows the steps for forming a semiconductor film pattern. An insulating film 35 is formed by depositing a nitride film or an oxide film, for example, over the entire surface of the substrate 30 on which the gate electrode is formed. A semiconductor film is then formed by depositing an amorphous silicon film 37 and a doped amorphous silicon film 39 over the entire surface of the substrate 30 on which the insulating layer is formed. The semiconductor film pattern, which is itself comprised of the amorphous silicon film 37 and the doped amorphous silicon film 39, is formed in the TFT area by performing a second photolithography on the doped and undoped semiconductor films 39 and 37. The insulating film 35, the amorphous silicon film 37, and the doped amorphous silicon film 39 are preferably formed to thicknesses of 2,000˜9,000 Å, 1,000˜4,000 Å, and 300˜1,000 Å, respectively.
FIG. 9 shows the steps for forming a source electrode 41a and a drain electrode 41b. A third metal film is initially deposited over the entire surface of the substrate on which the semiconductor film pattern is formed. A source electrode 41a and a drain electrode 41b are then formed in the TFT area and a pad electrode 41c is formed in the pad area by performing a third photolithography on the third metal film. The third metal film is preferably about 300˜4,000 Å thick, and comprises a refractory metal such as the Cr. During this step, a portion of the doped amorphous silicon film 39 is also etched, thus exposing a portion of the amorphous silicon film 37.
FIG. 10 shows the steps for forming a passivation film pattern 43. Initially, a passivation film is formed over the entire surface of the substrate 30. The passivation film is preferably a nitride film. The passivation film pattern 43 is then subjected to a fourth photolithography to create the passivation film pattern 43. At this time, a portion of the drain electrode 41b of the TFT area and a portion of the pad electrode 41c of the pad area are exposed. Also, the gate electrode formed in the gate pad connecting portion is simultaneously etched, thus exposing the second metal film 33. The gate pad connecting portion includes the passivation film pattern 43 and the insulating film 35 formed on the second metal film 33.
FIG. 11 shows steps of etching the exposed second metal film 33 of the gate-pad connecting area. The first metal film 31 is initially exposed by etching the second metal film 33 in the gate pad connecting portion 45 and the passivation film pattern 43. This process reduces the contact resistance between the pixel electrode 47 to be formed in a subsequent process and the second metal film 33.
FIG. 12 shows the steps for forming a pixel electrode 47. Initially, an ITO film is deposited over the entire surface of the substrate 30 on which the passivation film pattern is formed. The ITO film is then subjected to a fifth photolithography to create the pixel electrode 47. As a result of this process, the pixel electrode 47 and the drain electrode 41b are connected in the TFT area. Also, the gate electrode of the gate-pad connecting area and the pad electrode 41c of the pad area are connected through the pixel electrode 47.
FIGS. 13 through 16 are sectional views for explaining a method for manufacturing a liquid crystal display according to a second preferred embodiment of the present invention. Reference character “F” denotes a TFT area, which is a sectional view taken along the line I-I′ of FIG. 6 and reference character “G” represents a pad area, which is a sectional view taken along the line II-II′ of FIG. 6.
FIG. 13 shows the step for forming the gate electrode. Initially, a first metal film 51 is formed by depositing a film of a refractory metal over the entire surface of the transparent substrate 50. A second metal film 53 is then formed by depositing a film of Al or Al-alloy over the first metal film. The refractory metal is preferably 300˜4,000 Å thick, and preferably comprises Cr, Ta, or Ti. The second metal film in preferably 1,000˜4,000 Å thick. The gate electrode and the gate pad are then formed in the TFT area and the pad area by performing a first photolithography on the first and second metal films 51 and 53.
The gate electrode and the gate pad are simultaneously formed using a single mask. In the first photolithography process, taper-etching is performed on the second metal film 53 and then on the first metal film 51. As a result of this taper-etching, the first metal film 51 is made wider than the second metal film 53.
FIG. 14 shows the step of forming a semiconductor film pattern. A semiconductor film pattern to be used as an active area is formed in the TFT area. The semiconductor film pattern is formed by depositing an insulating film 55 and a semiconductor film over the entire surface of the substrate 50 in which the gate electrode and the gate pad are formed, and then performing a second photolithography on the semiconductor film. The insulating film 55 is preferably formed to a thickness of 2,000˜9,000 Å using a single-film nitride film SiNx or a double-film comprising a nitride film SiNx and an oxide film SiOx. The semiconductor film pattern preferably comprises an amorphous silicon layer 57 and a doped amorphous silicon layer 59.
FIG. 15 shows the steps for forming a source electrode 61a and a drain electrode 61b. The source electrode 61a and the drain electrode 61b are formed in the TFT area from a third metal film of a refractory metal. The third metal film is initially deposited over the entire surface of the substrate 50 on which the semiconductor film pattern 57, and is then subjected to a third photolithography to form the source electrode 61a and the drain electrode 61b. The third metal film is preferably 300˜4,000 Å thick and preferably comprises Cr, Ti, or Mo.
FIG. 16 shows the steps of forming a passivation film pattern 63 and a pixel electrode 65. A passivation film is initially formed by depositing a film such as a nitride film over the entire surface of the substrate in which the source electrode 61a and the drain electrode 61b are formed. A fourth photolithography is then performed on the passivation film to form the passivation film patters 63. In the fourth photolithography, a portion of the drain electrode 61b of the TFT area is exposed and the insulating film and the passivation film in the upper portion of the gate pad are simultaneously etched in the pad area, thus exposing a portion of the gate pad.
The first metal film 51 is then exposed by etching the portion of the second metal film 53 that is exposed by the passivation film pattern. It is possible to reduce the contact resistance between a pixel electrode 65 to be formed in a subsequent process and the second metal film 53 by etching the second metal film 53.
The pixel electrode 65, which is connected to the drain electrode 61b of the TFT area and to the first metal film of the pad area, is then formed by depositing the ITO film over the existing structure.
As mentioned above, the method for manufacturing the liquid crystal display according to the present invention makes it possible to reduce manufacturing costs and to improve the manufacturing yield by using double gate electrodes. Using these methods, only five photolithography processings are required compared to the seven or more photolithography processings required by conventional methods.
In addition, it is possible to suppress the growth of the hillock of the Al film due to the stress relaxation of the refractory metal film by forming the gate electrode of the double films of the refractory metal film and the Al film or Al-alloy film formed on the refractory metal film.
Also, as shown in FIG. 16, it is possible to reduce the contact resistance between the pixel electrode formed in a subsequent process and the Al film by etching the Al film or the Al-alloy film prior to forming the pixel electrode in the pad area.
The present invention is not limited to the above-described embodiments. Various changes and modifications may be effected by one having an ordinary skill in the art and remain within the scope of the invention, as defined by the appended claims.

Claims (37)

1. A method for manufacturing a liquid crystal display, comprising the steps of:
forming a gate electrode and a gate pad by depositing a first metal film and a second metal film over a substrate in a TFT area and a gate-pad connecting area, respectively, by a first photolithography process;
forming an insulating film over the gate electrode and the gate pad;
forming a semiconductor film pattern over the insulating film in the TFT area by a second photolithography process;
forming a source electrode/drain electrode and pad electrode in the TFT portion and pad portion, respectively, using a third photolithography process, the source electrode/drain electrode and pad electrode all being comprised of a third metal film;
forming a passivation film pattern by a fourth photolithography process, the passivation film exposing a portion of the drain electrode, a portion of the gate pad, and a portion of the pad electrode;
exposing the first metal film by etching a portion of the second metal film that comprises the gate pad using the passivation film pattern as a mask; and
forming a pixel electrode connected to the drain electrode of the TFT area by a fifth photolithography process, the pixel electrode acting to connect the gate pad of the gate-pad connecting area to the pad electrode of the pad area.
2. A method for manufacturing a liquid crystal display as recited in claim 1, wherein the first metal film comprises a refractory metal.
3. A method for manufacturing a liquid crystal display as recited in claim 1, wherein the second metal film comprises Al or an Al-alloy.
4. A method for manufacturing a liquid crystal display as recited in claim 2, wherein the first metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti.
5. A method for manufacturing a liquid crystal display as recited in claim 1, wherein the third metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti.
6. A method for manufacturing a liquid crystal display as recited in claim 1, wherein taper-etching is performed on the second metal film in the first photolithography process and then etching of the first metal film is performed.
7. A method for manufacturing a liquid crystal display as recited in claim 1, wherein the first metal film is wider than the second metal film.
8. A method for manufacturing a liquid crystal display, comprising the steps of:
forming a gate electrode and a gate pad by depositing a first metal film and a second metal film over a substrate of a TFT area and a pad area, respectively, by a first photolithography process;
forming an insulating film over the gate electrode and the gate pad;
forming a semiconductor film pattern over the insulating film in the TFT area by a second photolithography process;
forming a source electrode and a drain electrode in the TFT area by a third photolithography process, the source electrode and the drain electrode comprising a third metal film;
forming a passivation film pattern that exposes a portion of the drain electrode of the TFT area and a portion of the gate pad of the pad area by forming a passivation film over the source electrode and the drain electrode and performing a fourth photolithography process on the passivation film and the insulating film;
exposing the first metal film of the pad area by etching the second metal film using the passivation film pattern as a mask; and
forming a pixel electrode that is connected to the drain electrode of the TFT area and contacts the first metal film of the pad area by a fifth photolithography process.
9. A method for manufacturing a liquid crystal display as recited in claim 8, wherein the first metal film comprises a refractory metal.
10. A method for manufacturing a liquid crystal display as recited in claim 8, wherein the second metal film comprises Al or an Al-alloy.
11. A method for manufacturing a liquid crystal display as recited in claim 9, wherein the first metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti.
12. A method for manufacturing a liquid crystal display as recited in claim 8, wherein the third metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti.
13. A method for manufacturing a liquid crystal display as recited in claim 8, wherein taper-etching is performed on the second metal film in the first photolithography process and then etching the first metal film is performed.
14. A method for manufacturing a liquid crystal display as recited in claim 8, wherein the insulating film comprises a nitride film SiNx.
15. A method for manufacturing a liquid crystal display as recited in claim 8, wherein the insulating film comprises a double film including a nitride film SiNx and an oxide film SiOx.
16. A TFT substrate, comprising:
a gate electrode comprising a first metal film over a substrate and a second metal film over the first metal film;
a gate pad consisting the first metal film and a portion of a removed area of the second metal film;
an insulated film over the gate electrode and having an exposed area of the first metal film over the gate pad;
a semiconductor film pattern over the insulated film;
a source electrode formed over a first portion of the semiconductor film pattern;
a drain electrode formed over a second portion of the semiconductor film pattern;
a passivation film pattern formed over the source electrode, having a contact hole over the drain electrode and having an exposed area of the first metal film of the gate pad;
a first pixel electrode pattern electrically contacted to the drain electrode on the passivation film pattern; and
a second pixel electrode pattern electrically contacted to the exposed area of the first metal film of the gate pad.
17. A TFT substrate, as recited in claim 16, wherein the first metal film comprises a refractory metal.
18. A TFT substrate, as recited in claim 17, wherein the first metal film comprises a material selected from the group consisting of CR, Ta, Mo, and Ti.
19. A TFT substrate, as recited in claim 16, wherein the second metal film comprises Al or an Al alloy.
20. A TFT substrate, as recited in claim 16, wherein the insulated film comprises a nitride film SiN.
21. A TFT substrate, as recited in claim 16, wherein the first and second pixel patterns comprise ITO.
22. A TFT substrate, as recited in claim 16, wherein a portion of the passivation film directly contacts the semiconductor film pattern.
23. A TFT substrate, as recited in claim 16, wherein a portion of the passivation film directly contacts the semiconductor film pattern.
24. A TFT substrate as in claim 16, wherein at least one of the first and the second metal film of the gate electrode and the gate pad has tapered-sidewalls.
25. A TFT substrate as in claim 24, wherein the second metal film has tapered sidewalls.
26. A TFT substrate as in claim 16, wherein the semiconductor film pattern comprises:
an amorphous silicon film on the insulated film; and
a doped amorphous silicon film on the amorphous silicon film.
27. A TFT substrate as in claim 16, wherein the second pixel electrode pattern contacts portions of the exposed gate pad.
28. A TFT substrate, comprising:
a gate electrode comprising at least a refractory metal film formed over a first portion of a substrate;
a gate pad comprising the refractory metal film formed on a second portion of a substrate;
an insulated film formed over the gate electrode and having an exposed area corresponding to the refractory metal film of the gate pad;
a semiconductor film pattern formed over the insulated film;
a source electrode formed over a first portion of the semiconductor film pattern;
a drain electrode formed over a second portion of the semiconductor film pattern;
a passivation film pattern formed over the source electrode, having a contact hole over the drain electrode and having an exposed area corresponding to the refractory metal film of the gate pad;
a first pixel electrode pattern electrically contacted to the drain electrode on the passivation film pattern; and
a second pixel electrode electrically contacted to the exposed area of the refractory metal film of the gate pad.
29. A TFT substrate, as recited in claim 28, wherein the refractory metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti.
30. A TFT substrate, as recited in claim 28, further comprising a second metal film formed on the refractory metal film over the first portion of the substrate, and formed on the refractory metal film of the gate pad except for the exposed area thereof.
31. A TFT substrate, as recited in claim 28, wherein the second metal film comprises Al or Al alloy.
32. A TFT substrate, as recited in claim 28, wherein the insulated film comprises a nitride film SiN.
33. A TFT substrate, as recited in claim 28, wherein the first and second pixel patterns comprise ITO.
34. A TFT substrate as in claim 28, wherein at least one of the first and the second metal film of the gate electrode and the gate pad has tapered-sidewalls.
35. A TFT substrate as in claim 34, wherein the second metal film has tapered sidewalls.
36. A TFT substrate as in claim 28, wherein the semiconductor film pattern comprises:
an amorphous silicon film on the insulated film; and
a doped amorphous silicon film on the amorphous silicon film.
37. A TFT substrate as recite in claim 28, wherein the second pixel electrode pattern contacts portions of the exposed gate pad.
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TW387998B (en) 2000-04-21
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EP0782040A3 (en) 1998-07-15
EP1380880A1 (en) 2004-01-14
JPH09189924A (en) 1997-07-22
JP3976770B2 (en) 2007-09-19
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US5811318A (en) 1998-09-22
JP3891988B2 (en) 2007-03-14
JP3830593B2 (en) 2006-10-04
EP0782040A2 (en) 1997-07-02

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