USRE38961E1 - Method for production of semiconductor package - Google Patents

Method for production of semiconductor package Download PDF

Info

Publication number
USRE38961E1
USRE38961E1 US10/150,379 US15037902A USRE38961E US RE38961 E1 USRE38961 E1 US RE38961E1 US 15037902 A US15037902 A US 15037902A US RE38961 E USRE38961 E US RE38961E
Authority
US
United States
Prior art keywords
bumps
semiconductor wafer
sealant layer
sealant
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/150,379
Inventor
Atsushi Okuno
Koichiro Nagai
Noriko Fujita
Yuki Ishikawa
Noritaka Oyama
Tsunekazu Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyu Rec Co Ltd
Aoi Electronics Co Ltd
Original Assignee
Casio Computer Co Ltd
Sanyu Rec Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd, Sanyu Rec Co Ltd filed Critical Casio Computer Co Ltd
Priority to US10/150,379 priority Critical patent/USRE38961E1/en
Application granted granted Critical
Publication of USRE38961E1 publication Critical patent/USRE38961E1/en
Assigned to TERAMIKROS, INC. reassignment TERAMIKROS, INC. CHANGE OF OWNERSHIP BY CORPORATE SEPARATION Assignors: CASIO COMPUTER CO., LTD.
Assigned to TERAMIKROS, INC. reassignment TERAMIKROS, INC. CHANGE OF OWNERSHIP BY CORPORATE SEPARATION-TO CORRECT ASSIGNEE'S ADDRESS ON REEL 027465, FRAME 0812 Assignors: CASIO COMPUTER CO., LTD.
Assigned to TERA PROBE, INC. reassignment TERA PROBE, INC. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: TERAMIKROS, INC.
Assigned to AOI ELECTRONICS CO., LTD. reassignment AOI ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TERA PROBE, INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a method for producing a chip-size semiconductor package.
  • a resin layer is formed on the bump-arranged surface of the wafer before mounting the semiconductor packages on the printed circuit board. Consequently the methods eliminate the need for the step of filling an encapsulation resin into a narrow space between the semiconductor chips and the printed circuit board after mounting the semiconductor chips on the board so that the mounting reliability is improved. Because of the encapsulation of the wafer with a resin, the methods can achieve a higher production efficiency than the encapsulation of individual semiconductor packages with a resin.
  • the conventional methods pose the following problems due to the use of ai a mold.
  • high investment in equipment is essentially needed.
  • the encapsulating step and heat-curing step are conducted in this order within the mold, the wafer is confined in the mold for a prolonged period of time, thereby lowering the production efficiency.
  • An object of the invention is to provide a method for producing semiconductor packages, the method being capable of lowering the equipment investment, increasing the production efficiency and forming a resin layer with a thickness of 1 mm or less.
  • a method for producing semiconductor package comprising the steps of:
  • FIG. 1 is a perspective view showing an example of semiconductor packages produced by the method for producing semiconductor packages according to the invention.
  • FIG. 2 is a flow chart showing an embodiment of the invention.
  • FIG. 3 is a perspective view schematically showing electronic circuits as formed on the wafer in an embodiment of the method for producing semiconductor packages according to the invention.
  • FIG. 4 is a longitudinal sectional view schematically showing the bumps as formed on the circuit-forming side of the wafer.
  • FIG. 5 is a longitudinal sectional view schematically showing a sealant layer as formed by forcedly filling a sealant using screen printing means.
  • FIG. 6 is a longitudinal sectional view schematically showing the sealant layer as cured on the wafer illustrated in FIG. 4 .
  • FIG. 7 is a longitudinal sectional view schematically showing the sealant layer illustrated in FIG. 6 whose surface is being ground.
  • FIG. 8 is a longitudinal sectional view schematically showing solder balls as placed on and as welded to the upper end surface of bumps illustrated in FIG. 7 .
  • FIG. 9 is a longitudinal sectional view schematically showing the wafer and the sealant layer united as being cut, one by one, into individual semiconductor chips.
  • FIG. 10 is a perspective view schematically showing another example of semiconductor packages produced by the producing method of the invention.
  • FIG. 11 is a longitudinal sectional view schematically showing a sealant layer as being formed by feeding a sealant onto the wafer with bumps on the circuit-forming surface of the wafer and forcedly spreading the sealant on the wafer by screen printing means in the course of producing the semiconductor package as shown in FIG. 10 .
  • FIG. 11a is an enlarged view schematically showing a portion surrounded with a broken-line circle X in FIG. 11 .
  • FIG. 11b is a longitudinal sectional view schematically showing the cross section shape of a portion of sealant layer existing at one end of the wafer after release of the metal mask.
  • FIG. 12 is a longitudinal sectional view schematically showing the sealant layer as cured on the wafer of FIG. 11 .
  • FIG. 13 is a longitudinal sectional view schematically showing the surface of the sealant layer of FIG. 12 as being ground.
  • FIG. 2 is a flow chart showing a first embodiment of the invention.
  • FIGS. 3-9 schematically show respective steps of the method depicted in FIG. 2 .
  • FIG. 1 is a perspective view showing an example of semiconductor packages produced by the producing method practiced stepwise as illustrated in FIG. 2 .
  • the semiconductor package 10 comprises a semiconductor chip 11 , bumps 2 serving as electrodes, a sealant layer 4 having substantially the same height as the bumps 2 and solder balls 3 welded to the upper end surface of bumps. Namely the semiconductor package 10 has a very simple structure.
  • the semiconductor package 10 with said structure is substantially equal in size to the semiconductor chip 11 , and is of the so-called chip-size package structure. Because of this structure, the semiconductor package produced by the method of the invention can satisfactorily fulfil the need for the miniaturized semiconductor packages as required in recent years.
  • the method for producing the semiconductor package 10 is described below with reference to FIGS. 2-9 .
  • the semiconductor package 10 is produced by carrying out the steps shown in FIG. 2 .
  • electronic circuits (not shown) corresponding to a plurality of semiconductor chips 11 , e.g., a few hundreds of semiconductor chips, are formed on a wafer 1 made of a silicone or the like as shown in FIG. 3 .
  • the electronic circuits are formed by conventional techniques as by application of excimer laser.
  • the wafer 1 is subjected to the step of forming bumps.
  • step of forming bumps pillar-shaped bumps 2 with the specified height are provided on the wafer surface 111 provided with the circuit as shown in FIG. 4 .
  • the bumps 2 are formed by the bump-forming technique conventionally used for flip chips or the like, such as the plating method.
  • the wafer 1 is subjected to the step of printing encapsulation.
  • a viscous fluid sealant 40 is forcedly filled by screen printing to form on the entire circuit-forming surface of the wafer 1 a sealant layer 4 having a thickness of height higher than the bumps 2 as shown in FIG. 5 .
  • a specific amount of sealant 40 is fed onto the specified part of the metal mask 6 and forcedly filled into a through-hole 6 a of the metal mask 6 by the reciprocative movement of a squeegee 5 . After filling, the metal mask 6 is released from the sealant layer 4 .
  • the diameter of the through-hole 6 a is substantially equal to or smaller by about 1 to about 10 mm than that of the wafer.
  • Preferred sealing materials useful as the sealant 40 are viscous fluids which are excellent in adhesion to the wafer 1 , and have low shrinkage in curing, low residual stress after curing, low expansion coefficient, low water absorption and high heat resistance.
  • An epoxy resin composition having such properties is suitable as the sealant 40 .
  • Specific examples include a composition containing an epoxy resin and silica in an amount of 60 to 95% by weight based on the composition, such as NPR-780 and NPR-785 (trademarks, products of Japan Rec Co., Ltd.).
  • the air is included into the sealant 40 when the sealant 40 is forcedly filled into the through-hole 6 a of the metal mask 6 .
  • the inclusion of air can be effectively prevented by encapsulation with screen printing means under a vacuum atmosphere preferably in the same vacuum degree between during the forward movement of the squeegee and during the backward movement thereof.
  • the vacuum degree may be varied between during the forward movement of the squeegee and during the backward movement thereof (e.g. under 10 Torr or less in the forward movement and under 50 to 150 Torr in the backward movement).
  • printing means is used for encapsulation, so that the sealant layer can be thinned to a minimum thickness of about 50 ⁇ m. When required, a thick layer up to about 2 mm in thickness can be formed.
  • the wafer 1 is subjected to the step of curing the sealant layer.
  • the wafer 1 with the sealant layer is placed into a known heating furnace to cure the sealant layer as shown in FIG. 6 .
  • the wafer 1 is subjected to the step of exposing the bumps.
  • the surface of the sealant layer 4 is ground with a grinder 7 as shown in FIG. 7 until the upper end surface of the bump 2 becomes exposed.
  • the wafer 1 is subjected to the step of welding solder balls.
  • solder balls 3 for bonding to the printed circuit board are placed onto the exposed upper end surface of the bumps and welded thereto by the conventional ball mounter as shown in FIG. 8 .
  • the solder balls 3 can be welded to the bumps by the conventional bump-forming technique such as a transfer method.
  • the wafer 1 is subjected to the dicing step.
  • the wafer 1 and the sealant layer 4 as united are diced by a known dicer 8 into individual chips 11 , whereby numerous chip-size semiconductor packages 10 are obtained.
  • FIG. 10 is a perspective view schematically showing another example of semiconductor packages produced by the producing method of the invention.
  • a semiconductor package 100 shown in FIG. 10 is produced by practicing the same steps of FIG. 2 as done in producing the semiconductor package 10 of FIG. 1 except that the steps of printing encapsulation, curing the sealant layer and exposing the bumps are different from the corresponding steps of the first embodiment.
  • FIGS. 11 to 13 are depicted for clarification of the different steps in the second embodiment.
  • the semiconductor package 100 comprises a semiconductor chip 11 , bumps 2 , a sealant layer 400 and solder balls 3 which are provided in the semiconductor package 10 of the first embodiment.
  • the upper surface of the sealant layer 400 does not evenly extend and covers the bumps 2 in such a manner that the bump 2 is individually surrounded with a slope as shown in FIG. 10 .
  • the semiconductor package 100 is such that the bumps 2 are reinforced by the sealant layer 400 and the circuit-forming surface 111 of the chip 11 is covered and protected with the sealant layer 400 . Consequently the semiconductor package 100 is equal in mounting reliability to the semiconductor package 10 of the first embodiment shown in FIG. 1 .
  • the method for producing the semiconductor package 100 is described below.
  • the steps of forming electronic circuits and forming bumps as shown in FIG. 2 are initially conducted, followed by the step of encapsulating the surface of the wafer.
  • the steps of forming electronic circuits and forming bumps are identical with those executed in producing the semiconductor package 10 according to the first embodiment, Thus, the description of the steps is omitted.
  • a squeegee 5 made of an elastic material such as rubber is vertically stretched or retracted to forcedly fill the sealant 40 into the through-hole 6 a of the metal mask 6 in the printing encapsulation step of the second embodiment.
  • the sealant 40 is raked out to form the sealant layer 400 which is concave and convex with the bumps 2 individually surrounded with a slope.
  • the squeegee 5 in the initial position ( FIG. 11 , L 1 ) is retracted as strongly pressed against the upper surface of the metal mask 6 .
  • the squeegee 5 proceeds to forcedly fill the sealant 40 into the through-hole 6 a and then stretches downward to rake out the sealant 40 so that each bump 2 is surrounded with an inclined portion of the sealant layer 400 .
  • the location void of the bumps 2 FIG.
  • FIG. 11a is an enlarged view schematically showing a portion surrounded with a broken-line circle X in FIG.
  • the thickness H 2 of the sealant layer 400 on the upper surface of the bumps 2 may be about 20 ⁇ m and the thickness H 3 of the sealant layer 400 in the location void of the bumps 2 may be about 50 ⁇ m.
  • the metal mask 6 and the wafer 1 are adjusted in vertical position so that the upper surface of the metal mask 6 is at a lower level than the top of the bumps 2 .
  • 11b is a longitudinal sectional view schematically showing the cross section shape of a portion of sealant layer 400 at one end of the wafer 1 after release of the metal mask 6 .
  • a sealant layer portion 400 a at one end of the metal mask 6 levels off to become substantially identical in thickness with a sealant layer portion 400 b between the bumps 2 . In this way, it becomes possible to cut the wafer 1 with the resin layer into semiconductor packages 100 individually having substantially the same cross section shape.
  • the sealant 40 When the sealant layer 400 is formed according to the second embodiment, the sealant 40 will be consumed in a reduced amount, whereby lower costs are involved in producing semiconductor packages, as compared with the costs for producing semiconductor packages according to the first embodiment.
  • the second embodiment can employ favorable techniques used in the first embodiment such as materials of the sealant 40 , and printing encapsulation under a vacuum atmosphere.
  • the wafer 1 is subject(ed to the step of curing the sealant layer.
  • the printed wafer 1 is placed into a heating furnace to cure the sealant layer indented between the pairs of bumps as shown in FIG. 12 .
  • the wafer 1 is subjected to the step of exposing the bumps.
  • the surface of the sealant layer 400 is ground with the grinder 7 as shown in FIG. 13 until the upper end surface of the bump 2 becomes exposed.
  • the top of bumps 2 is slightly ground to become horizontal, thereby facilitating welding of solder balls to the top of bumps 2 .
  • the portion to be ground is limited in the second embodiment to the layer on the upper surface of bumps 2 and possibly to the surface of the bumps 2 , whereby grinding is facilitated. Further, a lower resistance to grinding is entailed, whereby the load on the bumps 2 is decreased and the possibility of damaging the bumps 2 is lowered.
  • a plurality of semiconductor packages 100 are obtained following the step of welding solder balls and the dicing steps.
  • the step of welding solder balls and the dicing steps can be carried out in the same manner as in the first embodiment. Thus the description of these steps is omitted.
  • screen printing means is used to encapsulate the entire surface of the wafer with a resin, so that the equipment costs can be markedly reduced as compared with conventional methods using a mold. Since the formation of sealant layer and the heat-curing are separately done, the production operation can be continuously performed without necessity of confining the wafer to a step for a prolonged period of time. Moreover, the sealant layer can be thinned to a minimum thickness of about 50 ⁇ m.

Abstract

The invention provides a method for producing semiconductor packages comprising the steps of forming electronic circuits for a plurality of semiconductor chips 11 on a wafer 1, forming bumps 2 on the plurality of semiconductor chips 11, encapsulating the circuit-forming surface 111 of the wafer 1 and the bumps 2 with a sealant by screen printing means to form a sealant layer 4, curing the sealant layer 4, grinding the surface of the sealant layer 4 until the upper end surface of the bump 2 becomes exposed, placing solder balls on said upper end surface of bumps 2 to weld the balls to the surface thereof, and dicing the wafer 1 and the sealant layer 4 as united into individual semiconductor chips 11. Screen printing means is used to encapsulate the entire surface of the wafer with a resin, so that the equipment costs can be markedly reduced as compared with conventional methods using a mold.

Description

FIELD OF THE INVENTION
The present invention relates to a method for producing a chip-size semiconductor package.
BACKGROUND ART
In view of recent development of electronic equipment such as portable telephones, notebook-size personal computers, electronic personal data books, etc., there are demands for production of semiconductor packages of higher density, smaller size and reduced thickness which are useful for such electronic equipment.
To meet said demands, various kinds of semiconductor packages have been developed. Examples are LSI-mounting TAB, tape carriers, plastic leaded chip carriers (PLCC), ball grid arrays (BGA), chip-size packages (CSP), flip chips, etc. These semiconductor packages have excellent features but are defective in production efficiency and mounting reliability.
Methods have been proposed for producing chip-size semiconductor packages among said semiconductor packages in an attempt to improve the production efficiency and the mounting reliability (of. Japanese Unexamined Patent Publication No. 79362/1998). According to the proposed methods, electronic circuits for a plurality of semiconductor chips are formed on a wafer and bumps are provided on the semiconductor chips. Then, after the wafer is placed into a mold cavity, a resin is supplied to the space around the bumps to encapsulate the bumps by the so-called transfer molding. Thereafter at least the tips of bumps covered with the resin layer are exposed at the surface of the resin layer. Finally the wafer with the resin layer formed thereon is cut into individual semiconductor chips to obtain semiconductor packages.
According to the foregoing conventional methods for producing semiconductor packages, a resin layer is formed on the bump-arranged surface of the wafer before mounting the semiconductor packages on the printed circuit board. Consequently the methods eliminate the need for the step of filling an encapsulation resin into a narrow space between the semiconductor chips and the printed circuit board after mounting the semiconductor chips on the board so that the mounting reliability is improved. Because of the encapsulation of the wafer with a resin, the methods can achieve a higher production efficiency than the encapsulation of individual semiconductor packages with a resin.
However, the conventional methods pose the following problems due to the use of ai a mold. First of all, high investment in equipment is essentially needed. Further, since the encapsulating step and heat-curing step are conducted in this order within the mold, the wafer is confined in the mold for a prolonged period of time, thereby lowering the production efficiency. Moreover, it is difficult to form a resin layer having a thickness of 1 mm or less.
DISCLOSURE OF THE INVENTION
The present invention was accomplished to overcome the above-mentioned prior art problems. An object of the invention is to provide a method for producing semiconductor packages, the method being capable of lowering the equipment investment, increasing the production efficiency and forming a resin layer with a thickness of 1 mm or less.
Other features of the invention will become apparent from the following description.
According to the invention, there is provided a method for producing semiconductor package, the method comprising the steps of:
    • forming electronic circuits for a plurality of semiconductor chips on a wafer;
    • forming bumps on the plurality of semiconductor chips, encapsulating the circuit-forming surface of the wafer and bumps with a sealant by screen printing means to form a sealant layer;
    • curing the sealant layer;
    • grinding the surface of the sealant layer until the upper end surface of the bumps becomes exposed;
    • placing solder balls on said upper end surface of the bumps to weld the balls to the surface thereof; and
    • dicing the wafer and the sealant layer as united into individual semiconductor chips.
BRIEF DESCRIPTION OF THE INVENTION
FIG. 1 is a perspective view showing an example of semiconductor packages produced by the method for producing semiconductor packages according to the invention.
FIG. 2 is a flow chart showing an embodiment of the invention.
FIG. 3 is a perspective view schematically showing electronic circuits as formed on the wafer in an embodiment of the method for producing semiconductor packages according to the invention.
FIG. 4 is a longitudinal sectional view schematically showing the bumps as formed on the circuit-forming side of the wafer.
FIG. 5 is a longitudinal sectional view schematically showing a sealant layer as formed by forcedly filling a sealant using screen printing means.
FIG. 6 is a longitudinal sectional view schematically showing the sealant layer as cured on the wafer illustrated in FIG. 4.
FIG. 7 is a longitudinal sectional view schematically showing the sealant layer illustrated in FIG. 6 whose surface is being ground.
FIG. 8 is a longitudinal sectional view schematically showing solder balls as placed on and as welded to the upper end surface of bumps illustrated in FIG. 7.
FIG. 9 is a longitudinal sectional view schematically showing the wafer and the sealant layer united as being cut, one by one, into individual semiconductor chips.
FIG. 10 is a perspective view schematically showing another example of semiconductor packages produced by the producing method of the invention.
FIG. 11 is a longitudinal sectional view schematically showing a sealant layer as being formed by feeding a sealant onto the wafer with bumps on the circuit-forming surface of the wafer and forcedly spreading the sealant on the wafer by screen printing means in the course of producing the semiconductor package as shown in FIG. 10.
FIG. 11a is an enlarged view schematically showing a portion surrounded with a broken-line circle X in FIG. 11.
FIG. 11b is a longitudinal sectional view schematically showing the cross section shape of a portion of sealant layer existing at one end of the wafer after release of the metal mask.
FIG. 12 is a longitudinal sectional view schematically showing the sealant layer as cured on the wafer of FIG. 11.
FIG. 13 is a longitudinal sectional view schematically showing the surface of the sealant layer of FIG. 12 as being ground.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
This invention will be further clarified by the description of two embodiments with reference to the accompanying drawings. The invention, however, is not limited to the embodiments, but various modifications are possible without deviation from the scope of the invention.
FIG. 2 is a flow chart showing a first embodiment of the invention. FIGS. 3-9 schematically show respective steps of the method depicted in FIG. 2. FIG. 1 is a perspective view showing an example of semiconductor packages produced by the producing method practiced stepwise as illustrated in FIG. 2.
First, the structure of a semiconductor package 10 is described below with reference to FIG. 1. The semiconductor package 10 comprises a semiconductor chip 11, bumps 2 serving as electrodes, a sealant layer 4 having substantially the same height as the bumps 2 and solder balls 3 welded to the upper end surface of bumps. Namely the semiconductor package 10 has a very simple structure.
The semiconductor package 10 with said structure is substantially equal in size to the semiconductor chip 11, and is of the so-called chip-size package structure. Because of this structure, the semiconductor package produced by the method of the invention can satisfactorily fulfil the need for the miniaturized semiconductor packages as required in recent years.
The method for producing the semiconductor package 10 is described below with reference to FIGS. 2-9. The semiconductor package 10 is produced by carrying out the steps shown in FIG. 2.
In the step of forming electronic circuits in FIG. 2, electronic circuits (not shown) corresponding to a plurality of semiconductor chips 11, e.g., a few hundreds of semiconductor chips, are formed on a wafer 1 made of a silicone or the like as shown in FIG. 3. The electronic circuits are formed by conventional techniques as by application of excimer laser.
After practicing the step of forming the electronic circuits, the wafer 1 is subjected to the step of forming bumps. In the step of forming bumps, pillar-shaped bumps 2 with the specified height are provided on the wafer surface 111 provided with the circuit as shown in FIG. 4. The bumps 2 are formed by the bump-forming technique conventionally used for flip chips or the like, such as the plating method.
After practicing the step of forming bumps, the wafer 1 is subjected to the step of printing encapsulation. In the printing encapsulation step, a viscous fluid sealant 40 is forcedly filled by screen printing to form on the entire circuit-forming surface of the wafer 1 a sealant layer 4 having a thickness of height higher than the bumps 2 as shown in FIG. 5. Stated more specifically, after a metal mask 6 and the wafer 1 are properly positioned, a specific amount of sealant 40 is fed onto the specified part of the metal mask 6 and forcedly filled into a through-hole 6a of the metal mask 6 by the reciprocative movement of a squeegee 5. After filling, the metal mask 6 is released from the sealant layer 4. The diameter of the through-hole 6a is substantially equal to or smaller by about 1 to about 10 mm than that of the wafer. Preferred sealing materials useful as the sealant 40 are viscous fluids which are excellent in adhesion to the wafer 1, and have low shrinkage in curing, low residual stress after curing, low expansion coefficient, low water absorption and high heat resistance. An epoxy resin composition having such properties is suitable as the sealant 40. Specific examples include a composition containing an epoxy resin and silica in an amount of 60 to 95% by weight based on the composition, such as NPR-780 and NPR-785 (trademarks, products of Japan Rec Co., Ltd.). It may occur that the air is included into the sealant 40 when the sealant 40 is forcedly filled into the through-hole 6a of the metal mask 6. The inclusion of air can be effectively prevented by encapsulation with screen printing means under a vacuum atmosphere preferably in the same vacuum degree between during the forward movement of the squeegee and during the backward movement thereof. Alternatively the vacuum degree may be varied between during the forward movement of the squeegee and during the backward movement thereof (e.g. under 10 Torr or less in the forward movement and under 50 to 150 Torr in the backward movement). In the method of the invention, printing means is used for encapsulation, so that the sealant layer can be thinned to a minimum thickness of about 50 μm. When required, a thick layer up to about 2 mm in thickness can be formed.
After practicing the step of printing encapsulation, the wafer 1 is subjected to the step of curing the sealant layer. In the step of curing the sealant layer, the wafer 1 with the sealant layer is placed into a known heating furnace to cure the sealant layer as shown in FIG. 6.
After practicing the step of curing the sealant layer, the wafer 1 is subjected to the step of exposing the bumps. In the step of exposing the bumps, the surface of the sealant layer 4 is ground with a grinder 7 as shown in FIG. 7 until the upper end surface of the bump 2 becomes exposed.
After practicing the step of exposing the bumps, the wafer 1 is subjected to the step of welding solder balls. In the step of welding solder balls, solder balls 3 for bonding to the printed circuit board are placed onto the exposed upper end surface of the bumps and welded thereto by the conventional ball mounter as shown in FIG. 8. The solder balls 3 can be welded to the bumps by the conventional bump-forming technique such as a transfer method.
Finally after executing the step of welding solder balls, the wafer 1 is subjected to the dicing step. In the dicing step, the wafer 1 and the sealant layer 4 as united are diced by a known dicer 8 into individual chips 11, whereby numerous chip-size semiconductor packages 10 are obtained.
A second embodiment of the invention will be described below. FIG. 10 is a perspective view schematically showing another example of semiconductor packages produced by the producing method of the invention. A semiconductor package 100 shown in FIG. 10 is produced by practicing the same steps of FIG. 2 as done in producing the semiconductor package 10 of FIG. 1 except that the steps of printing encapsulation, curing the sealant layer and exposing the bumps are different from the corresponding steps of the first embodiment. FIGS. 11 to 13 are depicted for clarification of the different steps in the second embodiment.
First, the semiconductor package 100 according to the second embodiment is described with reference to FIG. 10. The semiconductor package 100 comprises a semiconductor chip 11, bumps 2, a sealant layer 400 and solder balls 3 which are provided in the semiconductor package 10 of the first embodiment. However, unlike the semiconductor package 10, the upper surface of the sealant layer 400 does not evenly extend and covers the bumps 2 in such a manner that the bump 2 is individually surrounded with a slope as shown in FIG. 10. With this structure, the semiconductor package 100 is such that the bumps 2 are reinforced by the sealant layer 400 and the circuit-forming surface 111 of the chip 11 is covered and protected with the sealant layer 400. Consequently the semiconductor package 100 is equal in mounting reliability to the semiconductor package 10 of the first embodiment shown in FIG. 1.
The method for producing the semiconductor package 100 is described below. In the method for producing the semiconductor package 100, the steps of forming electronic circuits and forming bumps as shown in FIG. 2 are initially conducted, followed by the step of encapsulating the surface of the wafer. The steps of forming electronic circuits and forming bumps are identical with those executed in producing the semiconductor package 10 according to the first embodiment, Thus, the description of the steps is omitted. As shown in FIG. 11, a squeegee 5 made of an elastic material such as rubber is vertically stretched or retracted to forcedly fill the sealant 40 into the through-hole 6a of the metal mask 6 in the printing encapsulation step of the second embodiment. Then the sealant 40 is raked out to form the sealant layer 400 which is concave and convex with the bumps 2 individually surrounded with a slope. Stated more specifically, the squeegee 5 in the initial position (FIG. 11, L1) is retracted as strongly pressed against the upper surface of the metal mask 6. Then the squeegee 5 proceeds to forcedly fill the sealant 40 into the through-hole 6a and then stretches downward to rake out the sealant 40 so that each bump 2 is surrounded with an inclined portion of the sealant layer 400. In the location void of the bumps 2 (FIG. 11, L2), the extended squeegee 5 partly scrape out the sealant 40 so that the sealant layer 400 is concave and convex as shown in FIG. 10. On the bump 2 in position (FIG. 11, L2), the squeegee 5 is retracted against its top. After forming a thin layer of sealant 40 atop the bumps 2, the squeegee 5 moves forward beyond the bump 2. The end of the squeegee 5 has a shape with, for example, an inclined face as shown in FIG. 11 so that it can readily retract to prevent the bumps 2 from carrying an excessive load. FIG. 11a is an enlarged view schematically showing a portion surrounded with a broken-line circle X in FIG. 11. For example, if the height H1 of the bump 2 is 130 μm in FIG. 11a, the thickness H2 of the sealant layer 400 on the upper surface of the bumps 2 may be about 20 μm and the thickness H3 of the sealant layer 400 in the location void of the bumps 2 may be about 50 μm. To form a portion of sealant layer 400 at one end of the wafer 1 in substantially the same cross section shape as that of sealant layer 400 between the bumps 2, the metal mask 6 and the wafer 1 are adjusted in vertical position so that the upper surface of the metal mask 6 is at a lower level than the top of the bumps 2. FIG. 11b is a longitudinal sectional view schematically showing the cross section shape of a portion of sealant layer 400 at one end of the wafer 1 after release of the metal mask 6. When the upper surface of the metal mask 6 is brought to a lower level than the top of the bumps 2, a sealant layer portion 400a at one end of the metal mask 6 levels off to become substantially identical in thickness with a sealant layer portion 400b between the bumps 2. In this way, it becomes possible to cut the wafer 1 with the resin layer into semiconductor packages 100 individually having substantially the same cross section shape. When the sealant layer 400 is formed according to the second embodiment, the sealant 40 will be consumed in a reduced amount, whereby lower costs are involved in producing semiconductor packages, as compared with the costs for producing semiconductor packages according to the first embodiment. The second embodiment can employ favorable techniques used in the first embodiment such as materials of the sealant 40, and printing encapsulation under a vacuum atmosphere.
After practicing the step of printing encapsulation, the wafer 1 is subject(ed to the step of curing the sealant layer. In the step of curing the sealant layer, the printed wafer 1 is placed into a heating furnace to cure the sealant layer indented between the pairs of bumps as shown in FIG. 12.
After practicing the step of curing the sealant layer, the wafer 1 is subjected to the step of exposing the bumps. In the step of exposing the bumps, the surface of the sealant layer 400 is ground with the grinder 7 as shown in FIG. 13 until the upper end surface of the bump 2 becomes exposed. After the layer 400 on the bumps 2 is ground to expose the bumps 2, preferably the top of bumps 2 is slightly ground to become horizontal, thereby facilitating welding of solder balls to the top of bumps 2. Unlike the first embodiment, the portion to be ground is limited in the second embodiment to the layer on the upper surface of bumps 2 and possibly to the surface of the bumps 2, whereby grinding is facilitated. Further, a lower resistance to grinding is entailed, whereby the load on the bumps 2 is decreased and the possibility of damaging the bumps 2 is lowered.
After practicing the step of exposing the bumps, a plurality of semiconductor packages 100 are obtained following the step of welding solder balls and the dicing steps. The step of welding solder balls and the dicing steps can be carried out in the same manner as in the first embodiment. Thus the description of these steps is omitted.
According to the producing method of the invention, screen printing means is used to encapsulate the entire surface of the wafer with a resin, so that the equipment costs can be markedly reduced as compared with conventional methods using a mold. Since the formation of sealant layer and the heat-curing are separately done, the production operation can be continuously performed without necessity of confining the wafer to a step for a prolonged period of time. Moreover, the sealant layer can be thinned to a minimum thickness of about 50 μm.

Claims (20)

1. A method for producing semiconductor packages, comprising the steps of :
forming electronic circuits for a plurality of semiconductor chips on a surface of a semiconductor wafer;
forming substantially columnar shaped bumps on circuit-provided the surface of the semiconductor wafer in accordance with the electronic circuits by a plating method, each bump having an upper end and a height;
screen-printing the bump-provided surface of the semiconductor wafer with a resin sealant to encapsulate the bumps, including their the upper ends of the bumps, and the remaining circuit-provided electronic circuits formed on the surface of the semiconductor wafer with the resin sealant, by placing a metal mask having a single through-hole and a thickness which is larger than the height of each bump over the surface of the semiconductor wafer, thereby forming a sealant layer;
curing the sealant layer;
grinding the cured sealant layer downward until the upper ends of the bumps become exposed; and
placing solder balls on the exposed upper ends of the bumps to weld the balls thereto; and
dicing the semiconductor wafer and the sealant layer as an integrated unit into individual semiconductor chips.
2. The method according to claim 1, wherein the screen-printing step comprises the steps of :
placing a mask having through-holes on the bump-provided surface of the wafer;
feeding the resin sealant onto the placed mask; and
squeegeeing the resin sealant onto the bump-provided surface of the semiconductor wafer through the through-holes single through-hole of the mask by sliding a squeegee along the mask with a reciprocative movement.
3. The method according to claim 2, wherein the squeegee is made of elastic material and is passed over the bumps to make in a manner so as to cause the resin sealant to cave in between the bumps while being slid along the mask.
4. The method according to claim 1, wherein the resin sealant is a viscous fluid.
5. The method according to claim 1, further comprising welding solder balls to the bumps.
6. The method according to claim 5, wherein the welding comprises placing the solder balls on the exposed upper ends of the bumps.
7. The method according to claim 1, wherein the screen-printing is performed under a vacuum atmosphere.
8. The method according to claim 1, wherein the bumps have a substantially same width at a lower end as at the upper end, and a same specified height.
9. The method according to claim 1, wherein the single through-hole has a size which is not larger than the size of the wafer.
10. The method according to claim 9, wherein the single through-hole has a diameter which is smaller by about 1 mm to about 10 mm than a diameter of the semiconductor wafer.
11. The method according to claim 1, wherein the resin sealant includes silica.
12. The method according to claim 1, wherein the sealant layer is thinned to a minimum thickness of about 50 μm.
13. The method according to claim 1, wherein the cured sealant layer is ground to a thickness of no less than 50 μm.
14. The method according to claim 1, wherein the resin sealant is screen printed on the entire circuit-forming surface of the semiconductor wafer.
15. The method according to claim 1, wherein the semiconductor wafer comprises a periphery, and the metal mask is placed on the periphery of the semiconductor wafer.
16. The method according to claim 1, wherein the sealant layer is formed on the entire circuit-forming surface of the wafer.
17. The method according to claim 15, wherein the resin sealant includes silica.
18. The method according to claim 17, wherein the forming of the sealant layer comprises squeegeeing the resin sealant onto the surface of the semiconductor wafer through the single through-hole of the mask by sliding a squeegee along the mask with a reciprocative movement.
19. A method comprising:
forming electronic circuits for a plurality of semiconductor chips on a surface of a semiconductor wafer;
forming substantially columnar shaped bumps on the surface of the semiconductor wafer by a plating method, each bump having an upper end and a height;
screen-printing the surface of the semiconductor wafer with a resin sealant including silica in an amount of 60-95 % of the resin sealant by weight to encapsulate the bumps, including the upper ends of the bumps, and the electronic circuits formed on the surface of the semiconductor wafer with the resin sealant, thereby forming a sealant layer;
curing the sealant layer;
grinding the cured sealant layer downward until the upper ends of the bumps become exposed; and
dicing the semiconductor wafer and the sealant layer as an integrated unit into individual semiconductor chips.
20. The method according to claim 19, wherein the screen-printing comprises squeegeeing the resin sealant onto the surface of the semiconductor wafer by sliding a squeegee along a metal mask having a single through-hole.
US10/150,379 1998-10-06 2002-05-16 Method for production of semiconductor package Expired - Lifetime USRE38961E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/150,379 USRE38961E1 (en) 1998-10-06 2002-05-16 Method for production of semiconductor package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/167,207 US6063646A (en) 1998-10-06 1998-10-06 Method for production of semiconductor package
US10/150,379 USRE38961E1 (en) 1998-10-06 2002-05-16 Method for production of semiconductor package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/167,207 Reissue US6063646A (en) 1998-10-06 1998-10-06 Method for production of semiconductor package

Publications (1)

Publication Number Publication Date
USRE38961E1 true USRE38961E1 (en) 2006-01-31

Family

ID=22606396

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/167,207 Ceased US6063646A (en) 1998-10-06 1998-10-06 Method for production of semiconductor package
US10/150,379 Expired - Lifetime USRE38961E1 (en) 1998-10-06 2002-05-16 Method for production of semiconductor package

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/167,207 Ceased US6063646A (en) 1998-10-06 1998-10-06 Method for production of semiconductor package

Country Status (6)

Country Link
US (2) US6063646A (en)
EP (2) EP1724830B1 (en)
KR (2) KR100620088B1 (en)
DE (1) DE69941230D1 (en)
SG (1) SG115329A1 (en)
TW (1) TW421837B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050032271A1 (en) * 2001-05-30 2005-02-10 Nec Electronics Corporation Lead frame, semiconductor device using the same and method of producing the semiconductor device
US20050161814A1 (en) * 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
US20080036072A1 (en) * 2006-08-11 2008-02-14 Vishay General Semiconductor Llc Secmiconductor device and method for manufacturing a semiconductor device
US8604568B2 (en) 2010-11-26 2013-12-10 Cambridge Silicon Radio Limited Multi-chip package
US20140091457A1 (en) * 2012-09-29 2014-04-03 Hongjin Jiang Controlled solder height packages and assembly processes

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2783259B2 (en) * 1996-07-18 1998-08-06 日本電気株式会社 Semiconductor package and manufacturing method thereof
JP3181262B2 (en) * 1998-06-04 2001-07-03 スタンレー電気株式会社 Planar mounting type LED element and manufacturing method thereof
JP2000036552A (en) * 1998-07-17 2000-02-02 Fujitsu Ltd Semiconductor device and separately taking out method of metal component in sealing material used therein
US6903451B1 (en) * 1998-08-28 2005-06-07 Samsung Electronics Co., Ltd. Chip scale packages manufactured at wafer level
DE19842590A1 (en) * 1998-09-17 2000-04-13 Daimler Chrysler Ag Process for the production of circuit arrangements
US6319851B1 (en) 1999-02-03 2001-11-20 Casio Computer Co., Ltd. Method for packaging semiconductor device having bump electrodes
US6159773A (en) * 1999-02-12 2000-12-12 Lin; Mou-Shiung Strain release contact system for integrated circuits
JP2000311921A (en) * 1999-04-27 2000-11-07 Sony Corp Semiconductor device and manufacture thereof
JP2000332165A (en) * 1999-05-17 2000-11-30 Toray Ind Inc Resin composition for sealing semiconductor and semiconductor device employing it
JP3526788B2 (en) * 1999-07-01 2004-05-17 沖電気工業株式会社 Method for manufacturing semiconductor device
JP3223283B2 (en) 1999-09-14 2001-10-29 カシオ計算機株式会社 Method for manufacturing semiconductor device
EP1085564A1 (en) * 1999-09-14 2001-03-21 Casio Computer Co., Ltd. Method for packaging semiconductor device having bump electrodes
JP2001094005A (en) * 1999-09-22 2001-04-06 Oki Electric Ind Co Ltd Semiconductor device and method for producing it
JP3973340B2 (en) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 Semiconductor device, wiring board, and manufacturing method thereof
JP3485513B2 (en) * 2000-01-19 2004-01-13 沖電気工業株式会社 Method for manufacturing semiconductor device
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
US6576496B1 (en) * 2000-08-21 2003-06-10 Micron Technology, Inc. Method and apparatus for encapsulating a multi-chip substrate array
JP4330821B2 (en) * 2001-07-04 2009-09-16 株式会社東芝 Manufacturing method of semiconductor device
US6929981B2 (en) * 2002-09-06 2005-08-16 Advanpack Solutions Pte, Ltd. Package design and method of manufacture for chip grid array
TW554503B (en) * 2002-10-23 2003-09-21 Orient Semiconductor Elect Ltd Fabrication method of solder bump pattern in back-end wafer level package
US7169691B2 (en) * 2004-01-29 2007-01-30 Micron Technology, Inc. Method of fabricating wafer-level packaging with sidewall passivation and related apparatus
KR100817639B1 (en) 2004-03-19 2008-03-27 에스에무케이 가부시키가이샤 Screen-printing metal mask plate and method of resin-sealing vibrating part
TWI285069B (en) * 2004-05-26 2007-08-01 Advanced Semiconductor Eng Screen printing method of forming conductive bumps
US20080079150A1 (en) * 2006-09-28 2008-04-03 Juergen Simon Die arrangement and method for producing a die arrangement
US20090306811A1 (en) * 2008-06-06 2009-12-10 Raytheon Company Ball grid array cleaning system
US8030770B1 (en) * 2008-09-09 2011-10-04 Triquint Semiconductor, Inc. Substrateless package
US8487435B2 (en) 2008-09-09 2013-07-16 Triquint Semiconductor, Inc. Sheet-molded chip-scale package
US20110316201A1 (en) * 2010-06-24 2011-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer Level Packaging Using Blade Molding
US8680683B1 (en) 2010-11-30 2014-03-25 Triquint Semiconductor, Inc. Wafer level package with embedded passive components and method of manufacturing
US9202714B2 (en) * 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
JP6896347B2 (en) * 2017-10-27 2021-06-30 株式会社ディスコ Processing method of work piece
KR102030529B1 (en) * 2018-02-27 2019-10-10 문영엽 Molding apparatus and method for flip chip pakaging

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3644180A (en) * 1970-02-26 1972-02-22 Western Electric Co Methods of using inorganic resists
US4600600A (en) * 1983-11-30 1986-07-15 Siemens Aktiengesellschaft Method for the galvanic manufacture of metallic bump-like lead contacts
US5232651A (en) * 1989-12-11 1993-08-03 Japan Rec Co., Ltd. Method of sealing electric parts mounted on electric wiring board with resin composition
US5318651A (en) * 1991-11-27 1994-06-07 Nec Corporation Method of bonding circuit boards
EP0729182A2 (en) 1995-02-23 1996-08-28 Matsushita Electric Industrial Co., Ltd Chip carrier and method of manufacturing and mounting the same
US5620927A (en) * 1995-05-25 1997-04-15 National Semiconductor Corporation Solder ball attachment machine for semiconductor packages
US5641113A (en) 1994-06-30 1997-06-24 Oki Electronic Industry Co., Ltd. Method for fabricating an electronic device having solder joints
JPH1079362A (en) * 1996-07-12 1998-03-24 Fujitsu Ltd Manufacture of semiconductor device, mold for manufacturing semiconductor device, semiconductor device and mounting method thereof
US5786271A (en) * 1995-07-05 1998-07-28 Kabushiki Kaisha Toshiba Production of semiconductor package having semiconductor chip mounted with its face down on substrate with protruded electrodes therebetween and semiconductor package
US5789279A (en) * 1994-09-20 1998-08-04 Sgs-Thomson Microelectronics S.R.L. Method and apparatus for electrically insulating heat sinks in electronic power devices
DE19754372A1 (en) 1997-03-10 1998-09-24 Fraunhofer Ges Forschung Chip arrangement and method for producing a chip arrangement
US5837427A (en) * 1996-04-30 1998-11-17 Samsung Electro-Mechanics Co Co., Ltd. Method for manufacturing build-up multi-layer printed circuit board
US5849608A (en) * 1996-05-30 1998-12-15 Nec Corporation Semiconductor chip package
US5851845A (en) * 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
US5907786A (en) * 1992-11-11 1999-05-25 Mitsubishi Denki Kabushiki Kaisha Process for manufacturing a flip-chip integrated circuit
US5977641A (en) * 1997-05-14 1999-11-02 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US5989982A (en) * 1997-10-08 1999-11-23 Oki Electric Industry Co., Ltd. Semiconductor device and method of manufacturing the same
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6194250B1 (en) * 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
US6260264B1 (en) * 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6423102B1 (en) * 1994-11-30 2002-07-23 Sharp Kabushiki Kaisha Jig used for assembling semiconductor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3205686B2 (en) * 1995-08-21 2001-09-04 株式会社日立製作所 Semiconductor device for mounting and its mounting method
US5650667A (en) * 1995-10-30 1997-07-22 National Semiconductor Corporation Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created
JP3688065B2 (en) * 1996-07-26 2005-08-24 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
JP2861965B2 (en) * 1996-09-20 1999-02-24 日本電気株式会社 Method of forming bump electrodes
WO1998040912A1 (en) * 1997-03-10 1998-09-17 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Chip arrangement and method for the production of the same

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3644180A (en) * 1970-02-26 1972-02-22 Western Electric Co Methods of using inorganic resists
US4600600A (en) * 1983-11-30 1986-07-15 Siemens Aktiengesellschaft Method for the galvanic manufacture of metallic bump-like lead contacts
US5232651A (en) * 1989-12-11 1993-08-03 Japan Rec Co., Ltd. Method of sealing electric parts mounted on electric wiring board with resin composition
US5318651A (en) * 1991-11-27 1994-06-07 Nec Corporation Method of bonding circuit boards
US5907786A (en) * 1992-11-11 1999-05-25 Mitsubishi Denki Kabushiki Kaisha Process for manufacturing a flip-chip integrated circuit
US5641113A (en) 1994-06-30 1997-06-24 Oki Electronic Industry Co., Ltd. Method for fabricating an electronic device having solder joints
US5789279A (en) * 1994-09-20 1998-08-04 Sgs-Thomson Microelectronics S.R.L. Method and apparatus for electrically insulating heat sinks in electronic power devices
US6423102B1 (en) * 1994-11-30 2002-07-23 Sharp Kabushiki Kaisha Jig used for assembling semiconductor devices
EP0729182A2 (en) 1995-02-23 1996-08-28 Matsushita Electric Industrial Co., Ltd Chip carrier and method of manufacturing and mounting the same
US5620927A (en) * 1995-05-25 1997-04-15 National Semiconductor Corporation Solder ball attachment machine for semiconductor packages
US5786271A (en) * 1995-07-05 1998-07-28 Kabushiki Kaisha Toshiba Production of semiconductor package having semiconductor chip mounted with its face down on substrate with protruded electrodes therebetween and semiconductor package
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
US5851845A (en) * 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
US5837427A (en) * 1996-04-30 1998-11-17 Samsung Electro-Mechanics Co Co., Ltd. Method for manufacturing build-up multi-layer printed circuit board
US5849608A (en) * 1996-05-30 1998-12-15 Nec Corporation Semiconductor chip package
JPH1079362A (en) * 1996-07-12 1998-03-24 Fujitsu Ltd Manufacture of semiconductor device, mold for manufacturing semiconductor device, semiconductor device and mounting method thereof
DE19754372A1 (en) 1997-03-10 1998-09-24 Fraunhofer Ges Forschung Chip arrangement and method for producing a chip arrangement
US5977641A (en) * 1997-05-14 1999-11-02 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US5989982A (en) * 1997-10-08 1999-11-23 Oki Electric Industry Co., Ltd. Semiconductor device and method of manufacturing the same
US6260264B1 (en) * 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6194250B1 (en) * 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, vol. 1998, No. 06, Apr. 30, 1998 and JP 10-050772 A (Hitachi Ltd; Hitachi VLSI Eng. Corp.), Feb. 20, 1998-Abstract only.

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050032271A1 (en) * 2001-05-30 2005-02-10 Nec Electronics Corporation Lead frame, semiconductor device using the same and method of producing the semiconductor device
US7189599B2 (en) * 2001-05-30 2007-03-13 Nec Electronics Corporation Lead frame, semiconductor device using the same and method of producing the semiconductor device
US20050161814A1 (en) * 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
US8962470B2 (en) 2002-12-27 2015-02-24 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
US20080036072A1 (en) * 2006-08-11 2008-02-14 Vishay General Semiconductor Llc Secmiconductor device and method for manufacturing a semiconductor device
US7719096B2 (en) 2006-08-11 2010-05-18 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device
US8604568B2 (en) 2010-11-26 2013-12-10 Cambridge Silicon Radio Limited Multi-chip package
US20140091457A1 (en) * 2012-09-29 2014-04-03 Hongjin Jiang Controlled solder height packages and assembly processes
US9960105B2 (en) * 2012-09-29 2018-05-01 Intel Corporation Controlled solder height packages and assembly processes

Also Published As

Publication number Publication date
EP1724830B1 (en) 2009-08-05
EP1724830A3 (en) 2007-05-09
TW421837B (en) 2001-02-11
EP0993040A3 (en) 2001-03-14
US6063646A (en) 2000-05-16
KR20060092162A (en) 2006-08-22
KR100620088B1 (en) 2006-09-06
KR20000028855A (en) 2000-05-25
DE69941230D1 (en) 2009-09-17
SG115329A1 (en) 2005-10-28
EP1724830A2 (en) 2006-11-22
KR100621670B1 (en) 2006-09-07
EP0993040A2 (en) 2000-04-12

Similar Documents

Publication Publication Date Title
USRE38961E1 (en) Method for production of semiconductor package
US6560122B2 (en) Chip package with molded underfill
US6940182B2 (en) Flip-chip package with underfill dam for stress control
US6495083B2 (en) Method of underfilling an integrated circuit chip
US6987058B2 (en) Methods for underfilling and encapsulating semiconductor device assemblies with a single dielectric material
US6657124B2 (en) Advanced electronic package
US6038136A (en) Chip package with molded underfill
EP0929097A2 (en) Semiconductor device assembly method and semiconductor device produced by the method
JP2001094005A (en) Semiconductor device and method for producing it
TW200905755A (en) Wafer level package structure and fabrication methods
US6555924B2 (en) Semiconductor package with flash preventing mechanism and fabrication method thereof
US20020173074A1 (en) Method for underfilling bonding gap between flip-chip and circuit substrate
JP3622435B2 (en) Semiconductor device and manufacturing method thereof
US6867487B2 (en) Flash-preventing semiconductor package
JP2004128286A (en) Chip-like electronic component and manufacturing method thereof, pseudo wafer used for the manufacturing and manufacturing method thereof, and mounting structure
US20070212868A1 (en) Method, system, and apparatus for gravity assisted chip attachment
US20050051605A1 (en) Process of manufacturing a solder-fill for applying to semiconductor package
JP3694469B2 (en) Manufacturing method of semiconductor device
JP2005217295A (en) Manufacturing method of semiconductor device
JP2003332489A (en) Method and apparatus of manufacturing resin projection
TW488041B (en) An underfilling method of bonding gap between flip-chip and circuit board
EP1190448A1 (en) Chip package with molded underfill

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: TERAMIKROS, INC., JAPAN

Free format text: CHANGE OF OWNERSHIP BY CORPORATE SEPARATION;ASSIGNOR:CASIO COMPUTER CO., LTD.;REEL/FRAME:027465/0812

Effective date: 20111212

AS Assignment

Owner name: TERAMIKROS, INC., JAPAN

Free format text: CHANGE OF OWNERSHIP BY CORPORATE SEPARATION-TO CORRECT ASSIGNEE'S ADDRESS ON REEL 027465, FRAME 0812;ASSIGNOR:CASIO COMPUTER CO., LTD.;REEL/FRAME:027492/0449

Effective date: 20111212

AS Assignment

Owner name: TERA PROBE, INC., JAPAN

Free format text: MERGER;ASSIGNOR:TERAMIKROS, INC.;REEL/FRAME:040772/0440

Effective date: 20131001

AS Assignment

Owner name: AOI ELECTRONICS CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TERA PROBE, INC.;REEL/FRAME:041169/0952

Effective date: 20170124