FIG. 1 is a front, bottom and right side perspective view of a portion of semiconductor device, showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a top plan view thereof; a bottom plan view being a mirror image thereof;

FIG. 4 is a right side elevational view thereof; a left side elevational view being a mirror image thereof; and,

FIG. 5 is a rear elevational view thereof.

The broken line portions are shown for illustrative purpose only and form no part of the claimed design.