US9224637B1 - Bi-level dry etching scheme for transistor contacts - Google Patents
Bi-level dry etching scheme for transistor contacts Download PDFInfo
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- US9224637B1 US9224637B1 US14/468,893 US201414468893A US9224637B1 US 9224637 B1 US9224637 B1 US 9224637B1 US 201414468893 A US201414468893 A US 201414468893A US 9224637 B1 US9224637 B1 US 9224637B1
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- 238000001312 dry etching Methods 0.000 title 1
- 239000000463 material Substances 0.000 claims abstract description 53
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- 239000000758 substrate Substances 0.000 claims description 35
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 239000005368 silicate glass Substances 0.000 claims description 26
- 238000009413 insulation Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 230000000977 initiatory effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 21
- 230000015654 memory Effects 0.000 description 98
- 230000002093 peripheral effect Effects 0.000 description 9
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- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000003491 array Methods 0.000 description 7
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- 238000013500 data storage Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 208000033999 Device damage Diseases 0.000 description 1
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- 239000011370 conductive nanoparticle Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
Abstract
Description
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/468,893 US9224637B1 (en) | 2014-08-26 | 2014-08-26 | Bi-level dry etching scheme for transistor contacts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/468,893 US9224637B1 (en) | 2014-08-26 | 2014-08-26 | Bi-level dry etching scheme for transistor contacts |
Publications (1)
Publication Number | Publication Date |
---|---|
US9224637B1 true US9224637B1 (en) | 2015-12-29 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US14/468,893 Active US9224637B1 (en) | 2014-08-26 | 2014-08-26 | Bi-level dry etching scheme for transistor contacts |
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US (1) | US9224637B1 (en) |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5570315A (en) | 1993-09-21 | 1996-10-29 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
US5774397A (en) | 1993-06-29 | 1998-06-30 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state |
US5864153A (en) * | 1996-11-05 | 1999-01-26 | Sony Corporation | Capacitor structure of semiconductor memory cell and fabrication process thereof |
US5887145A (en) | 1993-09-01 | 1999-03-23 | Sandisk Corporation | Removable mother/daughter peripheral card |
US6011725A (en) | 1997-08-01 | 2000-01-04 | Saifun Semiconductors, Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6046935A (en) | 1996-03-18 | 2000-04-04 | Kabushiki Kaisha Toshiba | Semiconductor device and memory system |
US20050082602A1 (en) | 2003-10-20 | 2005-04-21 | Mutsumi Okajima | Semiconductor device and method of manufacturing the same |
US20060030109A1 (en) | 2004-08-04 | 2006-02-09 | Pushkar Ranade | Method to produce highly doped polysilicon thin films |
US20070012979A1 (en) | 2005-07-12 | 2007-01-18 | Samsung Electronics Co., Ltd. | NAND flash memory device and method of fabricating the same |
US20070057316A1 (en) | 2005-09-09 | 2007-03-15 | Toshitake Yaegashi | Semiconductor device and manufacturing method thereof |
US7232762B2 (en) * | 2004-06-16 | 2007-06-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an improved low power SRAM contact |
US20100314679A1 (en) | 2001-06-28 | 2010-12-16 | Samsung Electronics Co., Ltd. | Charge trapping nonvolatile memory devices with a high-k blocking insulation layer |
US7951669B2 (en) | 2006-04-13 | 2011-05-31 | Sandisk Corporation | Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element |
US20140054669A1 (en) | 2012-08-23 | 2014-02-27 | Jongsun Sel | Structures and Methods for Making NAND Flash Memory |
-
2014
- 2014-08-26 US US14/468,893 patent/US9224637B1/en active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5774397A (en) | 1993-06-29 | 1998-06-30 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state |
US5887145A (en) | 1993-09-01 | 1999-03-23 | Sandisk Corporation | Removable mother/daughter peripheral card |
US5570315A (en) | 1993-09-21 | 1996-10-29 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
US6046935A (en) | 1996-03-18 | 2000-04-04 | Kabushiki Kaisha Toshiba | Semiconductor device and memory system |
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
US5864153A (en) * | 1996-11-05 | 1999-01-26 | Sony Corporation | Capacitor structure of semiconductor memory cell and fabrication process thereof |
US6011725A (en) | 1997-08-01 | 2000-01-04 | Saifun Semiconductors, Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US20100314679A1 (en) | 2001-06-28 | 2010-12-16 | Samsung Electronics Co., Ltd. | Charge trapping nonvolatile memory devices with a high-k blocking insulation layer |
US20050082602A1 (en) | 2003-10-20 | 2005-04-21 | Mutsumi Okajima | Semiconductor device and method of manufacturing the same |
US7232762B2 (en) * | 2004-06-16 | 2007-06-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an improved low power SRAM contact |
US20060030109A1 (en) | 2004-08-04 | 2006-02-09 | Pushkar Ranade | Method to produce highly doped polysilicon thin films |
US20070012979A1 (en) | 2005-07-12 | 2007-01-18 | Samsung Electronics Co., Ltd. | NAND flash memory device and method of fabricating the same |
US20070057316A1 (en) | 2005-09-09 | 2007-03-15 | Toshitake Yaegashi | Semiconductor device and manufacturing method thereof |
US7951669B2 (en) | 2006-04-13 | 2011-05-31 | Sandisk Corporation | Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element |
US20140054669A1 (en) | 2012-08-23 | 2014-02-27 | Jongsun Sel | Structures and Methods for Making NAND Flash Memory |
Non-Patent Citations (1)
Title |
---|
Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545. |
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