US8716750B2 - Semiconductor device having epitaxial structures - Google Patents

Semiconductor device having epitaxial structures Download PDF

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US8716750B2
US8716750B2 US13/189,570 US201113189570A US8716750B2 US 8716750 B2 US8716750 B2 US 8716750B2 US 201113189570 A US201113189570 A US 201113189570A US 8716750 B2 US8716750 B2 US 8716750B2
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concentration
layer
epitaxial structures
semiconductor material
single layer
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US20130026538A1 (en
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Chin-I Liao
Teng-Chun Hsuan
I-Ming Lai
Chin-Cheng Chien
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United Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • the present invention relates to a semiconductor device having epitaxial structures, and more particularly, to a semiconductor device having an epitaxial source/drain.
  • Epitaxial structures are used in a wide variety of semiconductor applications.
  • the prior art usually forms an epitaxial layer such as a silicon germanium (hereinafter abbreviated as SiGe) layer in a single crystal substrate by performing a selective epitaxial growth (hereinafter abbreviated as SEG) method. Since the epitaxial layer has the crystalline orientation almost identical to the crystalline orientation of the substrate, the epitaxial layers serves as a raised source/drain or a recessed source/drain for the semiconductor device. Because the lattice constant of the epitaxial SiGe layer is larger than that of the silicon substrate, a strain stress is generated to the channel region of the meta-oxide semiconductor (MOS) transistor device. Accordingly, carrier mobility in the channel region is improved and the speed of the MOS transistor is increased.
  • MOS meta-oxide semiconductor
  • the epitaxial SiGe layer efficiently improves device performance, it increases complexity of the semiconductor fabrication and difficulties of the process control. For example, it is well-known that the stress is increased when the germanium concentration in the SiGe epitaxial structures is increased. However, the germanium concentration cannot be increased as expected: If the thickness of the epitaxial SiGe structure exceeds the critical thickness, it is relaxed and fails to cause stress to the channel region. Except the thickness issue, it is often found that agglomeration is formed by metal and germanium during the silicide process and causes serious junction leakage. Furthermore, the prior art also observes that because the lattice constants in the interface between the SiGe epitaxial structures and the silicon substrate are so different that the threshold voltage (hereinafter abbreviated as Vt) roll-off occurs.
  • Vt threshold voltage
  • the epitaxial structure is able to improve the device performance, it is always in need to improve the epitaxial structure itself.
  • a semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures.
  • the epitaxial structure includes a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant.
  • the second lattice constant is larger than the first lattice constant.
  • the undoped cap layer includes the first semiconductor material and the second semiconductor material.
  • the second semiconductor material in the epitaxial structures has a first concentration
  • the second semiconductor material in the undoped cap layer has a second concentration
  • the second concentration is lower than the first concentration.
  • a semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, a pair of recesses formed in the substrate respectively at two sides of the gate structure, epitaxial structures respectively formed in recesses at the two sides of the gate structure, and an undoped under layer formed in the recesses and in between the epitaxial structure and the substrate.
  • the epitaxial structures include a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant.
  • the second lattice constant is larger than the first lattice constant.
  • the undoped under layer covers sidewalls and a bottom of the recess and has the first semiconductor material and the second semiconductor material.
  • the second semiconductor material in the epitaxial structures has a first concentration
  • the second semiconductor material in the undoped under layer has a second concentration
  • the second concentration is lower than the first concentration.
  • the epitaxial structures serving as the source/drain of the semiconductor device includes the undoped cap layer with lower Ge concentration formed on the surface of the epitaxial structures, therefore the agglomeration formed by the metal and Ge in the silicide process and the junction leakage are both prevented. Furthermore, the semiconductor device having epitaxial structures provided by the present invention also includes the undoped under layer with lower Ge concentration formed in the recess and in between the epitaxial structure and the substrate, therefore the Vt roll-off issue, which is caused by the lattice constant difference between the SiGe epitaxial structure and the silicon substrate, is mitigated.
  • FIG. 1 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a first preferred embodiment of the present invention.
  • FIG. 2 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a second preferred embodiment of the present invention.
  • FIG. 3 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a third preferred embodiment of the present invention.
  • FIG. 4 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a fourth preferred embodiment of the present invention.
  • FIG. 5 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a fifth preferred embodiment of the present invention.
  • FIG. 1 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a first preferred embodiment of the present invention.
  • a semiconductor device 100 having epitaxial structures provided by the preferred embodiment includes a substrate 102 and a gate structure 110 formed on the substrate 102 .
  • the gate structure 110 includes a gate insulating layer 112 , and the gate insulating layer 112 can include high dielectric constant (high-k) material or silicon oxide.
  • the gate structure 110 also includes a gate electrode 114 defined by a patterned hard mask 116 .
  • the gate electrode 114 can include metal or polysilicon.
  • the semiconductor device 100 also includes lightly-doped drains (LDDs) 118 formed in the substrate 102 at two sides of the gate structure 110 , a spacer 120 formed on sidewalls of the gate structure 110 , and a pair of recesses 122 formed in the substrate 102 respectively at the two sides of the gate structure 110 , particularly at two sides of the spacer 120 .
  • LDDs lightly-doped drains
  • the semiconductor device 100 After performing a cleaning process to remove native oxides or other contaminants from the substrate 102 , a SEG method is performed to form an epitaxial structure 130 respectively in the recess 122 .
  • the semiconductor device 100 provided by the preferred embodiment also includes epitaxial structures 130 positioned in the substrate 102 respectively at the two sides of the gate structure 110 , particularly in the recess 122 at the two sides of gate structure 110 .
  • the epitaxial structure 130 includes a first semiconductor material and a second semiconductor material.
  • the first semiconductor material has a first lattice constant while the second semiconductor material has a second lattice constant, and the second lattice constant is larger than the first lattice constant.
  • the first semiconductor material includes Si and the second semiconductor material includes Ge. That means the epitaxial structure 130 includes SiGe, but not limited to this.
  • a concentration of the second semiconductor material that is the Ge concentration, is exemplarily but not limited to about 36% in the preferred embodiment. Because the lattice constant of SiGe is larger than that of the substrate, the epitaxial SiGe structure serves as a strained-silicon structure and causes changes to band structure. Therefore the carrier mobility in the channel region is increased and the performance of the semiconductor device 100 is consequently improved.
  • a surface of the epitaxial structures 130 and a surface of the substrate 102 are not coplanar. In detail, the surface of the epitaxial structure 130 is higher than the surface of the substrate 102 .
  • ion implantation can be performed before or after forming the epitaxial structures 130 , or during forming the epitaxial structures 130 .
  • dopants required by different conductivity types of the semiconductor device 100 are implanted into the epitaxial structures 130 .
  • the implanted epitaxial structures 130 include the required p-type or n-type dopant and serve as a source/drain of the semiconductor device 100 . Because the ion implantation and choices of the dopant are well-known to those skilled in the art, the details are omitted herein in the interest of brevity.
  • a cap layer can be formed on the surface of the epitaxial structure 130 .
  • a pure silicon cap layer (not shown) can be formed on the epitaxial structures 130 for serving as a reacting subject in the silicide process.
  • the Ge concentration in the pure silicon cap layer is 0%, which is distinctly different from the Ge concentration in the epitaxial structures 130 (36%), it is found that the pure silicon cap layer obtains a wavy surface.
  • an atomic force microscope hereinafter abbreviated as AFM
  • RMS root mean square
  • the preferred embodiment provides a not pure silicon undoped cap layer 140 formed on the epitaxial structures 130 .
  • the undoped cap layer 140 includes the first semiconductor material and the second semiconductor material as mentioned above, that is SiGe. According to the preferred embodiment, the undoped cap layer 140 is a single layer as shown in FIG. 1 .
  • a concentration of the second semiconductor material in the undoped cap layer 140 is lower than the Ge concentration in the epitaxial structures 130 , and is exemplarily about 25%.
  • a thickness of the undoped cap layer 140 is, exemplarily but not limited to, 150 angstroms ( ⁇ ) in the preferred embodiment.
  • the semiconductor device 100 provided by the preferred embodiment can further include an undoped under layer 150 positioned in the recess 122 and in between the epitaxial structure 130 and the substrate 102 .
  • the undoped under layer 150 covers sidewalls and a bottom of the recess 122 .
  • the undoped under layer 150 can be a single layer or multi-layer and includes the abovementioned first semiconductor material and second semiconductor material. That means the undoped under layer 150 include SiGe.
  • the second semiconductor material in the undoped under layer 150 has a concentration lower than the Ge concentration in the epitaxial structures 130 , and is between 10% and 25%. More important, the concentration of the second semiconductor material in the undoped under layer 150 is upwardly increased. It is noteworthy that details about the undoped under layer 150 will be described in the following preferred embodiments, therefore those details are omitted herein for simplicity.
  • the not pure silicon undoped cap layer 140 is formed on the surface of the epitaxial structures 130 .
  • the undoped cap layer 140 includes SiGe and the Ge concentration is preferably about 25%. Since the Ge concentration in the undoped cap layer 140 is about 25% and the Ge concentration in the epitaxial structures 130 is about 36%, the difference between the two Ge concentrations are much less. Consequently, the undoped cap layer 140 formed on the surface of the epitaxial structures 130 obtains a smooth surface, and an AFM measured RMS roughness of the undoped cap layer 140 is about 0.75 nm.
  • FIG. 2 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a second preferred embodiment of the present invention. It is noteworthy that elements the same in the first and second preferred embodiments are depicted by the same numerals.
  • a semiconductor device 100 having epitaxial structures provided by the preferred embodiment includes a substrate 102 and a gate structure 110 formed on the substrate 102 .
  • the gate structure 110 includes a gate insulating layer 112 , and the gate insulating layer 112 can include high-k material or silicon oxide.
  • the gate structure 110 also includes a gate electrode 114 defined by a patterned hard mask 116 .
  • the gate electrode 114 can include metal or polysilicon.
  • the semiconductor device 100 also includes LDDs 118 formed in the substrate 102 at two sides of the gate structure 110 , a spacer 120 formed on sidewalls of the gate structure 110 , and a pair of recesses 122 formed in the substrate 102 respectively at the two sides of the gate structure 110 , particularly at two sides of the spacer 120 .
  • the semiconductor device 100 provided by the preferred embodiment also includes epitaxial structures 130 positioned in the substrate 102 respectively at the two sides of the gate structure 110 , particularly in the recess 122 at the two sides of gate structure 110 .
  • the epitaxial structure 130 includes a first semiconductor material and a second semiconductor material.
  • the first semiconductor material has a first lattice constant while the second semiconductor material has a second lattice constant, and the second lattice constant is larger than the first lattice constant.
  • the first semiconductor material includes Si and the second semiconductor material includes Ge. That means the epitaxial structure 130 includes SiGe, but not limited to this.
  • a concentration of the second semiconductor material that is the Ge concentration, is exemplarily but not limited to, about 36% in the preferred embodiment.
  • a surface of the epitaxial structures 130 is higher than a surface of the substrate 102 .
  • the preferred embodiment provides an undoped cap layer 140 formed on the epitaxial structures 130 .
  • the undoped cap layer 140 provided by the preferred embodiment includes at least a first single layer 140 a and a second single layer 140 b as shown in FIG. 2 , and the first single layer 140 a is formed between the second single layer 140 b and the epitaxial structure 130 .
  • the undoped cap layer 140 (including the first single layer 140 a and the second single layer 140 b ) includes the first semiconductor material and the second semiconductor material as mentioned above, that is SiGe.
  • Ge in the first single layer 140 a has a first concentration
  • Ge in the second single layer 140 b has a second concentration
  • the first concentration and the second concentration are all lower than the Ge concentration in the epitaxial structures 130
  • the second concentration is lower than the first concentration.
  • the first concentration is preferably about 25% and the second concentration is preferably about 0%.
  • the second preferred embodiment provides a multilayered cap layer 140 having Ge concentration upwardly decreased.
  • a thickness of the undoped cap layer 140 is, exemplarily but not limited to, 150 ⁇ in the preferred embodiment. It is also noteworthy that a thickness of the first single layer 140 a and a thickness of the second single layer 140 b have a ratio, and the ratio is about 1:2 according to the preferred embodiment.
  • the semiconductor device 100 provided by the preferred embodiment can also include an undoped under layer 150 . Since details about the undoped under layer 150 will be described in the following preferred embodiments, therefore those details are omitted herein for simplicity.
  • the multilayered cap layer 140 is formed on the surface of the epitaxial structures 130 .
  • the multilayered cap layer 140 includes the first single layer 140 a and the second single layer 140 b .
  • Both the first single layer 140 a and the second single layer 140 b include SiGe and the Ge concentration in the first single layer 140 a is preferably about 25% while the Ge concentration in the second single layer 140 b is preferably about 0%.
  • a thickness of the second single layer 140 b is larger than a thickness of the first single layer 140 a . That means the multilayered cap layer 140 has the Ge concentration upwardly decreased.
  • the first single layer 140 a (Ge concentration of about 25%) is form between the second single layer 140 b (Ge concentration of about 0%) and the epitaxial structure 130 (Ge concentration of about 36%), the first single layer 140 a serves as a buffer layer between the second single layer 140 b and the epitaxial structure 130 . Consequently, the multilayered cap layer 140 formed on the surface of the epitaxial structures 130 obtains a smoother surface, and an AFM measured RMS roughness of the multilayered cap layer 140 is about 0.76 nm. Compared with the RMS roughness of the pure silicon cap layer, that is 4.21 nm, it is concluded that the surface roughness is substantially improved. Furthermore, since the Ge concentration of the second single layer 140 b in the multilayered cap layer 140 is 0%, the second single layer 140 b serves as the reacting subject in the silicide process. Thus the agglomeration problem in the silicide process is prevented.
  • FIG. 3 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a third preferred embodiment of the present invention. It is noteworthy that elements the same in the first and third preferred embodiments such as the substrate 102 , the gate structure 110 , the LDDs 118 , the spacer 120 , the recesses 122 , and the epitaxial structures 130 formed in the recesses 122 are depicted by the same numerals, and those details are omitted herein for simplicity. Please still refer to FIG. 3 .
  • the semiconductor device 100 provided by the preferred embodiment also includes the SiGe epitaxial structures 130 , and the concentration of the second semiconductor material, that is the Ge concentration, is exemplarily but not limited to 36% in the preferred embodiment. In addition, a surface of the epitaxial structures 130 is higher than a surface of the substrate 102 as shown in FIG. 3 .
  • the preferred embodiment provides an undoped cap layer 140 formed on the epitaxial structures 130 .
  • the undoped cap layer 140 provided by the preferred embodiment is a multilayered cap layer 140 as shown in FIG. 3 .
  • the undoped cap layer 140 includes at least a first single layer 140 a , a second single layer 140 b and a third single layer 140 c .
  • the first single layer 140 a and the third single layer 140 c are formed between the second single layer 140 b and the epitaxial structure 130
  • the third single layer 140 c is formed between the first single layer 140 a and the second single layer 140 b .
  • the undoped cap layer 140 (including the first single layer 140 a , the second single layer 140 b and the third single layer 140 c ) includes the first semiconductor material and the second semiconductor material as mentioned above, that is SiGe.
  • Ge in the first single layer 140 a has a first concentration
  • Ge in the second single layer 140 b has a second concentration
  • Ge in the third single layer 140 c has a third concentration.
  • the first concentration, the second concentration, and the third concentration are all lower than the Ge concentration in the epitaxial structures 130 .
  • the first concentration is preferably about 25%
  • the second concentration is preferably about 0%
  • the third concentration is between the first concentration and the second concentration, preferably but not limited to about 10%.
  • the second preferred embodiment provides a multilayered cap layer 140 has the Ge concentration upwardly decreased.
  • a thickness of the undoped cap layer 140 is, exemplarily but not limited to, 150 ⁇ in the preferred embodiment. It is also noteworthy that a thickness of the first single layer 140 a , a thickness of the second single layer 140 b , and a thickness of the third single layer 140 c have a ratio, and the ratio is about 1:1:1 according to the preferred embodiment.
  • the semiconductor device 100 provided by the preferred embodiment can also include an undoped under layer 150 . Since details about the undoped under layer 150 will be described in the following preferred embodiments, therefore those details are omitted herein for simplicity.
  • the multilayered cap layer 140 is formed on the surface of the epitaxial structures 130 .
  • the multilayered cap layer 140 upwardly includes the first single layer 140 a , the third single layer 140 c , and the second single layer 140 b . All of the first single layer 140 a , the third single layer 140 c , and the second single layer 140 b include SiGe.
  • the Ge concentration in the first single layer 140 a is preferably about 25%
  • the Ge concentration in third single layer 140 c is preferably about 10%
  • the Ge concentration in the second single layer 140 b is preferably about 0%.
  • first single layer 140 a , the third single layer 140 c , and second single layer 140 b are substantially identical. That means the multilayered cap layer 140 has the Ge concentration upwardly decreased. Since the first single layer 140 a (Ge concentration of about 25%) and the third single layer 140 c (Ge concentration of about 10%) are formed between the second single layer 140 b (Ge concentration of about 0%) and the epitaxial structure 130 (Ge concentration of about 36%), the first single layer 140 a and the third single layer 140 c serve as buffer layers between the second single layer 140 b and the epitaxial structure 130 . Because the two single layers having upwardly decreased concentration are formed between the second single layer 140 b and the epitaxial structure 130 , the concentration gradient is flatter.
  • the cap layer 140 formed on the surface of the epitaxial structures 130 obtains a much smoother surface, and an AFM measured RMS roughness of the cap layer 140 is about 0.65 nm. Compared with the RMS roughness of the pure silicon cap layer, that is 4.21 nm, it is concluded that the surface roughness is much improved. Furthermore, since the Ge concentration of the second single layer 140 b in the undoped cap layer 140 is 0%, the second single layer 140 b serves as the reacting subject in the silicide process. Thus the agglomeration problem in the silicide process is prevented.
  • FIGS. 4-5 are schematic drawings respectively illustrating a semiconductor device having epitaxial structures provided by a fourth and fifth preferred embodiments of the present invention. It is noteworthy that elements the same in the first and fourth and fifth preferred embodiments such as the substrate 102 , the gate structure 110 , the LDDs 118 , the spacer 120 , the recesses 122 , and the epitaxial structures 130 formed in the recesses 122 are depicted by the same numerals, and those details are omitted herein for simplicity.
  • the fourth preferred embodiment provides an undoped under layer 150 (that is the under layer 150 mentioned in the first, second and third preferred embodiments) formed in the recesses 122 .
  • the undoped under layer 150 is formed between the epitaxial structure 130 and the substrate 102 and covers sidewalls and a bottom of the recess 122 .
  • the undoped under layer 150 includes the first semiconductor material and the second semiconductor material. In other words, the undoped under layer 150 includes SiGe.
  • the preferred embodiment provides a single undoped under layer 150 , and a Ge concentration of the undoped under layer 150 is lower than the Ge concentration of the epitaxial structures 130 , exemplarily is about 25%.
  • the undoped under layer 150 is provided to solve the problem that the lattice constant of the epitaxial structure 130 is distinctly different from that of the substrate 102 , the undoped under layer 150 covering the bottom of the recess 122 cannot be formed so thick that the undoped under layer 150 occupies the space for forming the epitaxial structures 130 , and thus reduces the strain stress provided to the channel region. Accordingly, a thickness of the undoped under layer 150 covering the sidewalls of the recess 122 and the thickness of the undoped under layer 150 covering the bottom of the recess 122 have a ratio and the ratio is about 1:1 in the preferred embodiment.
  • the undoped under layer 150 having Ge concentration of about 25% is formed in a process pressure of about 50 Torr, a ratio of the thickness of the single under layer 150 covering the sidewalls of the recess 122 and the thickness of the single under layer 150 covering the bottom of the recess 122 is about 1:2. Consequently, the space for forming the epitaxial structure 130 is reduced. Therefore the preferred embodiment forms the single under layer 150 in a process pressure of about 10 Torr. Accordingly, the thickness of the single under layer 150 covering the sidewalls of the recess 122 and the thickness of the single under layer 150 covering the bottom of the recess 122 approaches the expected ratio: 1:1.
  • the single under layer 150 is formed in between the epitaxial structure 130 and the substrate 102 .
  • the single under layer 150 includes SiGe and the Ge concentration in the single under layer 150 is preferably about 25%. Since the single under layer 150 (Ge concentration of about 25%) is form between the substrate 102 (Ge concentration of about 0%) and the epitaxial structure 130 (Ge concentration of about 36%), the single under layer 150 serves as a buffer layer between the substrate 102 and the epitaxial structure 130 . And thus the Vt roll-off problem caused by the distinctive difference between the lattice constant of the epitaxial structures 130 and that of the substrate 102 is mitigated.
  • the single under layer 150 is formed not to occupy the precious space used to form the epitaxial structure 130 .
  • the single under layer 150 provided by the preferred embodiment is able to solve the Vt roll-off problem without rendering impact to the strain stress.
  • FIG. 5 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a fifth preferred embodiment of the present invention.
  • the fifth preferred embodiment provides an undoped under layer 150 (that is the undoped under layer 150 mentioned in the first, second and third preferred embodiments) formed in the recesses 122 .
  • the undoped under layer 150 is formed between the epitaxial structure 130 and the substrate 102 and covers sidewalls and a bottom of the recess 122 .
  • the undoped under layer 150 includes the first semiconductor material and the second semiconductor material.
  • the undoped under layer 150 includes SiGe.
  • the undoped under layer 150 is a multilayered under layer upwardly including a first single layer 150 a , a second single layer 150 b , and a third single layer 150 c .
  • Ge in the first single layer 150 a has a first concentration
  • Ge in second single layer 150 b has a second concentration
  • Ge in the third single layer 150 c has a third concentration.
  • the first concentration, the second concentration, and the third concentration are all lower than the Ge concentration of the epitaxial structures 130 .
  • the third concentration is larger than the second concentration and the second concentration is larger than the first concentration.
  • the first concentration is about 10%
  • the second concentration is about 17%
  • the third concentration is about 25%.
  • the Ge concentration of the multilayered under layer 150 provided by the preferred embodiment is upwardly increased.
  • a thickness of the first single layer 150 a , a thickness of the second single layer 150 b , and a thickness of the third single layer 150 c have a ratio, and the ratio is between 1:1:1 and 1:1:2. It is noteworthy that with increase of the Ge concentration in the first single layer 150 a , the second single layer 150 b , and the third single layer 150 c , the ratio of the thickness of the multilayered under layer 150 covering the sidewalls of the recess 122 and the thickness of the multilayered under layer 150 covering the bottom of the recess 122 is getting near to 1:1.
  • the multilayered under layer 150 is formed in between the epitaxial structure 130 and the substrate 102 .
  • the multilayered under layer 150 includes the first single layer 150 a , the second single layer 150 b , and the third single layer 150 c .
  • the first single layer 150 a , the second single layer 150 b and the third single layer 150 c all include SiGe.
  • the Ge concentrations in the first single layer 150 a , in the second single under layer 150 b and in the third single layer 150 c is increased from 10%, to 17%, and to 25%.
  • the multilayered under layer 150 serves as a buffer layer between the substrate 102 (having the Ge concentration of 0%) and the epitaxial structure 130 (having the Ge concentration of 36%). Because the three single layers having upwardly increased Ge concentration are formed between the substrate 102 and the epitaxial structure 130 , the concentration gradient is flatter. Consequently, the Vt roll-off problem caused by the distinctive difference between the lattice constant of the epitaxial structures 130 and that of the substrate 102 140 b is mitigated.
  • the multilayered under layer 150 is formed not to occupy the precious space used to form the epitaxial structures 130 .
  • the multilayered under layer 150 provided by the preferred embodiment is able to solve the Vt roll-off problem without rendering impact to the strain stress.
  • the undoped under layer 150 provided by the fourth and fifth preferred embodiments of the present invention and the undoped cap layer 140 provided by the first, second, and third preferred embodiments can be formed in different combination in order to improve the semiconductor device 100 having the epitaxial structures 130 .
  • the epitaxial structures serving as the source/drain of the semiconductor device includes the undoped cap layer with lower Ge concentration formed on the surface of the epitaxial structures, therefore the agglomeration between the metals and Ge in the silicide process and the junction leakage are both prevented. Furthermore, the semiconductor device having epitaxial structures provided by the present invention also includes the undoped under layer with lower Ge concentration formed in the recess and in between the epitaxial structure and the substrate, therefore the Vt roll-off issue, which is caused by lattice constant difference between the SiGe epitaxial structure and the silicon substrate, is mitigated.

Abstract

A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having epitaxial structures, and more particularly, to a semiconductor device having an epitaxial source/drain.
2. Description of the Prior Art
Epitaxial structures are used in a wide variety of semiconductor applications. For example, the prior art usually forms an epitaxial layer such as a silicon germanium (hereinafter abbreviated as SiGe) layer in a single crystal substrate by performing a selective epitaxial growth (hereinafter abbreviated as SEG) method. Since the epitaxial layer has the crystalline orientation almost identical to the crystalline orientation of the substrate, the epitaxial layers serves as a raised source/drain or a recessed source/drain for the semiconductor device. Because the lattice constant of the epitaxial SiGe layer is larger than that of the silicon substrate, a strain stress is generated to the channel region of the meta-oxide semiconductor (MOS) transistor device. Accordingly, carrier mobility in the channel region is improved and the speed of the MOS transistor is increased.
Although the epitaxial SiGe layer efficiently improves device performance, it increases complexity of the semiconductor fabrication and difficulties of the process control. For example, it is well-known that the stress is increased when the germanium concentration in the SiGe epitaxial structures is increased. However, the germanium concentration cannot be increased as expected: If the thickness of the epitaxial SiGe structure exceeds the critical thickness, it is relaxed and fails to cause stress to the channel region. Except the thickness issue, it is often found that agglomeration is formed by metal and germanium during the silicide process and causes serious junction leakage. Furthermore, the prior art also observes that because the lattice constants in the interface between the SiGe epitaxial structures and the silicon substrate are so different that the threshold voltage (hereinafter abbreviated as Vt) roll-off occurs.
Accordingly, though the epitaxial structure is able to improve the device performance, it is always in need to improve the epitaxial structure itself.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, a semiconductor device having epitaxial structures is provided. The semiconductor device includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structure includes a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant. The second lattice constant is larger than the first lattice constant. The undoped cap layer includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures has a first concentration, the second semiconductor material in the undoped cap layer has a second concentration, and the second concentration is lower than the first concentration.
According to another aspect of the present invention, a semiconductor device having epitaxial structures is provided. The semiconductor device includes a gate structure positioned on a substrate, a pair of recesses formed in the substrate respectively at two sides of the gate structure, epitaxial structures respectively formed in recesses at the two sides of the gate structure, and an undoped under layer formed in the recesses and in between the epitaxial structure and the substrate. The epitaxial structures include a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant. The second lattice constant is larger than the first lattice constant. The undoped under layer covers sidewalls and a bottom of the recess and has the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures has a first concentration, the second semiconductor material in the undoped under layer has a second concentration, and the second concentration is lower than the first concentration.
According to the semiconductor device having epitaxial structures provided by the present invention, the epitaxial structures serving as the source/drain of the semiconductor device includes the undoped cap layer with lower Ge concentration formed on the surface of the epitaxial structures, therefore the agglomeration formed by the metal and Ge in the silicide process and the junction leakage are both prevented. Furthermore, the semiconductor device having epitaxial structures provided by the present invention also includes the undoped under layer with lower Ge concentration formed in the recess and in between the epitaxial structure and the substrate, therefore the Vt roll-off issue, which is caused by the lattice constant difference between the SiGe epitaxial structure and the silicon substrate, is mitigated.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a first preferred embodiment of the present invention.
FIG. 2 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a second preferred embodiment of the present invention.
FIG. 3 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a third preferred embodiment of the present invention.
FIG. 4 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a fourth preferred embodiment of the present invention.
FIG. 5 is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a fifth preferred embodiment of the present invention.
 DETAILED DESCRIPTION
Please refer to FIG. 1, which is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a first preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor device 100 having epitaxial structures provided by the preferred embodiment includes a substrate 102 and a gate structure 110 formed on the substrate 102. The gate structure 110 includes a gate insulating layer 112, and the gate insulating layer 112 can include high dielectric constant (high-k) material or silicon oxide. The gate structure 110 also includes a gate electrode 114 defined by a patterned hard mask 116. The gate electrode 114 can include metal or polysilicon. The semiconductor device 100 also includes lightly-doped drains (LDDs) 118 formed in the substrate 102 at two sides of the gate structure 110, a spacer 120 formed on sidewalls of the gate structure 110, and a pair of recesses 122 formed in the substrate 102 respectively at the two sides of the gate structure 110, particularly at two sides of the spacer 120.
Please still refer to FIG. 1. After performing a cleaning process to remove native oxides or other contaminants from the substrate 102, a SEG method is performed to form an epitaxial structure 130 respectively in the recess 122. In other words, the semiconductor device 100 provided by the preferred embodiment also includes epitaxial structures 130 positioned in the substrate 102 respectively at the two sides of the gate structure 110, particularly in the recess 122 at the two sides of gate structure 110. The epitaxial structure 130 includes a first semiconductor material and a second semiconductor material. The first semiconductor material has a first lattice constant while the second semiconductor material has a second lattice constant, and the second lattice constant is larger than the first lattice constant. In the preferred embodiment, the first semiconductor material includes Si and the second semiconductor material includes Ge. That means the epitaxial structure 130 includes SiGe, but not limited to this. In addition, a concentration of the second semiconductor material, that is the Ge concentration, is exemplarily but not limited to about 36% in the preferred embodiment. Because the lattice constant of SiGe is larger than that of the substrate, the epitaxial SiGe structure serves as a strained-silicon structure and causes changes to band structure. Therefore the carrier mobility in the channel region is increased and the performance of the semiconductor device 100 is consequently improved. As shown in FIG. 1, a surface of the epitaxial structures 130 and a surface of the substrate 102 are not coplanar. In detail, the surface of the epitaxial structure 130 is higher than the surface of the substrate 102.
Furthermore, ion implantation can be performed before or after forming the epitaxial structures 130, or during forming the epitaxial structures 130. Thus dopants required by different conductivity types of the semiconductor device 100 are implanted into the epitaxial structures 130. Accordingly, the implanted epitaxial structures 130 include the required p-type or n-type dopant and serve as a source/drain of the semiconductor device 100. Because the ion implantation and choices of the dopant are well-known to those skilled in the art, the details are omitted herein in the interest of brevity.
As mentioned above, to prevent the epitaxial structure 130 from agglomeration formed by metals and Ge in the silicide process, a cap layer can be formed on the surface of the epitaxial structure 130. For example, a pure silicon cap layer (not shown) can be formed on the epitaxial structures 130 for serving as a reacting subject in the silicide process. However, since the Ge concentration in the pure silicon cap layer is 0%, which is distinctly different from the Ge concentration in the epitaxial structures 130 (36%), it is found that the pure silicon cap layer obtains a wavy surface. In detail, an atomic force microscope (hereinafter abbreviated as AFM) measured root mean square (hereinafter abbreviated as RMS) roughness of the pure silicon cap layer is about 4.21 nanometer (hereinafter abbreviated as nm). This wavy/rough surface renders adverse impact to the following processes, even to the strain stress provided by the epitaxial structures 130.
It is therefore assumed that the undesirable agglomeration problem occurs when the epitaxial structures 130 is provided without the pure silicon cap layer, however the epitaxial structures 130 with the pure silicon cap layer having Ge concentration distinctly different from the Ge concentration in the epitaxial structures 130 results in the wavy surface. As a countermeasure against to the dilemmatic problem, the preferred embodiment provides a not pure silicon undoped cap layer 140 formed on the epitaxial structures 130. The undoped cap layer 140 includes the first semiconductor material and the second semiconductor material as mentioned above, that is SiGe. According to the preferred embodiment, the undoped cap layer 140 is a single layer as shown in FIG. 1. A concentration of the second semiconductor material in the undoped cap layer 140, that is the Ge concentration, is lower than the Ge concentration in the epitaxial structures 130, and is exemplarily about 25%. In addition, a thickness of the undoped cap layer 140 is, exemplarily but not limited to, 150 angstroms (Å) in the preferred embodiment.
In addition, the semiconductor device 100 provided by the preferred embodiment can further include an undoped under layer 150 positioned in the recess 122 and in between the epitaxial structure 130 and the substrate 102. The undoped under layer 150 covers sidewalls and a bottom of the recess 122. The undoped under layer 150 can be a single layer or multi-layer and includes the abovementioned first semiconductor material and second semiconductor material. That means the undoped under layer 150 include SiGe. The second semiconductor material in the undoped under layer 150 has a concentration lower than the Ge concentration in the epitaxial structures 130, and is between 10% and 25%. More important, the concentration of the second semiconductor material in the undoped under layer 150 is upwardly increased. It is noteworthy that details about the undoped under layer 150 will be described in the following preferred embodiments, therefore those details are omitted herein for simplicity.
According to the semiconductor device 100 having epitaxial structures provided by the first preferred embodiment, the not pure silicon undoped cap layer 140 is formed on the surface of the epitaxial structures 130. The undoped cap layer 140 includes SiGe and the Ge concentration is preferably about 25%. Since the Ge concentration in the undoped cap layer 140 is about 25% and the Ge concentration in the epitaxial structures 130 is about 36%, the difference between the two Ge concentrations are much less. Consequently, the undoped cap layer 140 formed on the surface of the epitaxial structures 130 obtains a smooth surface, and an AFM measured RMS roughness of the undoped cap layer 140 is about 0.75 nm. Compared with the RMS roughness of the pure silicon cap layer, that is 4.21 nm, it is concluded that the surface roughness is substantially improved. Furthermore, since the Ge concentration in the undoped cap layer 140 is lower, the agglomeration problem in the silicide process is mitigated.
Please refer to FIG. 2, which is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a second preferred embodiment of the present invention. It is noteworthy that elements the same in the first and second preferred embodiments are depicted by the same numerals. As shown in FIG. 2, a semiconductor device 100 having epitaxial structures provided by the preferred embodiment includes a substrate 102 and a gate structure 110 formed on the substrate 102. The gate structure 110 includes a gate insulating layer 112, and the gate insulating layer 112 can include high-k material or silicon oxide. The gate structure 110 also includes a gate electrode 114 defined by a patterned hard mask 116. The gate electrode 114 can include metal or polysilicon. The semiconductor device 100 also includes LDDs 118 formed in the substrate 102 at two sides of the gate structure 110, a spacer 120 formed on sidewalls of the gate structure 110, and a pair of recesses 122 formed in the substrate 102 respectively at the two sides of the gate structure 110, particularly at two sides of the spacer 120.
Please still refer to FIG. 2. The semiconductor device 100 provided by the preferred embodiment also includes epitaxial structures 130 positioned in the substrate 102 respectively at the two sides of the gate structure 110, particularly in the recess 122 at the two sides of gate structure 110. The epitaxial structure 130 includes a first semiconductor material and a second semiconductor material. The first semiconductor material has a first lattice constant while the second semiconductor material has a second lattice constant, and the second lattice constant is larger than the first lattice constant. In the preferred embodiment, the first semiconductor material includes Si and the second semiconductor material includes Ge. That means the epitaxial structure 130 includes SiGe, but not limited to this. In addition, a concentration of the second semiconductor material, that is the Ge concentration, is exemplarily but not limited to, about 36% in the preferred embodiment. As shown in FIG. 2, a surface of the epitaxial structures 130 is higher than a surface of the substrate 102.
As mentioned above, to solve the dilemmatic problem, the preferred embodiment provides an undoped cap layer 140 formed on the epitaxial structures 130. It is noteworthy that the undoped cap layer 140 provided by the preferred embodiment includes at least a first single layer 140 a and a second single layer 140 b as shown in FIG. 2, and the first single layer 140 a is formed between the second single layer 140 b and the epitaxial structure 130. The undoped cap layer 140 (including the first single layer 140 a and the second single layer 140 b) includes the first semiconductor material and the second semiconductor material as mentioned above, that is SiGe. According to the preferred embodiment, Ge in the first single layer 140 a has a first concentration, Ge in the second single layer 140 b has a second concentration, the first concentration and the second concentration are all lower than the Ge concentration in the epitaxial structures 130, and the second concentration is lower than the first concentration. In the preferred embodiment, the first concentration is preferably about 25% and the second concentration is preferably about 0%. In other words, the second preferred embodiment provides a multilayered cap layer 140 having Ge concentration upwardly decreased. In addition, a thickness of the undoped cap layer 140 is, exemplarily but not limited to, 150 Å in the preferred embodiment. It is also noteworthy that a thickness of the first single layer 140 a and a thickness of the second single layer 140 b have a ratio, and the ratio is about 1:2 according to the preferred embodiment.
As mentioned above, the semiconductor device 100 provided by the preferred embodiment can also include an undoped under layer 150. Since details about the undoped under layer 150 will be described in the following preferred embodiments, therefore those details are omitted herein for simplicity.
According to the semiconductor device 100 having epitaxial structures provided by the second preferred embodiment, the multilayered cap layer 140 is formed on the surface of the epitaxial structures 130. The multilayered cap layer 140 includes the first single layer 140 a and the second single layer 140 b. Both the first single layer 140 a and the second single layer 140 b include SiGe and the Ge concentration in the first single layer 140 a is preferably about 25% while the Ge concentration in the second single layer 140 b is preferably about 0%. In addition, a thickness of the second single layer 140 b is larger than a thickness of the first single layer 140 a. That means the multilayered cap layer 140 has the Ge concentration upwardly decreased. Since the first single layer 140 a (Ge concentration of about 25%) is form between the second single layer 140 b (Ge concentration of about 0%) and the epitaxial structure 130 (Ge concentration of about 36%), the first single layer 140 a serves as a buffer layer between the second single layer 140 b and the epitaxial structure 130. Consequently, the multilayered cap layer 140 formed on the surface of the epitaxial structures 130 obtains a smoother surface, and an AFM measured RMS roughness of the multilayered cap layer 140 is about 0.76 nm. Compared with the RMS roughness of the pure silicon cap layer, that is 4.21 nm, it is concluded that the surface roughness is substantially improved. Furthermore, since the Ge concentration of the second single layer 140 b in the multilayered cap layer 140 is 0%, the second single layer 140 b serves as the reacting subject in the silicide process. Thus the agglomeration problem in the silicide process is prevented.
Please refer to FIG. 3, which is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a third preferred embodiment of the present invention. It is noteworthy that elements the same in the first and third preferred embodiments such as the substrate 102, the gate structure 110, the LDDs 118, the spacer 120, the recesses 122, and the epitaxial structures 130 formed in the recesses 122 are depicted by the same numerals, and those details are omitted herein for simplicity. Please still refer to FIG. 3. The semiconductor device 100 provided by the preferred embodiment also includes the SiGe epitaxial structures 130, and the concentration of the second semiconductor material, that is the Ge concentration, is exemplarily but not limited to 36% in the preferred embodiment. In addition, a surface of the epitaxial structures 130 is higher than a surface of the substrate 102 as shown in FIG. 3.
As mentioned above, to solve the dilemmatic problem, the preferred embodiment provides an undoped cap layer 140 formed on the epitaxial structures 130. It is noteworthy that the undoped cap layer 140 provided by the preferred embodiment is a multilayered cap layer 140 as shown in FIG. 3. The undoped cap layer 140 includes at least a first single layer 140 a, a second single layer 140 b and a third single layer 140 c. As shown in FIG. 3, the first single layer 140 a and the third single layer 140 c are formed between the second single layer 140 b and the epitaxial structure 130, while the third single layer 140 c is formed between the first single layer 140 a and the second single layer 140 b. The undoped cap layer 140 (including the first single layer 140 a, the second single layer 140 b and the third single layer 140 c) includes the first semiconductor material and the second semiconductor material as mentioned above, that is SiGe. According to the preferred embodiment, Ge in the first single layer 140 a has a first concentration, Ge in the second single layer 140 b has a second concentration, and Ge in the third single layer 140 c has a third concentration. The first concentration, the second concentration, and the third concentration are all lower than the Ge concentration in the epitaxial structures 130. According to the preferred embodiment, the first concentration is preferably about 25%, the second concentration is preferably about 0%, and the third concentration is between the first concentration and the second concentration, preferably but not limited to about 10%. In other words, the second preferred embodiment provides a multilayered cap layer 140 has the Ge concentration upwardly decreased. In addition, a thickness of the undoped cap layer 140 is, exemplarily but not limited to, 150 Å in the preferred embodiment. It is also noteworthy that a thickness of the first single layer 140 a, a thickness of the second single layer 140 b, and a thickness of the third single layer 140 c have a ratio, and the ratio is about 1:1:1 according to the preferred embodiment.
As mentioned above, the semiconductor device 100 provided by the preferred embodiment can also include an undoped under layer 150. Since details about the undoped under layer 150 will be described in the following preferred embodiments, therefore those details are omitted herein for simplicity.
According to the semiconductor device 100 having epitaxial structures provided by the third preferred embodiment, the multilayered cap layer 140 is formed on the surface of the epitaxial structures 130. The multilayered cap layer 140 upwardly includes the first single layer 140 a, the third single layer 140 c, and the second single layer 140 b. All of the first single layer 140 a, the third single layer 140 c, and the second single layer 140 b include SiGe. The Ge concentration in the first single layer 140 a is preferably about 25%, the Ge concentration in third single layer 140 c is preferably about 10%, and the Ge concentration in the second single layer 140 b is preferably about 0%. In addition, thickness of the first single layer 140 a, the third single layer 140 c, and second single layer 140 b are substantially identical. That means the multilayered cap layer 140 has the Ge concentration upwardly decreased. Since the first single layer 140 a (Ge concentration of about 25%) and the third single layer 140 c (Ge concentration of about 10%) are formed between the second single layer 140 b (Ge concentration of about 0%) and the epitaxial structure 130 (Ge concentration of about 36%), the first single layer 140 a and the third single layer 140 c serve as buffer layers between the second single layer 140 b and the epitaxial structure 130. Because the two single layers having upwardly decreased concentration are formed between the second single layer 140 b and the epitaxial structure 130, the concentration gradient is flatter. Consequently, the cap layer 140 formed on the surface of the epitaxial structures 130 obtains a much smoother surface, and an AFM measured RMS roughness of the cap layer 140 is about 0.65 nm. Compared with the RMS roughness of the pure silicon cap layer, that is 4.21 nm, it is concluded that the surface roughness is much improved. Furthermore, since the Ge concentration of the second single layer 140 b in the undoped cap layer 140 is 0%, the second single layer 140 b serves as the reacting subject in the silicide process. Thus the agglomeration problem in the silicide process is prevented.
Please refer to FIGS. 4-5, which are schematic drawings respectively illustrating a semiconductor device having epitaxial structures provided by a fourth and fifth preferred embodiments of the present invention. It is noteworthy that elements the same in the first and fourth and fifth preferred embodiments such as the substrate 102, the gate structure 110, the LDDs 118, the spacer 120, the recesses 122, and the epitaxial structures 130 formed in the recesses 122 are depicted by the same numerals, and those details are omitted herein for simplicity.
As shown in FIG. 4, the fourth preferred embodiment provides an undoped under layer 150 (that is the under layer 150 mentioned in the first, second and third preferred embodiments) formed in the recesses 122. The undoped under layer 150 is formed between the epitaxial structure 130 and the substrate 102 and covers sidewalls and a bottom of the recess 122. As mentioned above, the undoped under layer 150 includes the first semiconductor material and the second semiconductor material. In other words, the undoped under layer 150 includes SiGe. To solve the Vt roll-off problem due to the distinctive difference between the lattice constant of the epitaxial structures 130 and that of the substrate 102, the preferred embodiment provides a single undoped under layer 150, and a Ge concentration of the undoped under layer 150 is lower than the Ge concentration of the epitaxial structures 130, exemplarily is about 25%.
It is noteworthy that because the undoped under layer 150 is provided to solve the problem that the lattice constant of the epitaxial structure 130 is distinctly different from that of the substrate 102, the undoped under layer 150 covering the bottom of the recess 122 cannot be formed so thick that the undoped under layer 150 occupies the space for forming the epitaxial structures 130, and thus reduces the strain stress provided to the channel region. Accordingly, a thickness of the undoped under layer 150 covering the sidewalls of the recess 122 and the thickness of the undoped under layer 150 covering the bottom of the recess 122 have a ratio and the ratio is about 1:1 in the preferred embodiment. It is found that when the undoped under layer 150 having Ge concentration of about 25% is formed in a process pressure of about 50 Torr, a ratio of the thickness of the single under layer 150 covering the sidewalls of the recess 122 and the thickness of the single under layer 150 covering the bottom of the recess 122 is about 1:2. Consequently, the space for forming the epitaxial structure 130 is reduced. Therefore the preferred embodiment forms the single under layer 150 in a process pressure of about 10 Torr. Accordingly, the thickness of the single under layer 150 covering the sidewalls of the recess 122 and the thickness of the single under layer 150 covering the bottom of the recess 122 approaches the expected ratio: 1:1.
According to the semiconductor device 100 having epitaxial structures provided by the fourth preferred embodiment, the single under layer 150 is formed in between the epitaxial structure 130 and the substrate 102. The single under layer 150 includes SiGe and the Ge concentration in the single under layer 150 is preferably about 25%. Since the single under layer 150 (Ge concentration of about 25%) is form between the substrate 102 (Ge concentration of about 0%) and the epitaxial structure 130 (Ge concentration of about 36%), the single under layer 150 serves as a buffer layer between the substrate 102 and the epitaxial structure 130. And thus the Vt roll-off problem caused by the distinctive difference between the lattice constant of the epitaxial structures 130 and that of the substrate 102 is mitigated. Moreover, since the ratio of the thickness of the single under layer 150 covering the sidewalls of the recess 122 and the thickness of the single under layer 150 covering the bottom of the recess 122 is about 1:1, the single under layer 150 is formed not to occupy the precious space used to form the epitaxial structure 130. Briefly speaking, the single under layer 150 provided by the preferred embodiment is able to solve the Vt roll-off problem without rendering impact to the strain stress.
Please refer to FIG. 5, which is a schematic drawing illustrating a semiconductor device having epitaxial structures provided by a fifth preferred embodiment of the present invention. As shown in FIG. 5, the fifth preferred embodiment provides an undoped under layer 150 (that is the undoped under layer 150 mentioned in the first, second and third preferred embodiments) formed in the recesses 122. The undoped under layer 150 is formed between the epitaxial structure 130 and the substrate 102 and covers sidewalls and a bottom of the recess 122. As mentioned above, the undoped under layer 150 includes the first semiconductor material and the second semiconductor material. In other words, the undoped under layer 150 includes SiGe. It is noteworthy that the undoped under layer 150 provided by the preferred embodiment is a multilayered under layer upwardly including a first single layer 150 a, a second single layer 150 b, and a third single layer 150 c. Ge in the first single layer 150 a has a first concentration, Ge in second single layer 150 b has a second concentration, and Ge in the third single layer 150 c has a third concentration. The first concentration, the second concentration, and the third concentration are all lower than the Ge concentration of the epitaxial structures 130. The third concentration is larger than the second concentration and the second concentration is larger than the first concentration. For example, the first concentration is about 10%, the second concentration is about 17%, and the third concentration is about 25%. In other words, the Ge concentration of the multilayered under layer 150 provided by the preferred embodiment is upwardly increased. In addition, a thickness of the first single layer 150 a, a thickness of the second single layer 150 b, and a thickness of the third single layer 150 c have a ratio, and the ratio is between 1:1:1 and 1:1:2. It is noteworthy that with increase of the Ge concentration in the first single layer 150 a, the second single layer 150 b, and the third single layer 150 c, the ratio of the thickness of the multilayered under layer 150 covering the sidewalls of the recess 122 and the thickness of the multilayered under layer 150 covering the bottom of the recess 122 is getting near to 1:1.
According to the semiconductor device 100 having epitaxial structures provided by the fifth preferred embodiment, the multilayered under layer 150 is formed in between the epitaxial structure 130 and the substrate 102. The multilayered under layer 150 includes the first single layer 150 a, the second single layer 150 b, and the third single layer 150 c. The first single layer 150 a, the second single layer 150 b and the third single layer 150 c all include SiGe. The Ge concentrations in the first single layer 150 a, in the second single under layer 150 b and in the third single layer 150 c is increased from 10%, to 17%, and to 25%. Therefore the multilayered under layer 150 serves as a buffer layer between the substrate 102 (having the Ge concentration of 0%) and the epitaxial structure 130 (having the Ge concentration of 36%). Because the three single layers having upwardly increased Ge concentration are formed between the substrate 102 and the epitaxial structure 130, the concentration gradient is flatter. Consequently, the Vt roll-off problem caused by the distinctive difference between the lattice constant of the epitaxial structures 130 and that of the substrate 102 140 b is mitigated. Moreover, since the ratio of the thickness of the multilayered under layer 150 covering the sidewalls of the recess 122 and the thickness of the multilayered under layer 150 covering the bottom of the recess 122 is about 1:1, the multilayered under layer 150 is formed not to occupy the precious space used to form the epitaxial structures 130. Briefly speaking, the multilayered under layer 150 provided by the preferred embodiment is able to solve the Vt roll-off problem without rendering impact to the strain stress.
It should be noted that the undoped under layer 150 provided by the fourth and fifth preferred embodiments of the present invention and the undoped cap layer 140 provided by the first, second, and third preferred embodiments can be formed in different combination in order to improve the semiconductor device 100 having the epitaxial structures 130.
According to the semiconductor device having epitaxial structures provided by the present invention, the epitaxial structures serving as the source/drain of the semiconductor device includes the undoped cap layer with lower Ge concentration formed on the surface of the epitaxial structures, therefore the agglomeration between the metals and Ge in the silicide process and the junction leakage are both prevented. Furthermore, the semiconductor device having epitaxial structures provided by the present invention also includes the undoped under layer with lower Ge concentration formed in the recess and in between the epitaxial structure and the substrate, therefore the Vt roll-off issue, which is caused by lattice constant difference between the SiGe epitaxial structure and the silicon substrate, is mitigated.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (19)

What is claimed is:
1. A semiconductor device having epitaxial structures comprising:
a gate structure positioned on a substrate;
epitaxial structures formed in the substrate at two sides of the gate structure, the epitaxial structures comprising a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, the second lattice constant being larger than the first lattice constant, the second semiconductor material in the epitaxial structures having a first concentration; and
an undoped cap layer formed on the epitaxial structures, the undoped cap layer being a multi-layer and comprising the first semiconductor material and the second semiconductor material, the second semiconductor material in the undoped cap layer having a second concentration, and the second concentration is lower than the first concentration, the second concentration is at least 25%.
2. The semiconductor device having epitaxial structures according to claim 1, further comprising:
lightly-doped drains (LDDs) formed in the substrate respectively at the two sides of the gate structure; and
a spacer formed on sidewalls of the gate structure.
3. The semiconductor device having epitaxial structures according to claim 1, wherein the first semiconductor material comprises silicon (Si) and the second semiconductor material comprises germanium (Ge).
4. The semiconductor device having epitaxial structures according to claim 1, wherein the multi-layer comprises at least a first single layer and a second single layer, the first single layer is formed between the second single layer and the epitaxial structure, the first single layer has the second concentration, the second semiconductor material in the second single layer has a third concentration, and the third concentration is equal to 0%.
5. The semiconductor device having epitaxial structures according to claim 4, wherein a thickness of the first single layer and a thickness of the second single layer have a ratio, and the ratio is about 1:2.
6. The semiconductor device having epitaxial structures according to claim 4, wherein the multi-layer further comprises a third single layer formed between the first single layer and the second single layer, the second semiconductor material in the third single layer has a fourth concentration, and the fourth concentration is between the second concentration and the third concentration.
7. The semiconductor device having epitaxial structures according to claim 6, wherein the fourth concentration is about 10%.
8. The semiconductor device having epitaxial structures according to claim 6, wherein a thickness of the first single layer, a thickness of the second single layer, and a thickness of the third single layer have a ratio, and the ratio is about 1:1:1.
9. The semiconductor device having epitaxial structures according to claim 1, further comprising a multilayered under layer positioned between the epitaxial structure and the substrate, the multilayered under layer comprises the first semiconductor material and the second semiconductor material.
10. The semiconductor device having epitaxial structures according to claim 9, wherein the second semiconductor material in the multilayered under layer is between 10% and 25%.
11. The semiconductor device having epitaxial structures according to claim 10, wherein a concentration of the second semiconductor material in the multilayered under layer is upwardly increased.
12. A semiconductor device having epitaxial structures comprising:
a gate structure positioned on a substrate;
a pair of recesses formed in the substrate at two sides of the gate structure;
epitaxial structures respectively formed in recesses at the two sides of the gate structure, the epitaxial structures comprising a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, the second lattice constant being larger than the first lattice constant, the second semiconductor material in the epitaxial structures having a first concentration; and
an undoped under layer formed in the recesses and in between the epitaxial structure and the substrate, the undoped under layer being a multi-layer and covering sidewalls and a bottom of the recess and having the first semiconductor material and the second semiconductor material, the second semiconductor material in the undoped under layer having a second concentration, and the second concentration is lower than the first concentration, the second concentration is about 25%,
wherein a thickness of the undoped under layer covering the sidewalls of the recess and a thickness of the undoped under layer covering the bottom of the recess have a ratio, and the ratio is about 1:1 and
a multilayered cap layer positioned on epitaxial structures, the multilayered cap layer comprises the first semiconductor material and the second semiconductor material, wherein the second semiconductor material in the multilayered cap layer has a concentration of at least 25%.
13. The semiconductor device having epitaxial structures according to claim 12, further comprising:
lightly-doped drains formed in the substrate respectively at the two sides of the gate structure; and
a spacer formed on sidewalls of the gate structure.
14. The semiconductor device having epitaxial structures according to claim 12, wherein the first semiconductor material comprises Si and the second semiconductor material comprises Ge.
15. The semiconductor device having epitaxial structures according to claim 12, wherein the multilayered under layer comprises at least a first single layer, a second single layer, and a third single layer upwardly formed on the sidewalls and the bottom of the recess.
16. The semiconductor device having epitaxial structures according to claim 15, wherein the third single layer has the second concentration, the second single layer has a third concentration, and the first single layer has a fourth concentration, the second concentration is larger than the third concentration and the third concentration is larger than the fourth concentration.
17. The semiconductor device having epitaxial structures according to claim 16, wherein the third concentration is about 17% and the fourth concentration is about 10%.
18. The semiconductor device having epitaxial structures according to claim 16, wherein a thickness of the first single layer, a thickness of the second single layer and a thickness of the third single layer have a ratio and the ratio is between 1:1:1 and 1:1:2.
19. The semiconductor device having epitaxial structures according to claim 12, wherein the concentration of the second semiconductor material in the multilayered cap layer is upwardly decreased.
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