US8685807B2 - Method of forming metal gates and metal contacts in a common fill process - Google Patents
Method of forming metal gates and metal contacts in a common fill process Download PDFInfo
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- US8685807B2 US8685807B2 US13/100,798 US201113100798A US8685807B2 US 8685807 B2 US8685807 B2 US 8685807B2 US 201113100798 A US201113100798 A US 201113100798A US 8685807 B2 US8685807 B2 US 8685807B2
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- gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Definitions
- the present disclosure is generally directed to the field of semiconductor processing, and, more particularly, to a method of forming metal gate structures and metal contacts in a common fill process.
- many semiconductor devices e.g., transistors
- the techniques selected depends upon many factors, such as the type of device under construction, the desired performance characteristics, etc.
- the final gate electrode structure is formed earlier in the process as compared to when the final gate electrode is formed in a typical “gate-last” approach.
- the gate material is deposited on a previously formed gate insulation layer, and thereafter an etching process is performed to define the final gate electrode.
- gate-first the final gate electrode must be made of a material that is able to withstand all of the subsequent processing operations, e.g., various heat treatments, etc. For that reason, use of the “gate-first” technique tends to limit the material that may be used for the gate electrode.
- gate-last a “dummy gate” material is formed early in the process and serves as a placeholder for what will ultimately be the final gate electrode structure.
- the dummy gate material will be removed and a replacement gate electrode material will be formed in its place.
- This replacement gate electrode is the final gate electrode for the transistor. Since the replacement gate electrode material is not subject to all of the processing conditions that the gate electrode in a “gate-first” technique is subjected to, the final gate electrode in a “gate-last” technique may be made of a variety of different metals or other conductive material. Thus, the “gate-last” technique gives designers more flexibility as to the final gate electrode material which can be important in the ultimate performance of the device.
- CMP chemical mechanical polishing
- the present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.
- the method includes forming a gate structure comprising a sacrificial gate electrode material, forming at least one conductive contact opening in a layer of insulating material positioned adjacent the gate structure, removing the sacrificial gate electrode material to thereby define a gate electrode opening, and performing a common deposition process to fill the conductive contact opening and the gate electrode opening with a conductive fill material.
- the method includes forming a gate structure comprising a gate insulation layer, a high-k layer positioned above the gate insulation layer, and a sacrificial gate electrode material positioned above the high-k layer, forming at least one conductive contact opening in a layer of insulating material positioned adjacent the gate structure, removing the sacrificial gate electrode material to thereby define a gate electrode opening, performing a common deposition process to fill the conductive contact opening and the gate electrode opening with a conductive fill material, and performing a planarization process to remove portions of the conductive fill material positioned outside of the conductive contact opening and the gate electrode opening.
- FIGS. 1A-1G depict one illustrative process flow involving the subject matter disclosed herein.
- the present disclosure is directed to method for forming replacement gate electrode structures and conductive contacts in a common fill process on a semiconductor device.
- the present method is applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, resistors, conductive lines, etc.
- FIG. 1A depicts an illustrative device 100 that is generally comprised of a partially formed NFET transistor 100 N and a partially formed PFET transistor 100 P formed in and above a semiconducting substrate 10 .
- the illustrative transistors 100 N, 100 p are separated by an illustrative isolation structure 12 , e.g., a shallow trench isolation structure, formed in the substrate 10 .
- the semiconducting substrate 10 is comprised of silicon.
- the substrate 10 is depicted in a bulk configuration.
- SOI silicon-on-insulator
- the terms substrate or semiconductor substrate should be understood to cover all semiconductor structures.
- the transistors 100 N, 100 P are each comprised of source/drain regions 14 , sidewall spacers 16 , a gate insulation layer 18 , and a high-k insulation layer 20 .
- the partially formed transistors 100 N, 100 P are positioned in a layer of insulating material 22 , e.g., silicon dioxide, that is formed above the substrate 10 .
- the sidewall spacers 16 were formed adjacent a polysilicon “gate electrode” which has been removed in the view shown in FIG. 1A .
- the illustrative transistors 100 N, 100 P depicted herein are formed using a gate-last technique.
- the various components and structures of the transistors 100 n , 100 P may be formed using a variety of known techniques and materials.
- the gate insulation layer 18 may be comprised of a variety of materials, e.g., silicon dioxide, silicon nitride, an oxynitride, a silicon nitride/silicon dioxide bilayer, etc., and it may be formed by a variety of techniques, e.g., chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), thermal growth, etc.
- CVD chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- the gate insulation layer 16 is comprised of a thermally grown layer of silicon dioxide having a thickness ranging from approximately 1-4 nm.
- the high-k layer 20 may be comprised of a variety of materials having a dielectric constant greater that 10, e.g., hafnium oxide, zirconium oxide, etc.
- the high-k layer 20 may be formed by a variety of techniques, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), etc.
- the high-k layer 20 may have a thickness of less that approximately 10 nm.
- the sidewall spacers 16 may be formed by forming an appropriate layer(s) (not shown) of material above the surface of the substrate 10 and thereafter performing an anisotropic etching process to define the sidewall spacers 16 . As noted above, the sidewall spacers 16 were form adjacent a polysilicon “gate electrode” which has been removed at the point of fabrication depicted in FIG. 1A .
- the source/drain regions 14 may be formed by performing well known ion implantation techniques using well-known dopant materials.
- a work function metal layer 30 is conformally deposited above the transistors 100 N, 100 P.
- the work function metal layer 30 may be comprised of a variety of materials, e.g., titanium nitride, depending upon the particular application, and it may be formed by a variety of techniques, e.g., physical vapor deposition (PVD), etc.
- the work function metal layer 30 is a layer of titanium nitride having a thickness less than approximately 10 nm.
- FIG. 1C depicts the device 100 after portions of the work function metal layer 30 has been removed from the NFET transistor 100 N.
- Portions of the work function metal layer 30 may be removed by forming a masking layer (not shown), e.g., a resist mask, above the PFET transistor 100 P and thereafter performing a dry or wet etching process to remove the desired portions of the work function metal layer 30 from the NFET transistor 100 N.
- the parameters of the etching process are selected and controlled such that portions of the work function metal layer 30 remain above the high-k layer 20 in the NFET transistor 100 N.
- the work function metal layer 30 remains positioned above the high-k layer 20 and on the sidewalls of the spacers 16 .
- a process such as a CMP process, may be performed to remove portions of the work function metal layer 30 positioned above the layer of insulating material 22 .
- FIG. 1D depicts the device 100 at a point of fabrication wherein a sacrificial gate material 40 has been formed in the gate structures of the transistors 100 N, 100 P.
- a patterned masking layer 32 e.g., a resist mask, that has be formed above the device 100 using known techniques.
- the masking layer 32 is used when an etching process 33 is performed to define contact openings 34 in the insulating layer 22 .
- the sacrificial gate material 40 may be comprised of a variety of different materials and that may be formed by a variety of different processes.
- the sacrificial gate material 40 may be a spin-on type of material or it may be a deposited process layer, like polysilicon.
- the sacrificial gate material 40 is a wet gap fill (WGF) type of material that may be applied using a spin-on technique and subsequently cured. If a process layer of, for example, polysilicon is formed to serve as the sacrificial gate material 40 , then a deposition process followed by a CMP process may be performed to remove excess portions of the deposited layer of polysilicon.
- WGF wet gap fill
- the device 100 is depicted at the point of fabrication where the sacrificial gate material 40 and the masking layer 32 has been removed.
- the removal of the sacrificial gate material defines a gate electrode opening 41 in which final gate electrodes for the device 100 will be formed.
- FIG. 1E further depicts the device 100 after another work function metal layer 35 has been formed for the transistors 100 N, 100 P and in the openings 34 .
- the techniques employed to remove the sacrificial gate material 40 may vary depending upon the particular materials used for the sacrificial gate material 40 . For example, if the sacrificial gate material 40 is comprised of polysilicon, then one or more masking and etching processes may need to be performed to remove the polysilicon.
- the sacrificial gate material 40 is made of a spin-on type material, wet gap fill, then such a material may be removed by subjecting the device 100 to a solvent or acid bath that only attacks the sacrificial gate material 40 .
- the work function metal layer 35 may be comprised of a variety of materials, and it may be formed using a variety of techniques. In one illustrative embodiment, the work function metal layer 35 may be comprised of titanium nitride, it may have a thickness of less than 10 nm, and it may be formed using and physical vapor deposition process (PVD).
- the next process involves forming the final gate electrodes 50 and the conductive contacts 52 for the device 100 in a common fill process.
- the final gate electrodes 50 and the conductive contacts 52 may be comprised of any of a variety of conductive materials, e.g., aluminum, tungsten. The selection of the appropriate material for the final gate electrodes 50 and the conductive contacts 52 may vary depending upon the particular application.
- the formation of the final gate electrodes 50 and the conductive contacts 52 may be accomplished by performing a deposition process to overfill the desired opening and thereafter performing a CMP process to remove excess portions of the deposited layer.
- the metallization layer 60 is comprised of a plurality of conductive members 62 , e.g., metal lines and/or contacts, formed in a layer of insulating material 64 .
- the size, shape, configuration and materials of construction for the conductive members 62 may vary depending on the particular application, e.g., the conductive members 62 may be comprised of aluminum, tungsten, copper, etc.
- the insulating material 64 may be comprised of, for example, a low-k material (k value less than 3), a high-k material, silicon dioxide, etc.
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US13/100,798 US8685807B2 (en) | 2011-05-04 | 2011-05-04 | Method of forming metal gates and metal contacts in a common fill process |
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US13/100,798 US8685807B2 (en) | 2011-05-04 | 2011-05-04 | Method of forming metal gates and metal contacts in a common fill process |
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US20120282765A1 US20120282765A1 (en) | 2012-11-08 |
US8685807B2 true US8685807B2 (en) | 2014-04-01 |
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Citations (7)
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US6444592B1 (en) * | 2000-06-20 | 2002-09-03 | International Business Machines Corporation | Interfacial oxidation process for high-k gate dielectric process integration |
US20020142531A1 (en) * | 2001-03-29 | 2002-10-03 | Hsu Sheng Teng | Dual damascene copper gate and interconnect therefore |
US6506673B2 (en) * | 2001-06-11 | 2003-01-14 | Agere Systems Guardian Corp. | Method of forming a reverse gate structure with a spin on glass process |
US20050148131A1 (en) * | 2003-12-30 | 2005-07-07 | Brask Justin K. | Method of varying etch selectivities of a film |
US20060128055A1 (en) * | 2004-12-14 | 2006-06-15 | International Business Machines Corporation | Replacement gate with tera cap |
US20100289094A1 (en) | 2009-05-15 | 2010-11-18 | Carsten Reichel | Enhancing deposition uniformity of a channel semiconductor alloy by an in situ etch process |
US20110272767A1 (en) * | 2010-04-09 | 2011-11-10 | Haizhou Yin | Semiconductor device and method of fabricating the same |
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2011
- 2011-05-04 US US13/100,798 patent/US8685807B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6444592B1 (en) * | 2000-06-20 | 2002-09-03 | International Business Machines Corporation | Interfacial oxidation process for high-k gate dielectric process integration |
US20020142531A1 (en) * | 2001-03-29 | 2002-10-03 | Hsu Sheng Teng | Dual damascene copper gate and interconnect therefore |
US6506673B2 (en) * | 2001-06-11 | 2003-01-14 | Agere Systems Guardian Corp. | Method of forming a reverse gate structure with a spin on glass process |
US20050148131A1 (en) * | 2003-12-30 | 2005-07-07 | Brask Justin K. | Method of varying etch selectivities of a film |
US20060128055A1 (en) * | 2004-12-14 | 2006-06-15 | International Business Machines Corporation | Replacement gate with tera cap |
US20100289094A1 (en) | 2009-05-15 | 2010-11-18 | Carsten Reichel | Enhancing deposition uniformity of a channel semiconductor alloy by an in situ etch process |
US20110272767A1 (en) * | 2010-04-09 | 2011-11-10 | Haizhou Yin | Semiconductor device and method of fabricating the same |
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