US8633096B2 - Creating anisotropically diffused junctions in field effect transistor devices - Google Patents
Creating anisotropically diffused junctions in field effect transistor devices Download PDFInfo
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- US8633096B2 US8633096B2 US12/943,987 US94398710A US8633096B2 US 8633096 B2 US8633096 B2 US 8633096B2 US 94398710 A US94398710 A US 94398710A US 8633096 B2 US8633096 B2 US 8633096B2
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Definitions
- the present invention relates generally to semiconductor device manufacturing and, more particularly, to creating anisotropically diffused junctions in field effect transistor (FET) devices.
- FET field effect transistor
- halo implants shield the increasingly small FET channel regions from the encroachment of the source and drain implants and thus help to reduce deleterious short channel effects (SCE).
- SCE deleterious short channel effects
- the resulting highly doped channels or pocket implant regions degrade device performance and power consumption by increasing junction capacitance and band-to-band tunneling.
- a method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions; introducing a transistor dopant species in the source and drain regions; and performing an anneal so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.
- a method of forming a field effect transistor (FET) device includes implanting a diffusion inhibiting species in a silicon-on-insulator (SOI) substrate comprising a bulk substrate, a buried oxide layer (BOX) formed on the bulk substrate, and an SOI layer formed on the BOX layer, the SOI substrate having one or more FET gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the SOI layer corresponding to a channel region, and disposed in portions of the BOX corresponding to source and drain regions; implanting a first, shallow transistor dopant species in the source and drain regions; implanting a second, deep transistor dopant species in the source and drain regions; and performing an anneal so as to diffuse the second transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the second transistor dopant species into the channel region.
- SOI silicon-on-insulator
- BOX buried oxide layer
- a method of forming a field effect transistor (FET) device includes implanting a diffusion inhibiting species in a silicon-on-insulator (SOI) substrate comprising a bulk substrate, a buried oxide layer (BOX) formed on the bulk substrate, and an SOI layer formed on the BOX layer, the SOI substrate having one or more FET gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the SOI layer corresponding to a channel region, and disposed in portions of the BOX corresponding to source and drain regions; implanting a first, shallow transistor dopant species in the source and drain regions; recessing portions of the SOI layer in the source and drain regions; filling the recessed portions of the SOI layer with a semiconductor material that is in-situ doped with a second, deep transistor dopant species in the source and drain regions; and performing an anneal so as to diffuse the second transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the second transistor dopant species into the channel
- a transistor device in another embodiment, includes a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer; a gate structure formed on the semiconductor-on-insulator layer, the gate structure comprising a gate conductor and sidewall spacers adjacent the gate conductor; a diffusion inhibiting species disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, self-aligned to the gate structure, the diffusion inhibiting species also disposed in portions of the buried insulator layer corresponding to source and drain regions; and a transistor dopant species introduced in the source and drain regions; wherein the transistor dopant species has a substantially vertical profile within the source and drain regions, extending to the buried insulator layer while the channel region is substantially free of the transistor dopant species.
- a field effect transistor (FET) device includes a silicon-on-insulator (SOI) substrate comprising a bulk substrate, a buried oxide (BOX) layer, and an SOI layer; a gate structure formed on the SOI layer, the gate structure comprising a gate conductor and sidewall spacers adjacent the gate conductor; a diffusion inhibiting species disposed in portions of the SOI layer corresponding to a channel region, self-aligned to the gate structure, the diffusion inhibiting species also disposed in portions of the BOX layer corresponding to source and drain regions; a first, shallow transistor dopant species implanted in the source and drain regions; and a second, deep transistor dopant species introduced in the source and drain regions; wherein the second transistor dopant species has a substantially vertical profile within the source and drain regions, extending to the BOX layer while the channel region is substantially free of the second transistor dopant species.
- SOI silicon-on-insulator
- BOX buried oxide
- FIGS. 1( a ) through 1 ( f ) are cross sectional views of an exemplary method of creating anisotropically diffused junctions in field effect transistor (FET) devices, in accordance with an embodiment of the invention where, in particular:
- FIG. 1( a ) is cross sectional view of a silicon-on-insulator (SOI) substrate having a pair of NFET gates formed thereon;
- SOI silicon-on-insulator
- FIG. 1( b ) illustrates implantation of a carbon species for the device shown in FIG. 1( a );
- FIG. 1( c ) illustrates the resulting locations of the carbon regions in the channel regions of the SOI layer below the gate structures, and in the BOX layer below the source and drain regions, following the implantation of FIG. 1( b );
- FIG. 1( d ) illustrates a shallow source/drain implant of the device shown in FIG. 1( c ) using a first dopant
- FIG. 1( e ) illustrates a deep source/drain implant of the device shown in FIG. 1( d ) using a second dopant
- FIG. 1( f ) illustrates a rapid thermal anneal (RTA) process that drives the second dopant of FIG. 1( e ) vertically down toward the level of the BOX layer while inhibiting vertical encroachment of the second dopant into the channel regions;
- RTA rapid thermal anneal
- FIGS. 2( a ) through 2 ( c ) are cross sectional views of an exemplary method of creating anisotropically diffused junctions in field effect transistor (FET) devices, in accordance with an embodiment of the invention where, in particular:
- FIG. 2( a ) illustrates recessing of the SOI layer in between gate structures following the shallow source/drain implant of FIG. 1( d );
- FIG. 2( b ) illustrates filling of the recessed areas of the SOI layer in FIG. 2( a ) with a silicon or a silicon alloy that is in-situ doped with a second dopant;
- FIG. 2( c ) illustrates an RTA process that drives the second dopant of FIG. 2( c ) vertically down toward the level of the BOX layer while inhibiting vertical encroachment of the second dopant into the channel regions.
- a method and structure for creating anisotropically diffused junctions in field effect transistor (FET) devices are disclosed.
- FET field effect transistor
- embodiments of a method to promote vertical diffusion of an NFET and/or a PFET S/D junction and simultaneously inhibit lateral diffusion are disclosed, which embodiments enable a deep source/drain with a relatively modest size spacer and reduced halo implant dose. Consequently, such a process reduces the S/D series resistance of the NFET and/or PFET, and enables the use of thicker silicon-on-insulator (SOI) substrates, which are advantageous for eSiGe p-type FET (PFET) and eSiC n-type FET (NFET) stress optimization.
- SOI silicon-on-insulator
- boron difluoride (BF 2 ) dopant in a PFET device is equivalent to arsenic (As) dopant in an NFET device, while boron (B) dopant in the PFET device is equivalent to phosphorus (P) dopant in the NFET device.
- the embodiments implement a through-gate implant of a diffusion inhibiting species (e.g., carbon) for NFET SOI devices, such that the carbon is incorporated into the channel region (e.g., silicon) under the gate.
- a diffusion inhibiting species e.g., carbon
- the carbon species passes through the SOI layer and into the buried oxide (BOX) layer below the SOI layer.
- an n-type dopant such as P for example, is implanted or in-situ doped with regrown semiconductor material into the NFET S/D regions for deep junction formation.
- the diffusion of P is well-known to be inhibited by carbon.
- a rapid thermal anneal diffuses the phosphorous dopant atoms vertically down toward the BOX layer, effectively butting the junctions and reducing S/D resistance.
- RTA rapid thermal anneal
- the carbon that is effectively self-aligned to the FET channel substantially inhibits lateral diffusion of the phosphorous.
- FIG. 1 there is shown a cross sectional view of a semiconductor-on-insulator such as an SOI integrated circuit device 100 having a pair of NFET gates formed thereon, suitable for use in accordance with an embodiment of the invention.
- the device 100 includes a bulk substrate 102 , such as silicon for example, a BOX layer 104 or other suitable insulating layer formed on the bulk substrate 102 , and a thin SOI layer 106 , or other suitable semiconductor-on-insulator layer formed on the BOX layer 104 .
- a pair of NFET gate structures, each including gate electrodes 108 and sidewall spacers 110 are formed over the SOI layer 106 , in accordance with existing semiconductor processing techniques.
- the device is subjected to an implant with a species such as carbon (indicated by the arrows) such that the carbon becomes implanted into the channel regions of the SOI layer 106 below the gate electrodes 108 , while with respect to the source/drain regions of the SOI layer 106 , the carbon passes through the SOI layer and becomes implanted within the BOX layer 104 .
- a species such as carbon
- a first, shallow source/drain implant is performed using a first n-type dopant 114 .
- This first implant is self-aligned to the gate.
- the first n-type dopant 114 is arsenic (As), which also extends beneath the sidewall spacers.
- Arsenic is the dopant of choice for shallow source/drain junctions because its as-implanted profile is relatively shallow and abrupt and it is resistance to transient-enhanced diffusion.
- a second, deep source/drain implant is performed using a second n-type dopant. This second implant is also self-aligned to the gate.
- the second n-type dopant 116 is phosphorous (P).
- Phosphorus is the dopant species of choice for deep junctions because its as-implanted profile is broad and readily made deep, both relative to that of arsenic. However, in silicon, phosphorus diffuses extremely quickly compared to arsenic.
- FIG. 1( f ) illustrates diffusion of the second-type dopant 116 following an RTA process.
- the diffusion of the phosphorous species 116 is predominately in a vertical direction, toward the BOX layer 104 , due to the presence of the carbon species in the channel regions of the NFET.
- the uninhibited vertical diffusion enables a butted and low-resistance junction yet avoids short channel effects degradation from lateral encroachment of the dopant into the device channel.
- boron difluoride may be an analog dopant species of arsenic and boron (B) may be an analog dopant species of phosphorus.
- fluorine is a possible, though less desirable, analog of carbon for both NFETs and PFETs.
- introduction of the second type (deep) dopant into the source/drain regions is depicted by way of an implant process. In an alternative embodiment, however, this may be performed by SOI etching followed by epitaxial regrowth of the source drain regions with an in-situ doped semiconductor material.
- FIG. 2( a ) portions of the SOI layer 106 are recessed such as by etching following a point in processing after the first, shallow source/drain implant process of FIG. 1( d ). This results in recessed areas 202 shown in FIG. 2( a ). Then, as shown in FIG.
- the recessed areas are filled with an epitaxially grown semiconductor material 204 that is in-situ doped with a suitable second dopant.
- the dopant may be phosphorus, while for the PFET example, the dopant may be boron.
- the semiconductor material may be, for example, silicon, or an alloy of silicon such as silicon germanium (SiGe). Other semiconductor materials could also be used.
- an RTA process diffuses the in-situ dopant of the epitaxially grown semiconductor material 204 . As is the case with the implanted embodiment of FIG.
- the diffusion of the in-situ species is predominately in a vertical direction, toward the BOX layer 104 , due to the presence of the carbon species in the channel regions of the NFET and the PFET (or, alternatively, the fluorine species in the PFET channel).
- the uninhibited vertical diffusion enables a butted and low-resistance junction yet avoids short channel effects degradation from lateral encroachment of the dopant into the device channel.
Abstract
Description
Claims (13)
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US12/943,987 US8633096B2 (en) | 2010-11-11 | 2010-11-11 | Creating anisotropically diffused junctions in field effect transistor devices |
PCT/EP2011/069717 WO2012062791A1 (en) | 2010-11-11 | 2011-11-09 | Creating anisotrpically diffused junctions in field effect transistor devices |
CN201180054201.4A CN103201832B (en) | 2010-11-11 | 2011-11-09 | Create the anisotropy parameter knot in FET device |
US14/053,708 US8796771B2 (en) | 2010-11-11 | 2013-10-15 | Creating anisotropically diffused junctions in field effect transistor devices |
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US20140042541A1 (en) | 2014-02-13 |
CN103201832B (en) | 2016-01-20 |
US8796771B2 (en) | 2014-08-05 |
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US20120119294A1 (en) | 2012-05-17 |
WO2012062791A1 (en) | 2012-05-18 |
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