US7723182B2 - Storage electrode of a capacitor and a method of forming the same - Google Patents
Storage electrode of a capacitor and a method of forming the same Download PDFInfo
- Publication number
- US7723182B2 US7723182B2 US11/291,798 US29179805A US7723182B2 US 7723182 B2 US7723182 B2 US 7723182B2 US 29179805 A US29179805 A US 29179805A US 7723182 B2 US7723182 B2 US 7723182B2
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- United States
- Prior art keywords
- layer
- storage electrode
- forming
- capacitor
- amorphous silicon
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- Expired - Fee Related, expires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Definitions
- the present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a storage electrode of a capacitor of a semiconductor device and a method of forming a storage electrode of a capacitor.
- a DRAM device generally includes a cell array composed of cells to store information, and a peripheral circuit to transfer the information to an exterior region.
- a memory cell of the DRAM device is generally composed of a transistor for a switching function, and a capacitor for storing information.
- an important factor in a DRAM semiconductor device is a capacitance of the cell capacitor for storing information.
- providing a capacitor having a maximized capacitance with a small area is important in the fabrication of the DRAM device that has a reduced minimum line width and high integration.
- a capacitance of a capacitor is proportional to the permittivity of its dielectric layer and the area of its electrodes.
- the capacitor is also inversely proportional to the interval between the capacitor's electrodes. So one way to maximize the capacitance is to increase the areas of the capacitor's electrodes, reduce an interval between the capacitor's electrodes, and use a material layer having a high permittivity for the capacitor's dielectrics.
- a bridge may result between storage electrodes (lower electrodes) of different cells due to procedure misalignment and lack of process margins. This problem is a manifestation of a reduced design rule with a highly integrated DRAM device.
- the bridge may cause twin bit or multi-bit failures. Specifically, the magnitude of the bridge problem in a stack cell structure is inversely proportional to the interval between the storage electrodes (lower electrodes). That is, if the interval is increased, the number of bridges will decrease. But then surface areas of the storage electrodes (lower electrodes) are reduced, and thus, a capacitance of a capacitor is reduced.
- the concave structure is divided into a box type and a cylinder type.
- FIGS. 1 to 4 are cross-sectional views illustrating processes of a conventional method of forming a storage electrode of a concave structure capacitor.
- an insulating layer 102 is formed on a semiconductor substrate 100 having an isolation layer (not shown) and a transistor (not shown) formed thereon.
- the insulating layer 102 may be a silicon oxide layer, a silicon oxynitride layer, a phosphosilicate glass (PSG) layer, an undoped silicate glass (USG) layer, a borophosphosilicate glass (BPSG) layer, a plasma enhanced tetraethylothosilicate glass (PE-TEOS) layer, a TEOS layer, or a combination of these layers.
- a contact plug 104 is formed to penetrate the insulating layer 102 and to contact with a source region (not shown) of the transistor.
- a lower mold layer 106 , an etch stop layer 108 , and an upper mold layer 110 are formed on the surface of the resultant structure including the contact plug 104 .
- the upper mold layer 110 is formed of a silicon oxide layer, and is formed of a material layer having a high etch rate in an oxide layer etch recipe, such as for a P-TEOS or SOG group. Then, the upper mold layer 110 , the etch stop layer 108 , and the lower mold layer 106 are sequentially patterned, forming a storage electrode hole 112 exposing the contact plug 104 .
- a storage electrode layer 116 and a sacrificial layer such as a sacrificial oxide layer 118 are formed on the surface of the resultant structure including the storage electrode hole 112 .
- the storage electrode layer may be a metal layer and a metal nitride layer.
- the metal layer may be a titanium layer.
- the metal nitride layer may be a titanium nitride layer.
- the sacrificial oxide layer 118 may be a silicon oxide layer, a silicon oxynitride layer, a PSG layer, a BSG layer, a BPSG layer, a TEOS layer, a PE-TEOS layer, a spin-on-glass (SOG) layer, a photosensitive layer, or a combination of these layers.
- a thin TiSi x layer (for example, TiSi 2 layer) 117 is formed between the storage electrode layer 116 and the contact plug 104 during the formation of the storage electrode layer 116 , to increase adhesiveness between the storage electrode layer 116 and the contact plug 104 .
- a node separation process for the storage electrodes is performed.
- the sacrificial oxide layer 118 and the storage electrode layer 116 are planarized and etched until the upper mold layer 110 is exposed, separating a storage electrode 116 s into a cell unit.
- the storage electrode 116 s is a cylinder type or a box type, depending on the shape of the storage electrode layer 116 .
- the storage electrode layer 116 fully filling the storage electrode hole 112 forms the storage electrode 116 s having a box structure, and the storage electrode layer 116 conformally covering the inner wall of the storage electrode hole 112 forms the storage electrode 116 s having a cylinder structure. Then, the sacrificial oxide layer 118 remaining inside the cylinder of the cylinder-structured storage electrode 116 s is removed using a wet etch process, to expose the inner wall of the storage electrode 116 s.
- the upper mold layer 110 is isotropically etched, thereby exposing the etch stop layer 108 , and concurrently, exposing the outer wall of the storage electrode 116 s.
- FIGS. 5 to 8 are views illustrating a problem generated in the conventional method of forming a storage electrode of a capacitor.
- the sacrificial oxide layer 118 remaining inside the cylinder of the cylinder-structured storage electrode 116 s is removed using a wet etch process. Further, after the storage electrodes 116 s are separated into a cell unit, the upper mold layer 110 ( FIG. 3 ) surrounding the storage electrode 116 s is removed by an isotropic etching using a wet etch process.
- an etch solution may penetrate into the grain boundary of the storage electrode 116 s , to reach the TiSi x layer (for example, TiSi 2 layer) 117 , and etch the TiSi x layer (for example, TiSi 2 layer) 117 .
- the etch solution may penetrate into the lower mold layer 106 existing below the etch stop layer 108 through the interface between the storage electrode 116 s and the etch stop layer 108 , to etch the lower mold layer 106 .
- the etch solution penetrates into the storage electrode 116 s , and there occurs a Galvanic reaction between the storage electrode 116 s and the contact plug 104 .
- the contact plug 104 partially corrodes so that cavities are generated. The phenomenon brings snail-shaped defects, which may be so called ‘snail defect’ by one skilled in the art.
- a height of the storage electrode 116 s is formed relatively high compared to its width, to maximize the capacitance of the capacitor within a limited area.
- the lower mold layer 106 functions to support the lower portion of the storage electrode 116 s having a high aspect ratio.
- the lower mold layer 106 and the insulating layer 102 may be inadvertently etched by the penetrating etch solution. Then the storage electrode 116 s may fall, causing a bridge to occur between neighboring storage electrodes 116 s , thereby causing twin bit or multi-bit failures.
- the etching of the lower mold layer 106 and the insulating layer 102 during the operation of removing the sacrificial oxide layer 118 and the upper mold layer 110 may cause a lift-up phenomenon, wherein the storage electrode 116 s lifts up from the lower mold layer 106 and the insulating layer 102 , and the structure of the storage electrode 116 s formed through the node separation process may be distorted during an operation of forming a capacitor dielectric layer or an operation of annealing the capacitor dielectric layer.
- the interfaces of the storage electrode 116 s , the lower mold layer 106 , and the insulating layer 102 may be completely separated, thereby causing a lift-up phenomenon, in which the storage electrode 116 s is lifted up.
- the etch for the lower mold layer 106 and the insulating layer 102 during the operation of removing the sacrificial oxide layer 118 and the upper mold layer 110 is not excessive enough to cause the lift-up phenomenon.
- cavities may be generated by the etch of the lower mold layer 106 and the insulating layer 102 , causing the structure of the storage electrode of the capacitor to be distorted during subsequent processes of forming a capacitor dielectric layer, or annealing the capacitor dielectric layer.
- FIGS. 7 and 8 are photographs illustrating the storage electrode of the capacitor in which the snail defect phenomenon occurs.
- FIG. 7 illustrates a leaning hole phenomenon caused by the inclined storage electrode
- FIG. 8 illustrates that cavities are generated in the lower mold layer due to the snail defect phenomenon.
- embodiments of the present invention are directed to providing a semiconductor device, and a method of fabricating the same, capable of solving the problems depicted above.
- an embodiment of the present invention provides a storage electrode of a capacitor, and a method of forming the same, capable of not falling, despite the storage electrode having a high aspect ratio.
- a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes.
- a method of forming the storage electrode of the capacitor is described.
- the storage electrode of the capacitor may include a first metal layer electrically connected with a source region of a transistor through a contact plug penetrating an insulating layer on a semiconductor substrate.
- a polysilicon layer may be formed on the first metal layer.
- a second metal layer is formed on the polysilicon layer.
- Another embodiment of the present invention provides a storage electrode of a capacitor, and a method of forming the same, that avoids an excessive etch of a lower mold layer during its manufacture.
- Yet another embodiment of the present invention provides a storage electrode of a capacitor, and a method of forming the same, resistant to the development of a bridge problem.
- Still another embodiment of the present invention provides a storage electrode of a capacitor, and a method of forming the same, resistant to a snail defect phenomenon.
- Still another embodiment of the present invention provides a storage electrode of a capacitor having an improved concave structure, and a method of forming the same.
- FIGS. 1 to 4 are cross-sectional views illustrating processes of a conventional method of forming a storage electrode of a concave structure capacitor
- FIGS. 5 and 6 are cross-sectional views illustrating a problem generated in a conventional method of forming a storage electrode of a capacitor
- FIG. 7 is a photograph illustrating a leaning hole phenomenon caused by inclined storage electrodes
- FIG. 8 is a photograph illustrating cavities generated in a lower mold layer due to a snail defect phenomenon
- FIG. 9 is a cross-sectional view illustrating a structure of a storage electrode of a capacitor according to the present invention.
- FIGS. 10 a to 10 e are cross-sectional views illustrating processes of a method of forming the storage electrode of the capacitor of FIG. 9 according to an embodiment of the present invention.
- FIG. 9 is a cross-sectional view illustrating a structure of a storage electrode of a capacitor according to an embodiment of the present invention.
- the storage electrode of the capacitor includes a first metal layer 216 a being in contact with a source region (not shown) of a transistor through a contact plug 204 penetrating an insulating layer 202 of a semiconductor substrate 200 , and preferably formed as a concave shape inside a predetermined storage electrode region defined on the insulating layer.
- a silicon layer 216 b is formed on the first metal layer 216 a with a predetermined thickness.
- the silicon layer 216 b may be changed from an amorphous structure to a crystal structure by a subsequent annealing process.
- a second metal layer 216 c formed on the silicon layer 216 b to a predetermined thickness.
- FIGS. 10 a to 10 e are cross-sectional views illustrating a method of forming the storage electrode of the capacitor of FIG. 9 , according to an embodiment of the present invention.
- the insulating layer 202 is formed on the semiconductor substrate 200 having an isolation layer (not shown) and a transistor (not shown) formed thereon. Then, the contact plug 204 , being in contact with the source region (not shown) of the transistor, is formed to penetrate the insulating layer 202 . Then, a lower mold layer 206 , an etch stop layer 208 , and an upper mold layer 210 are formed on the surface of the resultant structure that includes the contact plug 204 .
- the upper mold layer 210 may be formed of a silicon oxide layer, and may be formed of a material layer having a high etch rate in an oxide layer etch recipe, such as for a P-TEOS or an SOG group. Then, the upper mold layer 210 , the etch stop layer 208 , and the lower mold layer 206 are sequentially patterned, thereby forming a storage electrode hole 212 , exposing the contact plug 204 .
- a storage electrode layer 216 is formed on the surface of the resultant structure including the storage electrode hole 212 .
- a thin TiSi x layer (for example, a TiSi 2 layer) 217 may be formed between the storage electrode layer 216 and the contact plug 204 during the formation of the storage electrode layer 216 .
- titanium nitride (Ti/TiN) 216 a is deposited on the thin titanium silicon layer to form the storage electrode layer 216 .
- a silicon layer 216 b is deposited on the titanium nitride (Ti/TiN) 216 a . Since the silicon layer 216 b may be deposited at a low temperature of perhaps about 530° C. or less, it may be deposited as an amorphous structure.
- the silicon layer 216 b may be formed by flowing silane (SiH 4 ) gas inside a chamber, and thermally decomposing the silane (SiH 4 ) gas.
- the silicon layer 216 b is preferably formed to a thickness of about 100 ⁇ or less.
- a titanium nitride (TiN) layer 216 c is deposited on the silicon layer 216 b .
- a total thickness of the titanium nitride layers deposited above and below the silicon layer 216 b is preferably less than about 350 ⁇ . This is because if the total thickness of the titanium nitride layers is about 400 ⁇ or more, a problem with cracking may occur.
- a sacrificial oxide layer 218 is formed on the storage electrode layer 216 to fill the storage electrode hole 212 .
- a node separation process for the storage electrode is performed.
- the sacrificial oxide layer 218 and the storage electrode layer 216 are planarized and etched until the upper mold layer 210 is exposed, thereby separating a storage electrode 216 s into a cell unit.
- the remaining sacrificial oxide layer 218 that is inside the cylinder structure of the storage electrode 216 s is removed using a wet etch process, thereby exposing the inner wall of the storage electrode 216 s.
- the etch solution for the wet etch process preferably uses an LAL solution.
- the silicon layer 216 b functions as an etch stop layer with respect to an etch solution. Thus, it can prevent the etch solution from penetrating into a grain boundary of the storage electrode 216 s , and avoid etching the TiSi x layer 217 . Further, it can prevent the etch solution from penetrating into the lower mold layer 206 that is below the etch stop layer 208 , through the interface between the storage electrode 216 s and the etch stop layer 208 , and avoid etching the lower mold layer 206 .
- the etch solution penetrating into the storage electrode 216 s prevents a snail defect phenomenon caused by the etch solution penetrating into the storage electrode 216 s , as well as a galvanic reaction occurring between the storage electrode 216 s and the contact plug 204 . Also prevented is the etch solution penetrating into the storage electrode 216 s and etching the insulating layer 202 .
- the upper mold layer 210 is isotropically etched, thereby exposing the etch stop layer 208 , and concurrently exposing the outer wall of the storage electrode 216 s.
- the storage electrode 216 s is annealed at a temperature of about 550° C. to about 600° C., to crystallize the amorphous structure of the silicon layer 216 b.
- Crystallizing the silicon layer 216 b is intended to make the polysilicon layer function as an electrode.
- capacitor dielectric layer 220 is conformally formed on the surface of the resultant structure in which the outer wall of the storage electrode 216 s is exposed, and subsequent capacitor formation processes are performed.
- an etch solution is prevented from penetrating into a grain boundary of a storage electrode to avoid etching a TiSi x layer. Further, the etch solution is prevented from penetrating into a lower mold layer that is below an etch stop layer, through the interface between the storage electrode 216 s and the etch stop layer 208 to avoid etching the lower mold layer 206 .
- a snail defect phenomenon is avoided, as well as a galvanic reaction occurring between the storage electrode and a contact plug. Also prevented is the etch solution penetrating into the storage electrode 216 s and etching the insulating layer 202 . Also, an etch solution is prevented from penetrating into the storage electrode to etch the insulating layer. Therefore, storage electrodes are prevented from falling, excessive etch of the lower mold layer is prevented, and a bridge occurring between the storage electrodes can be prevented.
Abstract
Description
Claims (15)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040099688A KR100665838B1 (en) | 2004-12-01 | 2004-12-01 | Storage electrode of capacitor and fabricating method thereof |
KR2004-99688 | 2004-12-01 | ||
KR10-2004-0099688 | 2004-12-01 |
Publications (2)
Publication Number | Publication Date |
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US20060113575A1 US20060113575A1 (en) | 2006-06-01 |
US7723182B2 true US7723182B2 (en) | 2010-05-25 |
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US11/291,798 Expired - Fee Related US7723182B2 (en) | 2004-12-01 | 2005-11-30 | Storage electrode of a capacitor and a method of forming the same |
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US (1) | US7723182B2 (en) |
KR (1) | KR100665838B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11244946B2 (en) | 2019-10-29 | 2022-02-08 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for fabricating thereof |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5476311B2 (en) * | 2007-11-09 | 2014-04-23 | イー・アイ・デュポン・ドウ・ヌムール・アンド・カンパニー | Method of stripping solvent using antioxidant |
EP2395125A1 (en) * | 2010-06-08 | 2011-12-14 | The Swatch Group Research and Development Ltd. | Method of manufacturing a coated amorphous metal part |
CN102947022B (en) * | 2010-06-22 | 2016-03-16 | 斯沃奇集团研究和开发有限公司 | Parts assembling method |
KR101110388B1 (en) * | 2011-02-23 | 2012-02-24 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
KR101218506B1 (en) * | 2011-09-23 | 2013-01-21 | 에스케이하이닉스 주식회사 | Method for manufacturing semiconductor device |
US9831303B2 (en) * | 2012-11-02 | 2017-11-28 | Nanya Technology Corporation | Capacitor structure and process for fabricating the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6146967A (en) | 1997-08-20 | 2000-11-14 | Micron Technology, Inc. | Selective deposition of amorphous silicon film seeded in a chlorine gas and a hydride gas ambient when forming a stacked capacitor with HSG |
US6174769B1 (en) | 1999-04-27 | 2001-01-16 | Worldwide Semiconductor Manufacturing Corp. | Method for manufacturing stacked capacitor |
US6287965B1 (en) * | 1997-07-28 | 2001-09-11 | Samsung Electronics Co, Ltd. | Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor |
-
2004
- 2004-12-01 KR KR1020040099688A patent/KR100665838B1/en not_active IP Right Cessation
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2005
- 2005-11-30 US US11/291,798 patent/US7723182B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6287965B1 (en) * | 1997-07-28 | 2001-09-11 | Samsung Electronics Co, Ltd. | Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor |
US6146967A (en) | 1997-08-20 | 2000-11-14 | Micron Technology, Inc. | Selective deposition of amorphous silicon film seeded in a chlorine gas and a hydride gas ambient when forming a stacked capacitor with HSG |
US6174769B1 (en) | 1999-04-27 | 2001-01-16 | Worldwide Semiconductor Manufacturing Corp. | Method for manufacturing stacked capacitor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11244946B2 (en) | 2019-10-29 | 2022-02-08 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for fabricating thereof |
US11711915B2 (en) | 2019-10-29 | 2023-07-25 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for fabricating thereof |
Also Published As
Publication number | Publication date |
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US20060113575A1 (en) | 2006-06-01 |
KR100665838B1 (en) | 2007-01-09 |
KR20060060897A (en) | 2006-06-07 |
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