US7682906B2 - Method of manufacturing a non-volatile memory device - Google Patents
Method of manufacturing a non-volatile memory device Download PDFInfo
- Publication number
- US7682906B2 US7682906B2 US11/907,162 US90716207A US7682906B2 US 7682906 B2 US7682906 B2 US 7682906B2 US 90716207 A US90716207 A US 90716207A US 7682906 B2 US7682906 B2 US 7682906B2
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- Prior art keywords
- oxide layer
- layer
- forming
- metal oxide
- silicon oxide
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 73
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 73
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 68
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 65
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 63
- 239000010703 silicon Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims description 82
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 229910052735 hafnium Inorganic materials 0.000 claims description 12
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052684 Cerium Inorganic materials 0.000 claims description 3
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- 229910052691 Erbium Inorganic materials 0.000 claims description 3
- 229910052693 Europium Inorganic materials 0.000 claims description 3
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- 229910052765 Lutetium Inorganic materials 0.000 claims description 3
- 229910052779 Neodymium Inorganic materials 0.000 claims description 3
- 229910052777 Praseodymium Inorganic materials 0.000 claims description 3
- 229910052772 Samarium Inorganic materials 0.000 claims description 3
- 229910052771 Terbium Inorganic materials 0.000 claims description 3
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- 229910052782 aluminium Inorganic materials 0.000 claims description 3
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- OGPBJKLSAFTDLK-UHFFFAOYSA-N europium atom Chemical compound [Eu] OGPBJKLSAFTDLK-UHFFFAOYSA-N 0.000 claims description 3
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 claims description 3
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- 238000011065 in-situ storage Methods 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 3
- OHSVLFRHMCKCQY-UHFFFAOYSA-N lutetium atom Chemical compound [Lu] OHSVLFRHMCKCQY-UHFFFAOYSA-N 0.000 claims description 3
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 3
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 claims description 3
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 claims description 3
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 claims description 3
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 claims description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 2
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 description 37
- 239000004065 semiconductor Substances 0.000 description 37
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- 238000005530 etching Methods 0.000 description 15
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- 238000009792 diffusion process Methods 0.000 description 9
- 229910000449 hafnium oxide Inorganic materials 0.000 description 9
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
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- 229910052760 oxygen Inorganic materials 0.000 description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- NFHFRUOZVGFOOS-UHFFFAOYSA-N palladium;triphenylphosphane Chemical compound [Pd].C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 NFHFRUOZVGFOOS-UHFFFAOYSA-N 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012705 liquid precursor Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
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- 238000001020 plasma etching Methods 0.000 description 2
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- 239000000243 solution Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- LKZQVAFXXIATRL-UHFFFAOYSA-N C(C)[Hf]NC Chemical compound C(C)[Hf]NC LKZQVAFXXIATRL-UHFFFAOYSA-N 0.000 description 1
- YWATTXMDZQWERV-UHFFFAOYSA-N CN(C)[Hf] Chemical compound CN(C)[Hf] YWATTXMDZQWERV-UHFFFAOYSA-N 0.000 description 1
- OEZJRMFFFWXQJL-UHFFFAOYSA-N COCC(C)(O[Hf])C Chemical compound COCC(C)(O[Hf])C OEZJRMFFFWXQJL-UHFFFAOYSA-N 0.000 description 1
- 229910019044 CoSix Inorganic materials 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- DBOSVWZVMLOAEU-UHFFFAOYSA-N [O-2].[Hf+4].[La+3] Chemical compound [O-2].[Hf+4].[La+3] DBOSVWZVMLOAEU-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- MIQVEZFSDIJTMW-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O-2].[Al+3].[Hf+4] MIQVEZFSDIJTMW-UHFFFAOYSA-N 0.000 description 1
- BOIGHUSRADNYQR-UHFFFAOYSA-N aluminum;lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Al+3].[La+3] BOIGHUSRADNYQR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
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- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- VBCSQFQVDXIOJL-UHFFFAOYSA-N diethylazanide;hafnium(4+) Chemical compound [Hf+4].CC[N-]CC.CC[N-]CC.CC[N-]CC.CC[N-]CC VBCSQFQVDXIOJL-UHFFFAOYSA-N 0.000 description 1
- 125000002147 dimethylamino group Chemical group [H]C([H])([H])N(*)C([H])([H])[H] 0.000 description 1
- ZYLGGWPMIDHSEZ-UHFFFAOYSA-N dimethylazanide;hafnium(4+) Chemical compound [Hf+4].C[N-]C.C[N-]C.C[N-]C.C[N-]C ZYLGGWPMIDHSEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- WZVIPWQGBBCHJP-UHFFFAOYSA-N hafnium(4+);2-methylpropan-2-olate Chemical compound [Hf+4].CC(C)(C)[O-].CC(C)(C)[O-].CC(C)(C)[O-].CC(C)(C)[O-] WZVIPWQGBBCHJP-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
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- FRNOGLGSGLTDKL-UHFFFAOYSA-N thulium atom Chemical compound [Tm] FRNOGLGSGLTDKL-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31616—Deposition of Al2O3
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/314—Inorganic layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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- H01L21/31645—Deposition of Hafnium oxides, e.g. HfO2
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Definitions
- Embodiments of the present invention relate to a method of manufacturing a non-volatile memory device. More particularly, embodiments of the present invention relate to a method of manufacturing a non-volatile memory device having a blocking layer exhibiting reduced leakage current.
- semiconductor memory devices may be classified as either volatile or non-volatile memory devices.
- Volatile memory devices e.g., dynamic random access memory (DRAM) devices and/or static random access memory (SRAM) devices
- DRAM dynamic random access memory
- SRAM static random access memory
- non-volatile memory devices e.g., read-only memory (ROM) devices, electrically erasable programmable ROM (EEPROM) devices, and/or flash EEPROM devices
- ROM read-only memory
- EEPROM electrically erasable programmable ROM
- flash EEPROM devices may have relatively slow I/O speeds, and may be able to maintain data stored therein even when power is shut off.
- data may be electrically stored, i.e., programmed or erased, through a Fowler-Nordheim (F-N) tunneling mechanism and/or through a channel hot electron injection mechanism.
- F-N Fowler-Nordheim
- the conventional non-volatile memory device may be classified as either a floating gate type or a charge trap type, e.g., silicon-oxide-nitride-oxide semiconductor (SONOS) devices or metal-oxide-nitride-oxide semiconductor (MONOS) devices.
- the floating gate type non-volatile memory device may include a gate structure and source/drain regions on a semiconductor substrate.
- the conventional gate structure of the floating gate type non-volatile memory device may include a tunnel insulation layer, a floating gate electrode, a blocking layer, and a control gate electrode, while the blocking layer may have a multilayered dielectric structure including a silicon nitride layer between two silicon oxide layers.
- a metal oxide layer between two silicon oxide layers may increase diffusion of materials between the metal oxide layer and the silicon oxide layers, thereby deteriorating interface morphology therebetween.
- a deteriorated morphology between the layers of the blocking layer may increase leakage current through the blocking layer, thereby reducing operability and reliability of the non-volatile memory device.
- Embodiments of the present invention are therefore directed to a method of manufacturing a non-volatile memory device, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
- At least one of the above and other features of the present invention may be realized by providing a method of manufacturing a non-volatile memory device including forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface portion of the lower silicon oxide layer with a nitridation treatment to form a first silicon oxynitride layer on the lower silicon oxide layer, forming a metal oxide layer on the first silicon oxynitride layer, forming an upper silicon oxide layer on the metal oxide layer, and forming a conductive layer on the upper silicon oxide layer.
- Forming the metal oxide layer may include employing a metal oxide having a higher dielectric constant than silicon nitride.
- Forming the metal oxide layer may include employing one or more of hafnium, zirconium, tantalum, aluminum, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and/or lutetium.
- Treating the surface portion of the lower silicon oxide layer with the nitridation treatment may include performing a plasma nitridation treatment using nitrogen gas and/or ammonia gas.
- Treating the surface portion of the lower silicon oxide layer with the nitridation treatment may include using a remote plasma system or a direct plasma system. Treating the surface portion of the lower silicon oxide layer with the nitridation treatment may include processing at a temperature of about 500° C. or less. Treating the surface portion of the lower silicon oxide layer with the nitridation treatment may include forming the first silicon oxynitride layer to a thickness of about 5 angstroms to about 20 angstroms.
- the method may further include performing a plasma nitridation treatment on the metal oxide layer to form a metal oxynitride layer between the metal oxide layer and the upper silicon oxide layer.
- Performing the plasma nitridation treatment on the metal oxide layer may include processing at a temperature of about 500° C. or less.
- Performing the plasma nitridation treatment on the metal oxide layer may include processing at a temperature of about 350° C. or less.
- Performing the plasma nitridation treatment on the metal oxide layer may include processing at a temperature of about 250° C. to about 350° C.
- Performing the plasma nitridation treatment on the metal oxide layer may include forming the metal oxynitride layer to a thickness of about 5 angstroms to about 20 angstroms.
- the method may further include forming a second silicon oxynitride layer between the metal oxide layer and the upper silicon layer.
- the second silicon oxynitride layer may be formed directly on the metal oxide layer.
- Forming the second silicon oxynitride layer may include performing a middle temperature oxynitride deposition or a high density plasma deposition on the metal oxide layer.
- the second silicon oxynitride layer may be formed to a thickness of about 5 angstroms to about 20 angstroms. Forming the second silicon oxynitride layer may be performed in-situ with forming the upper silicon oxide layer.
- the method may further include forming a gate structure on the substrate by sequentially patterning the conductive layer, the upper silicon oxide layer, the metal oxide layer, the silicon oxynitride layer, the conductive pattern, and the tunnel isolation layer.
- the method may further include forming source/drain regions at surface portions of the substrate adjacent to the gate structure.
- FIGS. 1-10 illustrate cross-sectional views of sequential stages during manufacturing of a non-volatile memory device in accordance with an embodiment of the present invention
- FIG. 11 illustrates an enlarged, partial cross-sectional view of a blocking layer of a non-volatile memory device manufactured in accordance with another embodiment of the present invention
- FIG. 12 illustrates an enlarged, partial cross-sectional view of a blocking layer of a non-volatile memory device manufactured in accordance with another embodiment of the present invention.
- FIG. 13 illustrates a graph of leakage current characteristics of a non-volatile memory device in accordance with an embodiment of the present invention as compared to conventional non-volatile memory devices.
- FIGS. 1-10 An exemplary embodiment of a method of manufacturing a non-volatile memory device in accordance with the present invention will now be more fully described with reference to FIGS. 1-10 .
- a pad oxide layer 102 may be formed on a semiconductor substrate 100 , e.g., a silicon wafer, followed by formation of a mask layer 104 thereon. More specifically, the pad oxide layer 102 may be formed on the semiconductor substrate 100 to a thickness of about 70 angstroms to about 100 angstroms to facilitate surface treatment of the semiconductor substrate 100 .
- the pad oxide 102 may be formed by, e.g., a thermal oxidation process or a chemical vapor deposition (CVD) process, at a temperature of about 750° C. to about 900° C.
- the mask layer 104 may be formed of, e.g., silicon nitride, on the pad oxide layer 102 to a thickness of about 1,500 angstroms by, e.g., a plasma-enhanced CVD (PECVD) process or a low pressure CVD (LPCVD) process using a source gas including, e.g., dichlorosilane (SiH 2 Cl 2 ) gas, silane (SiH 4 ) gas, and/or ammonia (NH 3 ) gas.
- PECVD plasma-enhanced CVD
- LPCVD low pressure CVD
- a photoresist pattern 106 may be formed on the mask layer 104 by, e.g., a photolithography process, so predetermined portions of the mask layer 104 may be exposed through the photoresist pattern 106 . Then, portions of the mask layer 104 exposed through the photoresist pattern 106 and corresponding portions of the pad oxide layer 102 may be sequentially removed from the semiconductor substrate 100 to form a mask pattern 108 and an oxide pattern 110 , respectively, on the semiconductor substrate 100 , as illustrated in FIG. 2 .
- the oxide pattern 110 and the mask pattern 108 may define at least one first opening 112 , as further illustrated in FIG. 2 , so an upper surface of the semiconductor substrate 100 may be exposed to define a device isolation region 100 a.
- Portions of the mask layer 104 and the pad oxide layer 102 may be removed by, e.g., an etching process using the photoresist pattern 106 as an etching mask.
- the etching process may include, e.g., a dry etching process and/or a reactive ion etching process.
- the photoresist pattern 106 may be removed from the mask pattern 108 by, e.g., an ashing process and/or a strip process.
- the device isolation region 100 a may be etched by the etching process using the mask pattern 108 as an etching mask to form at least one trench 114 in the semiconductor substrate 100 .
- the trench 114 may extend the first opening 112 vertically in a first direction, i.e., from an upper surface of the semiconductor substrate 100 downward toward a lower surface thereof, to a predetermined depth.
- the trench 114 may be formed to a depth of about 1,000 angstroms to about 5,000 angstroms as measured from the upper surface of the semiconductor substrate 100 , i.e., an interface between the semiconductor substrate 100 and the oxide pattern 110 .
- the trench 114 may be formed in the semiconductor substrate 100 using the photoresist pattern 106 as an etching mask, are within the scope of the present invention.
- Two adjacent trenches 114 may define an active region 100 b therebetween. More specifically, as further illustrated in FIG. 3 , the active region 100 b may be a portion of the semiconductor substrate 100 overlapping with the oxide pattern 110 and positioned between two adjacent trenches 114 .
- a thermal oxidation treatment may be performed on an inner surface thereof to minimize leakage current therethrough. More specifically, the etching process may damage the semiconductor substrate 100 , e.g., high energy ions may damage the silicon structure of the semiconductor substrate 100 during a reactive ion etching process, thereby triggering a leakage current in the semiconductor substrate 100 .
- the thermal oxidation treatment may form a trench oxide layer (not shown) on the inner surface of the trench 114 to a thickness of about 50 angstroms to about 250 angstroms in order to prevent or minimize damage to the silicon structure.
- a nitride liner (not shown) may be formed on the trench oxide layer to a thickness of about 50 angstroms to about 100 angstroms, so that diffusion of impurities, e.g., carbon (C) and/or hydrogen (H), into the active region 100 b may be prevented or substantially minimized.
- a field isolation layer (not shown) may be formed on the semiconductor substrate 100 to a sufficient thickness to fill up the trench 114 .
- the field isolation layer may include a silicon oxide layer, e.g., an undoped silicate glass (USG) layer, a tetraethyl orthosilicate (TEOS) layer, and/or a high-density plasma (HDP) oxide layer, and may be formed by an HDP process using, e.g., silane (SiH 4 ), oxygen (O 2 ), and/or argon (Ar) as a plasma source gas.
- silane SiH 4
- oxygen oxygen
- Ar argon
- the field isolation layer may be partially removed by a planarization process, e.g., chemical mechanical polishing (CMP) process, to expose an upper surface of the mask pattern 108 , so that the field isolation layer may remain only in the trench 114 to form a field isolation pattern 116 therein.
- the field isolation pattern 116 may electrically isolate conductive structures, e.g., unit devices of a memory device, formed on the active region 100 b of the semiconductor substrate 100 .
- the mask pattern 108 may be partially removed from the semiconductor substrate 100 during the planarization process.
- the mask pattern 108 and the pad oxide pattern 110 may be removed from the semiconductor substrate 100 to form at least one second opening 118 . More specifically, the second opening 118 may be formed between adjacent field isolation patterns 116 to expose an upper surface of the active region 100 b , as illustrated in FIG. 5 .
- the mask pattern 108 may be removed by, e.g., a wet etching process with a phosphoric acid solution.
- the pad oxide pattern 110 may be removed by, e.g., a wet etching process with a diluted HF solution.
- Portions of the field isolation pattern 116 may be also removed from the substrate 100 during the etching process of the mask pattern 108 and pad oxide pattern 110 . For example, portions of the field isolation pattern 116 may be removed, so the second opening 118 may be wider than the active region 100 b , as further illustrated in FIG. 5 .
- a tunnel oxide layer 120 may be formed on the active region 100 b of the semiconductor substrate 100 .
- the tunnel oxide layer 120 may include pure silicon oxide, silicon oxide doped with fluorine (F), silicon oxide doped with carbon (C), and/or a low-k material having a low dielectric constant.
- the tunnel oxide layer 120 may be formed on the active region 100 b of the semiconductor substrate 100 to a thickness of about 30 angstroms to about 100 angstroms.
- a first conductive layer (not shown) may be formed on the tunnel oxide layer 120 and the field isolation layer 116 to a sufficient thickness to fill up the second opening 118 .
- the first conductive layer may include, e.g., polysilicon doped with impurities, and may be formed at a temperature of about 580° C. to about 620° C. using, e.g., silane (SiH 4 ) gas and/or phosphine (PH 3 ) gas.
- the first conductive layer may be removed from the semiconductor substrate 100 by a planarization process, e.g., an etch-back process or a CMP process, to expose an upper surface of the field isolation pattern 116 , so that the first conductive pattern may remain only in the second opening 118 to form a conductive pattern 122 therein.
- the conductive pattern 122 may function as a floating gate pattern. Portions of the field isolation pattern 116 may be removed from the semiconductor substrate 100 during the planarization process.
- an upper portion of the field isolation pattern 116 may be removed from the semiconductor substrate 100 to expose upper portions of sidewalls of the conductive pattern 122 . More specifically, the upper portion of the field isolation pattern 116 may be removed by, e.g., an isotropic or an anisotropic etching process, to expose only upper portions of the conductive pattern 122 , as illustrated in FIG. 7 , so the tunnel oxide layer 120 may not be exposed. Therefore, the tunnel oxide layer 120 may be shielded from potential etching damage, e.g., an etchant or an etching gas. In addition, a corner portion of the conductive pattern 122 may be rounded during etching of the field isolation pattern 116 , as further illustrated in FIG. 7 .
- a blocking layer 124 may be formed on the conductive pattern 122 and the field isolation pattern 116 .
- the blocking layer 124 may have a multi-layered structure including a lower silicon oxide layer 126 , a silicon oxynitride layer 128 , a metal oxide layer 130 , and an upper silicon oxide layer 132 , as illustrated in FIG. 9 .
- the lower silicon oxide layer 126 may be formed on the conductive pattern 122 and the field isolation pattern 116 to a thickness of about 30 angstroms to about 150 angstroms by, e.g., a middle temperature oxide (MTO) deposition process or an HDP deposition process.
- MTO middle temperature oxide
- the silicon oxynitride layer 128 may be formed on the lower silicon oxide layer 126 to a thickness of about 5 angstroms to about 20 angstroms. More specifically, plasma nitridation treatment may be performed on an upper surface of the lower silicon oxide layer 126 , so a predetermined portion of the lower silicon oxide layer 126 , e.g., a thickness of about 5 angstroms to about 20 angstroms thereof, may be transformed into the silicon oxynitride layer 128 .
- a thickness below about 5 angstroms of the silicon oxynitride layer 128 may be insufficient to minimize diffusion through the silicon oxynitride layer 128 , while a thickness of more than about 20 angstroms of the silicon oxynitride layer 128 may decrease the dielectric constant of the blocking layer 124 . Formation of the silicon oxynitride layer 128 on the lower silicon oxide layer 126 may be advantageous in improving an interface morphology between the lower silicon oxide layer 126 and the metal oxide layer 130 .
- the plasma nitridation treatment on the lower silicon oxide layer 126 may be performed in a remote plasma system or in a direct plasma system using a gas including, e.g., nitrogen (N 2 ) or ammonia (NH 3 ) gas.
- the plasma nitridation treatment may be performed at a temperature of about 500° C. or lower, and preferably at a temperature of about 250° C. to about 350° C. If the plasma nitridation treatment is performed in a remote plasma system, a microwave having a frequency of about 2.45 GHz may be used as an energy source.
- the metal oxide layer 130 may be formed on the silicon oxynitride layer 128 to a thickness of about 20 angstroms to about 50 angstroms by an atomic layer deposition (ALD) process or a CVD process, and may have a higher dielectric constant than a silicon nitride layer.
- ALD atomic layer deposition
- CVD chemical vapor deposition
- the metal oxide layer 130 may include a metal, e.g., hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and so forth.
- a metal e.g., hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium
- Examples of the metal oxide layer 130 may include a hafnium oxide (HfO 2 ) layer, a zirconium oxide (ZrO 2 ) layer, an aluminum oxide (Al 2 O 3 ) layer, a hafnium aluminum oxide (HfAlO) layer, a lanthanum oxide (La 2 O 3 ) layer, a hafnium lanthanum oxide (HfLaO) layer, an aluminum lanthanum oxide (AlLaO) layer, and so forth.
- An exemplary method of forming the metal oxide layer 130 is as follows. It should be noted, however, that even though the exemplary method will be described with respect to formation of a hafnium oxide layer on the silicon oxynitride layer 128 by an ALD process, other materials or methods for forming the metal oxide layer 130 are within the scope of the present invention.
- the semiconductor substrate 100 including the silicon oxynitride layer 128 may be loaded into a process chamber (not shown) for the ALD process.
- the process chamber may be maintained at a temperature of about 150° C. to about 400° C. under a pressure of about 0.1 Torr to about 3.0 Torr.
- reaction materials i.e., precursors and carrier gases, may be provided onto the semiconductor substrate 100 in the process chamber for about 0.5 seconds to about 3 seconds.
- a liquid precursor e.g., a liquid hafnium precursor, a liquid delivery system (LDS) and a bubbler system may be used to modify the liquid precursor into a gaseous state.
- LDS liquid delivery system
- bubbler system may be used to modify the liquid precursor into a gaseous state.
- hafnium precursor gases may be carried into the process chamber by a carrier gas, e.g., nitrogen (N 2 ) gas and/or argon (Ar) gas, to form a hafnium precursor layer on the silicon oxynitride layer 128 .
- a carrier gas e.g., nitrogen (N 2 ) gas and/or argon (Ar) gas
- hafnium precursor gas may include tetrakis dimethylamino hafnium (TDMAH, Hf[N(CH 3 ) 2 ] 4 ), tetrakis ethyl methylamino hafnium (TEMAH, Hf[N(C 2 H 5 )CH 3 ] 4 ), tetrakis diethylamino hafnium (TDEAH, Hf[N(C 2 H 5 ) 2 ] 4 ), tetrakis 1-methoxy-2-methyl-2-propoxy hafnium (Hf-MMP, Hf[OC(CH 3 ) 2 CH 2 OCH 3 ] 4 ), hafnium tertiary butoxide (HTB, Hf[OC(CH 3 ) 3 ] 4 ), and/or a mixture thereof.
- TDMAH tetrakis dimethylamino hafnium
- TEMAH tetrakis ethyl methylamino haf
- Provision of the reaction materials onto the semiconductor substrate 100 may facilitate chemisorption of some of the reaction materials onto the silicon oxynitride layer 128 to form the hafnium precursor layer thereon.
- the remaining reaction materials may be physisorbed onto the hafnium precursor layer or may remain in the process chamber.
- a first purge gas e.g., nitrogen (N 2 ) gas and argon (Ar) gas
- N 2 nitrogen
- Ar argon
- an oxidizer may be provided onto the semiconductor substrate 100 in the process chamber, so that the hafnium precursor layer may be oxidized by the oxidizer to form a hafnium oxide layer on the silicon oxynitride layer 128 .
- the oxidizer may include oxygen (O 2 ), ozone (O 3 ), water vapor (H 2 O), and/or plasma oxygen (O 2 ).
- oxygen (O 2 ) may be provided onto the substrate 100 for about 1 second to about 5 seconds.
- a second purge gas may be provided into the process chamber to remove by-products of the hafnium precursor layer and the oxidizer and a residual oxidizer. The second purge gas may be provided into the process chamber for about 1 second to about 5 seconds.
- the ALD process for forming the metal oxide layer 130 may be performed on the semiconductor substrate 100 to complete a unit cycle, i.e., form the hafnium oxide layer to a predetermined thickness in a single deposition cycle.
- the ALD process may be repeated as determined by one of ordinary skill in the art, i.e., perform multiple unit cycles, to form the hafnium oxide layer with a desired thickness.
- the unit cycle of the ALD process may be repeated to form the metal oxide layer 130 to have a thickness of about 50 angstroms or less.
- a metal oxide layer 130 having a thickness of above about 50 angstroms may be crystallized in a subsequent process.
- the upper silicon oxide layer 132 may be formed on the metal oxide layer 130 to a thickness of about 30 angstroms to about 150 angstroms by, e.g., an MTO deposition process or a HDP deposition process.
- the silicon oxynitride layer 128 between the lower silicon oxide layer 126 and the metal oxide layer 130 may prevent or substantially minimize diffusion of materials therebetween.
- the mutual diffusion of silicon and metal may be sufficiently minimized between the silicon oxynitride layer 128 and the metal oxide layer 130 , so that the interface morphology therebetween may be improved, thereby decreasing leakage current through the blocking layer 124 .
- a second conductive layer (not shown) may be formed on the blocking layer 124 .
- the second conductive layer may include at least one conductive material, such as polysilicon doped with impurities, metal, e.g., tungsten (W), and/or metal silicide, e.g., tungsten silicide (WSi x ), titanium silicide (TiSi x ), cobalt silicide (CoSi x ), and/or tantalum silicide (TaSi x ).
- the second conductive layer may be patterned by, e.g., an etching process, to form a control gate electrode 134 extending in a second direction, e.g., a direction perpendicular to the first direction.
- the blocking layer 124 , the conductive pattern 122 , and the tunnel oxide layer 120 may be sequentially patterned by an etching process to form a blocking pattern 136 , a floating gate electrode 138 , and a tunnel oxide pattern 140 , respectively, so a gate structure 142 including the control gate electrode 134 of a non-volatile memory device may be formed.
- source/drain regions may be formed on surface portions of the active region 100 b of the semiconductor substrate 100 and adjacent to the gate structure 142 by, e.g., an ion implantation process and a heat treatment for activating impurities.
- a method of manufacturing a non-volatile memory device may be substantially similar to the method described previously with respect to FIGS. 1-10 with the exception of forming a blocking layer 224 to include a metal oxynitride layer 232 .
- a non-volatile memory device may include a field isolation pattern 216 , a tunnel isolation layer 220 , a conductive pattern 222 , a blocking layer 224 , and a control gate electrode 236 on a semiconductor substrate 200 .
- the field isolation pattern 216 , tunnel isolation layer 220 , conductive pattern 222 , and control gate electrode 236 may be substantially similar to the field isolation pattern 116 , tunnel isolation layer 120 , conductive pattern 122 , and control gate electrode 136 , respectively, described previously with reference to FIGS. 1-10 , and thus, their detailed description will non be repeated herein.
- the blocking layer 224 may be formed on the field isolation pattern 216 and the conductive pattern 222 , and may include a lower silicon oxide layer 226 , a silicon oxynitride layer 228 , a metal oxide layer 230 , a metal oxynitride layer 232 , and an upper silicon oxide layer 234 .
- the lower silicon oxide layer 226 , silicon oxynitride layer 228 , metal oxide layer 230 , and upper silicon oxide layer 234 may be substantially similar to the lower silicon oxide layer 126 , silicon oxynitride layer 128 , metal oxide layer 130 , and upper silicon oxide layer 134 , respectively, described previously with reference to FIGS. 8-9 , and thus, their detailed descriptions will not be repeated herein.
- the nitridation treatment may be performed on the metal oxide layer 230 to form the metal oxynitride layer 232 on a surface of the metal oxide layer 230 .
- the metal oxynitride layer 232 may be formed to a thickness of about 5 angstroms to about 20 angstroms by, e.g., a plasma nitridation treatment, in order to improve an interface morphology between the metal oxide layer 230 and the upper silicon oxide layer 234 .
- the dielectric constant of the blocking layer 224 may be decreased.
- the plasma nitridation treatment may be performed in a remote plasma system or in a direct plasma system using, e.g., nitrogen (N 2 ) gas or ammonia gas (NH 3 ) gas. If the plasma nitridation treatment is performed in a remote plasma system, a microwave having a frequency of about 2.45 GHz may be employed as an energy source.
- a temperature of the plasma nitridation treatment may be determined with respect to the materials employed in the metal oxide layer 230 , and preferably at a temperature of no more than about 500° C. to prevent crystallization of the metal oxide layer 230 . For example, if zirconium oxide is used to form the metal oxide layer 23 , a temperature of no more than about 350° C.
- the control gate electrode 236 is formed thereon, followed by patterning the blocking layer 224 , conductive pattern 222 , and tunnel oxide layer 220 , and formation of source/drain regions on surface portions of the substrate 200 to complete formation of the non-volatile memory device.
- Formation of the metal oxynitride layer 232 between the metal oxide layer 230 and the upper silicon oxide layer 234 may be advantageous in minimizing diffusion of silicon and/or metal therebetween, thereby improving the interface morphology between the upper silicon oxide layer 234 and the metal oxide layer 230 and decreasing the leakage current through the blocking layer 234 .
- a method of manufacturing a non-volatile memory device may be substantially similar to the method described previously with respect to FIG. 11 , with the exception of forming a blocking layer 324 to include first and second silicon oxynitride layers 328 and 332 , instead of the silicon and metal oxynitride layers 228 and 232 .
- a non-volatile memory device may include a field isolation pattern 316 , a tunnel isolation layer 320 , a conductive pattern 322 , a blocking layer 324 , and a control gate electrode 336 on a semiconductor substrate 300 .
- the processing steps for forming the field isolation pattern 316 , tunnel isolation layer 320 , conductive pattern 322 , and control gate electrode 336 may be substantially similar to steps used to from the field isolation pattern 216 , tunnel isolation layer 220 , conductive pattern 222 , and control gate electrode 236 , respectively, described previously with reference to FIG. 11 , and thus, their detailed description will non be repeated herein.
- the blocking layer 324 may be formed on the field isolation pattern 316 and the conductive pattern 322 , and may include a lower silicon oxide layer 326 , a first silicon oxynitride layer 328 , a metal oxide layer 330 , a second silicon oxynitride layer 332 , and an upper silicon oxide layer 334 .
- the processing steps for forming the lower silicon oxide layer 326 , first silicon oxynitride layer 328 , metal oxide layer 330 , and upper silicon oxide layer 334 may be substantially similar to the steps described previously with reference to FIG. 11 , and thus, their detailed descriptions will not be repeated herein.
- the second silicon oxynitride layer 332 may be formed on the metal oxide layer 330 by a middle temperature oxynitride deposition process or an HDP deposition process using a source gas including silicon (Si), a first processing gas including oxygen (O 2 ) gas, and a second processing gas including nitrogen (N 2 ) gas.
- the second silicon oxynitride layer 332 may be formed to a thickness of about 5 angstroms to about 20 angstroms, and the upper silicon oxide layer 334 may be formed in-situ with the second silicon oxynitride layer 332 .
- the upper silicon oxide layer 334 may be formed on the second silicon oxynitride layer 332 to a thickness of about 30 angstroms to about 150 angstroms.
- control gate electrode 336 may be formed thereon, followed by patterning the blocking layer 324 , the conductive pattern 322 , and the tunnel oxide layer 320 , and formation of source/drain regions on surface portions of the substrate 300 to complete formation of the non-volatile memory device.
- Formation of the silicon oxynitride layer 332 between the metal oxide layer 330 and the upper silicon oxide layer 334 may be advantageous in minimizing diffusion of silicon and/or metal therebetween, thereby improving the interface morphology between the upper silicon oxide layer 334 and the metal oxide layer 330 , and decreasing the leakage current through the blocking layer 334 .
- a non-volatile memory device i.e., Example 1 was manufactured to include a blocking layer in accordance with an embodiment of the present invention and compared to two conventional non-volatile memory device, i.e., Comparative Examples 1-2.
- the three non-volatile memory devices were manufactured to include a tunnel isolation layer, a conductive pattern, a blocking layer, and a conductive layer formed sequentially on a silicon semiconductor substrate, followed by patterning thereof to form a gate structure on the substrate. Impurity ions were implanted into surface portions of the substrate adjacent to the gate structure to form source/drain regions. Formation of all elements of the three non-volatile memory devices was substantially identical with the exception of formation of the blocking layer of each non-volatile memory device.
- the blocking layer was formed as follows. A lower silicon oxide layer was deposited on the conductive pattern to a thickness of 61 angstroms. Then, a plasma nitridation process was performed on the lower silicon oxide layer to form a silicon oxynitride layer thereon. Next, a hafnium oxide layer was formed on the silicon oxynitride layer to a thickness of 50 angstroms, and an upper silicon oxide layer was formed on the hafnium oxide layer to a thickness of 61 angstroms.
- the blocking layer was manufactured according to a conventional process, i.e., without a silicon oxynitride layer between the lower silicon oxide layer and the hafnium oxide layer.
- the materials and thicknesses of the lower silicon oxide layer, hafnium oxide layer, and upper silicon oxide layer were identical to those in Example 1.
- the blocking layer was manufactured according to a method used in Comparative Example 1, with the exception of forming the lower silicon oxide layer to a thickness of 52 angstroms instead of 61 angstroms.
- the three non-volatile memory devices were compared in terms of equivalent oxide thickness (EOT) and leakage current through the blocking layer.
- the first non-volatile memory device was measured to have an EOT of 127 angstroms
- the second non-volatile memory device was measured to have an EOT of 138 angstroms
- the third non-volatile memory device was measured to have an EOT of 128 angstroms. Results of leakage current through the blocking layer are illustrated in FIG. 13 .
- the first non-volatile memory device showed improved leakage current characteristics, i.e., a curve represented by a solid line, as compared to the non-volatile memory devices of Comparative Examples 1-2, i.e., curves represented by respective dotted and dot-dash lines.
- the first non-volatile memory device exhibited remarkably improved leakage current characteristics in a lower voltage area, i.e., between about 0 and 6 mV/cm, as compared with the second and third non-volatile memory devices.
- the second and third non-volatile memory devices exhibited leakage current of up to about 10 ⁇ 8 A/cm 2
- the first non-volatile memory device exhibited leakage current of about 10 ⁇ 9 A/cm 2 .
- Embodiments of the present invention may be advantageous in substantially minimizing or preventing mutual diffusion of silicon and metal between a lower silicon oxide layer and a metal oxide layer by forming a silicon oxynitride layer therebetween.
- mutual diffusion of silicon and metal between an upper silicon oxide layer and the metal oxide layer may be substantially minimized or prevented by forming a second silicon oxynitride layer or a metal oxynitride layer therebetween. Therefore, leakage current through a blocking layer may be substantially decreased, thereby improving data reliability of a non-volatile memory device.
- first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein to describe a relative relationship between elements and/or features with respect to the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below.
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US10776433B2 (en) * | 2016-09-29 | 2020-09-15 | Oath Inc. | User profile expansion for personalization and recommendation |
US10586705B2 (en) * | 2017-11-28 | 2020-03-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fluorine doped non-volatile memory cells and methods for forming the same |
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